xref: /linux/drivers/gpu/drm/msm/dsi/dsi.h (revision dceac340155b66b6c97cb802b03d4778dd82e9be)
1a689554bSHai Li /*
2a689554bSHai Li  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3a689554bSHai Li  *
4a689554bSHai Li  * This program is free software; you can redistribute it and/or modify
5a689554bSHai Li  * it under the terms of the GNU General Public License version 2 and
6a689554bSHai Li  * only version 2 as published by the Free Software Foundation.
7a689554bSHai Li  *
8a689554bSHai Li  * This program is distributed in the hope that it will be useful,
9a689554bSHai Li  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10a689554bSHai Li  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11a689554bSHai Li  * GNU General Public License for more details.
12a689554bSHai Li  */
13a689554bSHai Li 
14a689554bSHai Li #ifndef __DSI_CONNECTOR_H__
15a689554bSHai Li #define __DSI_CONNECTOR_H__
16a689554bSHai Li 
17ec31abf6SHai Li #include <linux/of_platform.h>
18a689554bSHai Li #include <linux/platform_device.h>
19a689554bSHai Li 
20a689554bSHai Li #include "drm_crtc.h"
21a689554bSHai Li #include "drm_mipi_dsi.h"
22a689554bSHai Li #include "drm_panel.h"
23a689554bSHai Li 
24a689554bSHai Li #include "msm_drv.h"
25a689554bSHai Li 
26a689554bSHai Li #define DSI_0	0
27a689554bSHai Li #define DSI_1	1
28a689554bSHai Li #define DSI_MAX	2
29a689554bSHai Li 
30*dceac340SHai Li struct msm_dsi_phy_shared_timings;
31*dceac340SHai Li 
329d32c498SHai Li enum msm_dsi_phy_type {
339d32c498SHai Li 	MSM_DSI_PHY_28NM_HPM,
349d32c498SHai Li 	MSM_DSI_PHY_28NM_LP,
35dcefc117SHai Li 	MSM_DSI_PHY_20NM,
36225380b3SArchit Taneja 	MSM_DSI_PHY_28NM_8960,
379d32c498SHai Li 	MSM_DSI_PHY_MAX
389d32c498SHai Li };
399d32c498SHai Li 
40ec31abf6SHai Li #define DSI_DEV_REGULATOR_MAX	8
416e0eb52eSArchit Taneja #define DSI_BUS_CLK_MAX		4
42ec31abf6SHai Li 
43ec31abf6SHai Li /* Regulators for DSI devices */
44ec31abf6SHai Li struct dsi_reg_entry {
45ec31abf6SHai Li 	char name[32];
46ec31abf6SHai Li 	int enable_load;
47ec31abf6SHai Li 	int disable_load;
48ec31abf6SHai Li };
49ec31abf6SHai Li 
50ec31abf6SHai Li struct dsi_reg_config {
51ec31abf6SHai Li 	int num;
52ec31abf6SHai Li 	struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX];
53ec31abf6SHai Li };
54ec31abf6SHai Li 
55a689554bSHai Li struct msm_dsi {
56a689554bSHai Li 	struct drm_device *dev;
57a689554bSHai Li 	struct platform_device *pdev;
58a689554bSHai Li 
59c118e290SArchit Taneja 	/* connector managed by us when we're connected to a drm_panel */
60a689554bSHai Li 	struct drm_connector *connector;
61c118e290SArchit Taneja 	/* internal dsi bridge attached to MDP interface */
62a689554bSHai Li 	struct drm_bridge *bridge;
63a689554bSHai Li 
64a689554bSHai Li 	struct mipi_dsi_host *host;
65a689554bSHai Li 	struct msm_dsi_phy *phy;
66c118e290SArchit Taneja 
67c118e290SArchit Taneja 	/*
68c118e290SArchit Taneja 	 * panel/external_bridge connected to dsi bridge output, only one of the
69c118e290SArchit Taneja 	 * two can be valid at a time
70c118e290SArchit Taneja 	 */
71a689554bSHai Li 	struct drm_panel *panel;
72c118e290SArchit Taneja 	struct drm_bridge *external_bridge;
73a9ddac9cSArchit Taneja 	unsigned long device_flags;
749d32c498SHai Li 
75ec31abf6SHai Li 	struct device *phy_dev;
76a689554bSHai Li 	bool phy_enabled;
77a689554bSHai Li 
7897e00119SArchit Taneja 	/* the encoder we are hooked to (outside of dsi block) */
7997e00119SArchit Taneja 	struct drm_encoder *encoder;
80a689554bSHai Li 
81a689554bSHai Li 	int id;
82a689554bSHai Li };
83a689554bSHai Li 
84a689554bSHai Li /* dsi manager */
85a689554bSHai Li struct drm_bridge *msm_dsi_manager_bridge_init(u8 id);
86a689554bSHai Li void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge);
87a689554bSHai Li struct drm_connector *msm_dsi_manager_connector_init(u8 id);
88c118e290SArchit Taneja struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
89a689554bSHai Li int msm_dsi_manager_phy_enable(int id,
90a689554bSHai Li 		const unsigned long bit_rate, const unsigned long esc_rate,
91*dceac340SHai Li 		struct msm_dsi_phy_shared_timings *shared_timing);
92a689554bSHai Li void msm_dsi_manager_phy_disable(int id);
93a689554bSHai Li int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
944ff9d4cbSArchit Taneja bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
959c9f6f8dSArchit Taneja void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
96a689554bSHai Li int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
97a689554bSHai Li void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
98a689554bSHai Li 
99a689554bSHai Li /* msm dsi */
1006f054ec5SArchit Taneja static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
1016f054ec5SArchit Taneja {
102c118e290SArchit Taneja 	return msm_dsi->panel || msm_dsi->external_bridge;
1036f054ec5SArchit Taneja }
1046f054ec5SArchit Taneja 
105a689554bSHai Li struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
106a689554bSHai Li 
1079d32c498SHai Li /* dsi pll */
1089d32c498SHai Li struct msm_dsi_pll;
1099d32c498SHai Li #ifdef CONFIG_DRM_MSM_DSI_PLL
1109d32c498SHai Li struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
1119d32c498SHai Li 			enum msm_dsi_phy_type type, int dsi_id);
1129d32c498SHai Li void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
1139d32c498SHai Li int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
1149d32c498SHai Li 	struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
115328e1a63SHai Li void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
116328e1a63SHai Li int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
1179d32c498SHai Li #else
1189d32c498SHai Li static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
1199d32c498SHai Li 			 enum msm_dsi_phy_type type, int id) {
1209d32c498SHai Li 	return ERR_PTR(-ENODEV);
1219d32c498SHai Li }
1229d32c498SHai Li static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
1239d32c498SHai Li {
1249d32c498SHai Li }
1259d32c498SHai Li static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
1269d32c498SHai Li 	struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
1279d32c498SHai Li {
1289d32c498SHai Li 	return -ENODEV;
1299d32c498SHai Li }
130328e1a63SHai Li static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
131328e1a63SHai Li {
132328e1a63SHai Li }
133328e1a63SHai Li static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
134328e1a63SHai Li {
135328e1a63SHai Li 	return 0;
136328e1a63SHai Li }
1379d32c498SHai Li #endif
1389d32c498SHai Li 
139a689554bSHai Li /* dsi host */
140a689554bSHai Li int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
141a689554bSHai Li 					const struct mipi_dsi_msg *msg);
142a689554bSHai Li void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
143a689554bSHai Li 					const struct mipi_dsi_msg *msg);
144a689554bSHai Li int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
145a689554bSHai Li 					const struct mipi_dsi_msg *msg);
146a689554bSHai Li int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
147a689554bSHai Li 					const struct mipi_dsi_msg *msg);
148a689554bSHai Li void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host,
1494ff9d4cbSArchit Taneja 					u32 dma_base, u32 len);
150a689554bSHai Li int msm_dsi_host_enable(struct mipi_dsi_host *host);
151a689554bSHai Li int msm_dsi_host_disable(struct mipi_dsi_host *host);
152a689554bSHai Li int msm_dsi_host_power_on(struct mipi_dsi_host *host);
153a689554bSHai Li int msm_dsi_host_power_off(struct mipi_dsi_host *host);
154a689554bSHai Li int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
155a689554bSHai Li 					struct drm_display_mode *mode);
156a689554bSHai Li struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
157a689554bSHai Li 					unsigned long *panel_flags);
158c118e290SArchit Taneja struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
159a689554bSHai Li int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer);
160a689554bSHai Li void msm_dsi_host_unregister(struct mipi_dsi_host *host);
1619d32c498SHai Li int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1629d32c498SHai Li 			struct msm_dsi_pll *src_pll);
163a689554bSHai Li void msm_dsi_host_destroy(struct mipi_dsi_host *host);
164a689554bSHai Li int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
165a689554bSHai Li 					struct drm_device *dev);
166a689554bSHai Li int msm_dsi_host_init(struct msm_dsi *msm_dsi);
167a689554bSHai Li 
168a689554bSHai Li /* dsi phy */
169a689554bSHai Li struct msm_dsi_phy;
170*dceac340SHai Li struct msm_dsi_phy_shared_timings {
171*dceac340SHai Li 	u32 clk_post;
172*dceac340SHai Li 	u32 clk_pre;
173*dceac340SHai Li 	bool clk_pre_inc_by_2;
174*dceac340SHai Li };
175ec31abf6SHai Li void msm_dsi_phy_driver_register(void);
176ec31abf6SHai Li void msm_dsi_phy_driver_unregister(void);
17713351cd1SHai Li int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
178a689554bSHai Li 	const unsigned long bit_rate, const unsigned long esc_rate);
17929e61690SHai Li void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
180*dceac340SHai Li void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
181*dceac340SHai Li 			struct msm_dsi_phy_shared_timings *shared_timing);
1829d32c498SHai Li struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
1839d32c498SHai Li 
184a689554bSHai Li #endif /* __DSI_CONNECTOR_H__ */
185a689554bSHai Li 
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