xref: /linux/drivers/gpu/drm/msm/dsi/dsi.h (revision 6b16f05aa39f9fae43c18d4fd1ddad7988ab6d90)
197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2a689554bSHai Li /*
3a689554bSHai Li  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4a689554bSHai Li  */
5a689554bSHai Li 
6a689554bSHai Li #ifndef __DSI_CONNECTOR_H__
7a689554bSHai Li #define __DSI_CONNECTOR_H__
8a689554bSHai Li 
9ec31abf6SHai Li #include <linux/of_platform.h>
10a689554bSHai Li #include <linux/platform_device.h>
11a689554bSHai Li 
12ee68c743SBoris Brezillon #include <drm/drm_bridge.h>
1378f27b1cSMasahiro Yamada #include <drm/drm_crtc.h>
1478f27b1cSMasahiro Yamada #include <drm/drm_mipi_dsi.h>
1578f27b1cSMasahiro Yamada #include <drm/drm_panel.h>
16a689554bSHai Li 
17a689554bSHai Li #include "msm_drv.h"
18a689554bSHai Li 
19a689554bSHai Li #define DSI_0	0
20a689554bSHai Li #define DSI_1	1
21a689554bSHai Li #define DSI_MAX	2
22a689554bSHai Li 
23dceac340SHai Li struct msm_dsi_phy_shared_timings;
24b62aa70aSHai Li struct msm_dsi_phy_clk_request;
25dceac340SHai Li 
269d32c498SHai Li enum msm_dsi_phy_type {
279d32c498SHai Li 	MSM_DSI_PHY_28NM_HPM,
289d32c498SHai Li 	MSM_DSI_PHY_28NM_LP,
29dcefc117SHai Li 	MSM_DSI_PHY_20NM,
30225380b3SArchit Taneja 	MSM_DSI_PHY_28NM_8960,
31f079f6d9SArchit Taneja 	MSM_DSI_PHY_14NM,
32973e02dbSArchit Taneja 	MSM_DSI_PHY_10NM,
339d32c498SHai Li 	MSM_DSI_PHY_MAX
349d32c498SHai Li };
359d32c498SHai Li 
3657bf4338SHai Li enum msm_dsi_phy_usecase {
3757bf4338SHai Li 	MSM_DSI_PHY_STANDALONE,
3857bf4338SHai Li 	MSM_DSI_PHY_MASTER,
3957bf4338SHai Li 	MSM_DSI_PHY_SLAVE,
4057bf4338SHai Li };
4157bf4338SHai Li 
42ec31abf6SHai Li #define DSI_DEV_REGULATOR_MAX	8
436e0eb52eSArchit Taneja #define DSI_BUS_CLK_MAX		4
44ec31abf6SHai Li 
45ec31abf6SHai Li /* Regulators for DSI devices */
46ec31abf6SHai Li struct dsi_reg_entry {
47ec31abf6SHai Li 	char name[32];
48ec31abf6SHai Li 	int enable_load;
49ec31abf6SHai Li 	int disable_load;
50ec31abf6SHai Li };
51ec31abf6SHai Li 
52ec31abf6SHai Li struct dsi_reg_config {
53ec31abf6SHai Li 	int num;
54ec31abf6SHai Li 	struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX];
55ec31abf6SHai Li };
56ec31abf6SHai Li 
57a689554bSHai Li struct msm_dsi {
58a689554bSHai Li 	struct drm_device *dev;
59a689554bSHai Li 	struct platform_device *pdev;
60a689554bSHai Li 
61c118e290SArchit Taneja 	/* connector managed by us when we're connected to a drm_panel */
62a689554bSHai Li 	struct drm_connector *connector;
63c118e290SArchit Taneja 	/* internal dsi bridge attached to MDP interface */
64a689554bSHai Li 	struct drm_bridge *bridge;
65a689554bSHai Li 
66a689554bSHai Li 	struct mipi_dsi_host *host;
67a689554bSHai Li 	struct msm_dsi_phy *phy;
68c118e290SArchit Taneja 
69c118e290SArchit Taneja 	/*
70c118e290SArchit Taneja 	 * panel/external_bridge connected to dsi bridge output, only one of the
71c118e290SArchit Taneja 	 * two can be valid at a time
72c118e290SArchit Taneja 	 */
73a689554bSHai Li 	struct drm_panel *panel;
74c118e290SArchit Taneja 	struct drm_bridge *external_bridge;
759d32c498SHai Li 
76ec31abf6SHai Li 	struct device *phy_dev;
77a689554bSHai Li 	bool phy_enabled;
78a689554bSHai Li 
7997e00119SArchit Taneja 	/* the encoder we are hooked to (outside of dsi block) */
8097e00119SArchit Taneja 	struct drm_encoder *encoder;
81a689554bSHai Li 
82a689554bSHai Li 	int id;
83a689554bSHai Li };
84a689554bSHai Li 
85a689554bSHai Li /* dsi manager */
86a689554bSHai Li struct drm_bridge *msm_dsi_manager_bridge_init(u8 id);
87a689554bSHai Li void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge);
88a689554bSHai Li struct drm_connector *msm_dsi_manager_connector_init(u8 id);
89c118e290SArchit Taneja struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
90a689554bSHai Li int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
914ff9d4cbSArchit Taneja bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
9203436e3eSSean Paul void msm_dsi_manager_setup_encoder(int id);
93a689554bSHai Li int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
94a689554bSHai Li void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
958b03ad30SChandan Uddaraju bool msm_dsi_manager_validate_current_config(u8 id);
96a689554bSHai Li 
97a689554bSHai Li /* msm dsi */
986f054ec5SArchit Taneja static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
996f054ec5SArchit Taneja {
100c118e290SArchit Taneja 	return msm_dsi->panel || msm_dsi->external_bridge;
1016f054ec5SArchit Taneja }
1026f054ec5SArchit Taneja 
103a689554bSHai Li struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
104a689554bSHai Li 
1059d32c498SHai Li /* dsi pll */
1069d32c498SHai Li struct msm_dsi_pll;
1079d32c498SHai Li #ifdef CONFIG_DRM_MSM_DSI_PLL
1089d32c498SHai Li struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
1099d32c498SHai Li 			enum msm_dsi_phy_type type, int dsi_id);
1109d32c498SHai Li void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
1119d32c498SHai Li int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
1129d32c498SHai Li 	struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
113328e1a63SHai Li void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
114328e1a63SHai Li int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
115f079f6d9SArchit Taneja int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
116f079f6d9SArchit Taneja 			    enum msm_dsi_phy_usecase uc);
1179d32c498SHai Li #else
1189d32c498SHai Li static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
1199d32c498SHai Li 			 enum msm_dsi_phy_type type, int id) {
1209d32c498SHai Li 	return ERR_PTR(-ENODEV);
1219d32c498SHai Li }
1229d32c498SHai Li static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
1239d32c498SHai Li {
1249d32c498SHai Li }
1259d32c498SHai Li static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
1269d32c498SHai Li 	struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
1279d32c498SHai Li {
1289d32c498SHai Li 	return -ENODEV;
1299d32c498SHai Li }
130328e1a63SHai Li static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
131328e1a63SHai Li {
132328e1a63SHai Li }
133328e1a63SHai Li static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll)
134328e1a63SHai Li {
135328e1a63SHai Li 	return 0;
136328e1a63SHai Li }
137f079f6d9SArchit Taneja static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
138f079f6d9SArchit Taneja 					  enum msm_dsi_phy_usecase uc)
139f079f6d9SArchit Taneja {
140f079f6d9SArchit Taneja 	return -ENODEV;
141f079f6d9SArchit Taneja }
1429d32c498SHai Li #endif
1439d32c498SHai Li 
144a689554bSHai Li /* dsi host */
145e18177ccSSibi Sankar struct msm_dsi_host;
146a689554bSHai Li int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
147a689554bSHai Li 					const struct mipi_dsi_msg *msg);
148a689554bSHai Li void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
149a689554bSHai Li 					const struct mipi_dsi_msg *msg);
150a689554bSHai Li int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
151a689554bSHai Li 					const struct mipi_dsi_msg *msg);
152a689554bSHai Li int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
153a689554bSHai Li 					const struct mipi_dsi_msg *msg);
154a689554bSHai Li void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host,
1554ff9d4cbSArchit Taneja 					u32 dma_base, u32 len);
156a689554bSHai Li int msm_dsi_host_enable(struct mipi_dsi_host *host);
157a689554bSHai Li int msm_dsi_host_disable(struct mipi_dsi_host *host);
158b62aa70aSHai Li int msm_dsi_host_power_on(struct mipi_dsi_host *host,
159ed9976a0SChandan Uddaraju 			struct msm_dsi_phy_shared_timings *phy_shared_timings,
160ed9976a0SChandan Uddaraju 			bool is_dual_dsi);
161a689554bSHai Li int msm_dsi_host_power_off(struct mipi_dsi_host *host);
162a689554bSHai Li int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
16363f8f3baSLaurent Pinchart 				  const struct drm_display_mode *mode);
164e3a91f89SSean Paul struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host);
165e3a91f89SSean Paul unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host);
166c118e290SArchit Taneja struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
167a689554bSHai Li int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer);
168a689554bSHai Li void msm_dsi_host_unregister(struct mipi_dsi_host *host);
1699d32c498SHai Li int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1709d32c498SHai Li 			struct msm_dsi_pll *src_pll);
17134d9545bSArchit Taneja void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
172b62aa70aSHai Li void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
173ed9976a0SChandan Uddaraju 	struct msm_dsi_phy_clk_request *clk_req,
174ed9976a0SChandan Uddaraju 	bool is_dual_dsi);
175a689554bSHai Li void msm_dsi_host_destroy(struct mipi_dsi_host *host);
176a689554bSHai Li int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
177a689554bSHai Li 					struct drm_device *dev);
178a689554bSHai Li int msm_dsi_host_init(struct msm_dsi *msm_dsi);
179f54ca1a0SArchit Taneja int msm_dsi_runtime_suspend(struct device *dev);
180f54ca1a0SArchit Taneja int msm_dsi_runtime_resume(struct device *dev);
181*6b16f05aSRob Clark int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host);
182*6b16f05aSRob Clark int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host);
183c4d8cfe5SSibi Sankar int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
184c4d8cfe5SSibi Sankar int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
185c4d8cfe5SSibi Sankar void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
186c4d8cfe5SSibi Sankar void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
187c4d8cfe5SSibi Sankar int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
188c4d8cfe5SSibi Sankar int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
189c4d8cfe5SSibi Sankar void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
190c4d8cfe5SSibi Sankar void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host);
191c4d8cfe5SSibi Sankar void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host);
192c4d8cfe5SSibi Sankar int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
193c4d8cfe5SSibi Sankar int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
194c4d8cfe5SSibi Sankar int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
195c4d8cfe5SSibi Sankar int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
196ed9976a0SChandan Uddaraju int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
197ed9976a0SChandan Uddaraju int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
198a689554bSHai Li 
199a689554bSHai Li /* dsi phy */
200a689554bSHai Li struct msm_dsi_phy;
201dceac340SHai Li struct msm_dsi_phy_shared_timings {
202dceac340SHai Li 	u32 clk_post;
203dceac340SHai Li 	u32 clk_pre;
204dceac340SHai Li 	bool clk_pre_inc_by_2;
205dceac340SHai Li };
206b62aa70aSHai Li 
207b62aa70aSHai Li struct msm_dsi_phy_clk_request {
208b62aa70aSHai Li 	unsigned long bitclk_rate;
209b62aa70aSHai Li 	unsigned long escclk_rate;
210b62aa70aSHai Li };
211b62aa70aSHai Li 
212ec31abf6SHai Li void msm_dsi_phy_driver_register(void);
213ec31abf6SHai Li void msm_dsi_phy_driver_unregister(void);
21413351cd1SHai Li int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
215b62aa70aSHai Li 			struct msm_dsi_phy_clk_request *clk_req);
21629e61690SHai Li void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
217dceac340SHai Li void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
218dceac340SHai Li 			struct msm_dsi_phy_shared_timings *shared_timing);
2199d32c498SHai Li struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
22057bf4338SHai Li void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
22157bf4338SHai Li 			     enum msm_dsi_phy_usecase uc);
2229d32c498SHai Li 
223a689554bSHai Li #endif /* __DSI_CONNECTOR_H__ */
224a689554bSHai Li 
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