1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dp_panel.h" 7 #include "dp_reg.h" 8 #include "dp_utils.h" 9 10 #include <drm/drm_connector.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/io.h> 16 #include <linux/types.h> 17 #include <asm/byteorder.h> 18 19 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) 20 21 struct msm_dp_panel_private { 22 struct device *dev; 23 struct drm_device *drm_dev; 24 struct msm_dp_panel msm_dp_panel; 25 struct drm_dp_aux *aux; 26 struct msm_dp_link *link; 27 void __iomem *link_base; 28 void __iomem *p0_base; 29 bool panel_on; 30 }; 31 32 static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) 33 { 34 return readl_relaxed(panel->link_base + offset); 35 } 36 37 static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, 38 u32 offset, u32 data) 39 { 40 /* 41 * To make sure link reg writes happens before any other operation, 42 * this function uses writel() instread of writel_relaxed() 43 */ 44 writel(data, panel->link_base + offset); 45 } 46 47 static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, 48 u32 offset, u32 data) 49 { 50 /* 51 * To make sure interface reg writes happens before any other operation, 52 * this function uses writel() instread of writel_relaxed() 53 */ 54 writel(data, panel->p0_base + offset); 55 } 56 57 static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, 58 u32 offset) 59 { 60 /* 61 * To make sure interface reg writes happens before any other operation, 62 * this function uses writel() instread of writel_relaxed() 63 */ 64 return readl_relaxed(panel->p0_base + offset); 65 } 66 67 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) 68 { 69 ssize_t rlen; 70 struct msm_dp_panel *msm_dp_panel; 71 72 msm_dp_panel = &panel->msm_dp_panel; 73 74 /* edp sink */ 75 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 76 rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT, 77 &msm_dp_panel->psr_cap, sizeof(msm_dp_panel->psr_cap)); 78 if (rlen == sizeof(msm_dp_panel->psr_cap)) { 79 drm_dbg_dp(panel->drm_dev, 80 "psr version: 0x%x, psr_cap: 0x%x\n", 81 msm_dp_panel->psr_cap.version, 82 msm_dp_panel->psr_cap.capabilities); 83 } else 84 DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen); 85 } 86 } 87 88 static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel) 89 { 90 int rc, max_lttpr_lanes, max_lttpr_rate; 91 struct msm_dp_panel_private *panel; 92 struct msm_dp_link_info *link_info; 93 struct msm_dp_link *link; 94 u8 *dpcd, major, minor; 95 96 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 97 dpcd = msm_dp_panel->dpcd; 98 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); 99 if (rc) 100 return rc; 101 102 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); 103 link_info = &msm_dp_panel->link_info; 104 link_info->revision = dpcd[DP_DPCD_REV]; 105 major = (link_info->revision >> 4) & 0x0f; 106 minor = link_info->revision & 0x0f; 107 108 link = panel->link; 109 drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n", 110 link->max_dp_lanes, link->max_dp_link_rate); 111 112 max_lttpr_lanes = drm_dp_lttpr_max_lane_count(link->lttpr_common_caps); 113 max_lttpr_rate = drm_dp_lttpr_max_link_rate(link->lttpr_common_caps); 114 115 /* eDP sink */ 116 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 117 u8 edp_rev; 118 119 rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev); 120 if (rc) 121 return rc; 122 123 drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev); 124 125 /* For eDP v1.4+, parse the SUPPORTED_LINK_RATES table */ 126 if (edp_rev >= DP_EDP_14) { 127 __le16 rates[DP_MAX_SUPPORTED_RATES]; 128 u8 bw_set; 129 int i; 130 131 rc = drm_dp_dpcd_read_data(panel->aux, DP_SUPPORTED_LINK_RATES, 132 rates, sizeof(rates)); 133 if (rc) 134 return rc; 135 136 rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set); 137 if (rc) 138 return rc; 139 140 /* Find index of max supported link rate that does not exceed dtsi limits */ 141 for (i = 0; i < ARRAY_SIZE(rates); i++) { 142 /* 143 * The value from the DPCD multiplied by 200 gives 144 * the link rate in kHz. Divide by 10 to convert to 145 * symbol rate, accounting for 8b/10b encoding. 146 */ 147 u32 rate = (le16_to_cpu(rates[i]) * 200) / 10; 148 149 if (!rate) 150 break; 151 152 drm_dbg_dp(panel->drm_dev, 153 "SUPPORTED_LINK_RATES[%d]: %d\n", i, rate); 154 155 /* 156 * Limit link rate from link-frequencies of endpoint 157 * property of dtsi 158 */ 159 if (rate > link->max_dp_link_rate) 160 break; 161 162 /* Limit link rate from LTTPR capabilities, if any */ 163 if (max_lttpr_rate && rate > max_lttpr_rate) 164 break; 165 166 link_info->rate = rate; 167 link_info->supported_rates[i] = rate; 168 link_info->rate_set = i; 169 } 170 171 /* Only use LINK_RATE_SET if LINK_BW_SET hasn't already been written to */ 172 if (!bw_set && link_info->rate) 173 link_info->use_rate_set = true; 174 } 175 } 176 177 /* Fall back on MAX_LINK_RATE/LINK_BW_SET (DP, eDP <= v1.3) */ 178 if (!link_info->rate) { 179 link_info->rate = drm_dp_max_link_rate(dpcd); 180 181 /* Limit link rate from link-frequencies of endpoint property of dtsi */ 182 if (link_info->rate > link->max_dp_link_rate) 183 link_info->rate = link->max_dp_link_rate; 184 185 /* Limit link rate from LTTPR capabilities, if any */ 186 if (max_lttpr_rate && max_lttpr_rate < link_info->rate) 187 link_info->rate = max_lttpr_rate; 188 } 189 190 link_info->num_lanes = drm_dp_max_lane_count(dpcd); 191 192 /* Limit data lanes from data-lanes of endpoint property of dtsi */ 193 if (link_info->num_lanes > link->max_dp_lanes) 194 link_info->num_lanes = link->max_dp_lanes; 195 196 /* Limit data lanes from LTTPR capabilities, if any */ 197 if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes) 198 link_info->num_lanes = max_lttpr_lanes; 199 200 drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); 201 drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); 202 drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set); 203 drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set); 204 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); 205 206 if (drm_dp_enhanced_frame_cap(dpcd)) 207 link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; 208 209 msm_dp_panel_read_psr_cap(panel); 210 211 return rc; 212 } 213 214 static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, 215 u32 mode_edid_bpp, u32 mode_pclk_khz) 216 { 217 const struct msm_dp_link_info *link_info; 218 const u32 max_supported_bpp = 30, min_supported_bpp = 18; 219 u32 bpp, data_rate_khz; 220 221 bpp = min(mode_edid_bpp, max_supported_bpp); 222 223 link_info = &msm_dp_panel->link_info; 224 data_rate_khz = link_info->num_lanes * link_info->rate * 8; 225 226 do { 227 if (mode_pclk_khz * bpp <= data_rate_khz) 228 return bpp; 229 bpp -= 6; 230 } while (bpp > min_supported_bpp); 231 232 return min_supported_bpp; 233 } 234 235 int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, 236 struct drm_connector *connector) 237 { 238 int rc, bw_code; 239 int count; 240 struct msm_dp_panel_private *panel; 241 242 if (!msm_dp_panel || !connector) { 243 DRM_ERROR("invalid input\n"); 244 return -EINVAL; 245 } 246 247 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 248 249 rc = msm_dp_panel_read_dpcd(msm_dp_panel); 250 if (rc) { 251 DRM_ERROR("read dpcd failed %d\n", rc); 252 return rc; 253 } 254 255 bw_code = drm_dp_link_rate_to_bw_code(msm_dp_panel->link_info.rate); 256 if (!is_link_rate_valid(bw_code) || 257 !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || 258 (bw_code > msm_dp_panel->max_bw_code)) { 259 DRM_ERROR("Illegal link rate=%d lane=%d\n", msm_dp_panel->link_info.rate, 260 msm_dp_panel->link_info.num_lanes); 261 return -EINVAL; 262 } 263 264 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { 265 count = drm_dp_read_sink_count(panel->aux); 266 if (!count) { 267 panel->link->sink_count = 0; 268 return -ENOTCONN; 269 } 270 } 271 272 rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, 273 msm_dp_panel->downstream_ports); 274 if (rc) 275 return rc; 276 277 drm_edid_free(msm_dp_panel->drm_edid); 278 279 msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc); 280 281 drm_edid_connector_update(connector, msm_dp_panel->drm_edid); 282 283 if (!msm_dp_panel->drm_edid) { 284 DRM_ERROR("panel edid read failed\n"); 285 /* check edid read fail is due to unplug */ 286 if (!msm_dp_aux_is_link_connected(panel->aux)) { 287 rc = -ETIMEDOUT; 288 goto end; 289 } 290 } 291 292 end: 293 return rc; 294 } 295 296 void msm_dp_panel_unplugged(struct msm_dp_panel *msm_dp_panel, 297 struct drm_connector *connector) 298 { 299 drm_edid_connector_update(connector, NULL); 300 drm_edid_free(msm_dp_panel->drm_edid); 301 msm_dp_panel->drm_edid = NULL; 302 } 303 304 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, 305 u32 mode_edid_bpp, u32 mode_pclk_khz) 306 { 307 struct msm_dp_panel_private *panel; 308 u32 bpp; 309 310 if (!msm_dp_panel || !mode_edid_bpp || !mode_pclk_khz) { 311 DRM_ERROR("invalid input\n"); 312 return 0; 313 } 314 315 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 316 317 if (msm_dp_panel->video_test) 318 bpp = msm_dp_link_bit_depth_to_bpp( 319 panel->link->test_video.test_bit_depth); 320 else 321 bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp, 322 mode_pclk_khz); 323 324 return bpp; 325 } 326 327 int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, 328 struct drm_connector *connector) 329 { 330 if (!msm_dp_panel) { 331 DRM_ERROR("invalid input\n"); 332 return -EINVAL; 333 } 334 335 if (msm_dp_panel->drm_edid) 336 return drm_edid_connector_add_modes(connector); 337 338 return 0; 339 } 340 341 static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) 342 { 343 edid += edid->extensions; 344 345 return edid->checksum; 346 } 347 348 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) 349 { 350 struct msm_dp_panel_private *panel; 351 352 if (!msm_dp_panel) { 353 DRM_ERROR("invalid input\n"); 354 return; 355 } 356 357 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 358 359 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { 360 /* FIXME: get rid of drm_edid_raw() */ 361 const struct edid *edid = drm_edid_raw(msm_dp_panel->drm_edid); 362 u8 checksum; 363 364 if (edid) 365 checksum = msm_dp_panel_get_edid_checksum(edid); 366 else 367 checksum = msm_dp_panel->connector->real_edid_checksum; 368 369 msm_dp_link_send_edid_checksum(panel->link, checksum); 370 msm_dp_link_send_test_response(panel->link); 371 } 372 } 373 374 static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, 375 struct drm_display_mode *drm_mode) 376 { 377 struct msm_dp_panel_private *panel = 378 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 379 u32 hsync_period, vsync_period; 380 u32 display_v_start, display_v_end; 381 u32 hsync_start_x, hsync_end_x; 382 u32 v_sync_width; 383 u32 hsync_ctl; 384 u32 display_hctl; 385 386 /* TPG config parameters*/ 387 hsync_period = drm_mode->htotal; 388 vsync_period = drm_mode->vtotal; 389 390 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * 391 hsync_period); 392 display_v_end = ((vsync_period - (drm_mode->vsync_start - 393 drm_mode->vdisplay)) 394 * hsync_period) - 1; 395 396 display_v_start += drm_mode->htotal - drm_mode->hsync_start; 397 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); 398 399 hsync_start_x = drm_mode->htotal - drm_mode->hsync_start; 400 hsync_end_x = hsync_period - (drm_mode->hsync_start - 401 drm_mode->hdisplay) - 1; 402 403 v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start; 404 405 hsync_ctl = (hsync_period << 16) | 406 (drm_mode->hsync_end - drm_mode->hsync_start); 407 display_hctl = (hsync_end_x << 16) | hsync_start_x; 408 409 410 msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); 411 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * 412 hsync_period); 413 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * 414 hsync_period); 415 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); 416 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); 417 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); 418 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); 419 msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); 420 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); 421 msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); 422 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); 423 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); 424 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); 425 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); 426 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); 427 msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); 428 429 msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 430 DP_TPG_CHECKERED_RECT_PATTERN); 431 msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, 432 DP_TPG_VIDEO_CONFIG_BPP_8BIT | 433 DP_TPG_VIDEO_CONFIG_RGB); 434 msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 435 DP_BIST_ENABLE_DPBIST_EN); 436 msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 437 DP_TIMING_ENGINE_EN_EN); 438 drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); 439 } 440 441 static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) 442 { 443 struct msm_dp_panel_private *panel = 444 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 445 446 msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); 447 msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); 448 msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); 449 } 450 451 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 452 { 453 struct msm_dp_panel_private *panel; 454 455 if (!msm_dp_panel) { 456 DRM_ERROR("invalid input\n"); 457 return; 458 } 459 460 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 461 462 if (!panel->panel_on) { 463 drm_dbg_dp(panel->drm_dev, 464 "DP panel not enabled, handle TPG on next on\n"); 465 return; 466 } 467 468 if (!enable) { 469 msm_dp_panel_tpg_disable(msm_dp_panel); 470 return; 471 } 472 473 drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n"); 474 msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.drm_mode); 475 } 476 477 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) 478 { 479 struct msm_dp_panel_private *panel = 480 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 481 482 msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); 483 } 484 485 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) 486 { 487 u32 header[2]; 488 u32 val; 489 int i; 490 491 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); 492 493 msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); 494 msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); 495 496 for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { 497 val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | 498 (vsc_sdp->db[i + 3] << 24)); 499 msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); 500 } 501 } 502 503 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) 504 { 505 u32 hw_revision = panel->msm_dp_panel.hw_revision; 506 507 if (hw_revision >= DP_HW_VERSION_1_0 && 508 hw_revision < DP_HW_VERSION_1_2) { 509 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); 510 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); 511 } 512 } 513 514 void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp) 515 { 516 struct msm_dp_panel_private *panel = 517 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 518 u32 cfg, cfg2, misc; 519 520 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 521 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 522 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 523 524 cfg |= GEN0_SDP_EN; 525 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 526 527 cfg2 |= GENERIC0_SDPSIZE_VALID; 528 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 529 530 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); 531 532 /* indicates presence of VSC (BIT(6) of MISC1) */ 533 misc |= DP_MISC1_VSC_SDP; 534 535 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); 536 537 pr_debug("misc settings = 0x%x\n", misc); 538 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 539 540 msm_dp_panel_update_sdp(panel); 541 } 542 543 void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) 544 { 545 struct msm_dp_panel_private *panel = 546 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 547 u32 cfg, cfg2, misc; 548 549 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 550 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 551 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 552 553 cfg &= ~GEN0_SDP_EN; 554 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 555 556 cfg2 &= ~GENERIC0_SDPSIZE_VALID; 557 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 558 559 /* switch back to MSA */ 560 misc &= ~DP_MISC1_VSC_SDP; 561 562 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); 563 564 pr_debug("misc settings = 0x%x\n", misc); 565 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 566 567 msm_dp_panel_update_sdp(panel); 568 } 569 570 static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 571 { 572 struct msm_dp_display_mode *msm_dp_mode; 573 struct drm_dp_vsc_sdp vsc_sdp_data; 574 struct dp_sdp vsc_sdp; 575 ssize_t len; 576 577 if (!msm_dp_panel) { 578 DRM_ERROR("invalid input\n"); 579 return -EINVAL; 580 } 581 582 msm_dp_mode = &msm_dp_panel->msm_dp_mode; 583 584 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); 585 586 /* VSC SDP header as per table 2-118 of DP 1.4 specification */ 587 vsc_sdp_data.sdp_type = DP_SDP_VSC; 588 vsc_sdp_data.revision = 0x05; 589 vsc_sdp_data.length = 0x13; 590 591 /* VSC SDP Payload for DB16 */ 592 vsc_sdp_data.pixelformat = DP_PIXELFORMAT_YUV420; 593 vsc_sdp_data.colorimetry = DP_COLORIMETRY_DEFAULT; 594 595 /* VSC SDP Payload for DB17 */ 596 vsc_sdp_data.bpc = msm_dp_mode->bpp / 3; 597 vsc_sdp_data.dynamic_range = DP_DYNAMIC_RANGE_CTA; 598 599 /* VSC SDP Payload for DB18 */ 600 vsc_sdp_data.content_type = DP_CONTENT_TYPE_GRAPHICS; 601 602 len = drm_dp_vsc_sdp_pack(&vsc_sdp_data, &vsc_sdp); 603 if (len < 0) { 604 DRM_ERROR("unable to pack vsc sdp\n"); 605 return len; 606 } 607 608 msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); 609 610 return 0; 611 } 612 613 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) 614 { 615 u32 data, total_ver, total_hor; 616 struct msm_dp_panel_private *panel; 617 struct drm_display_mode *drm_mode; 618 u32 width_blanking; 619 u32 sync_start; 620 u32 msm_dp_active; 621 u32 total; 622 u32 reg; 623 624 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 625 drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode; 626 627 drm_dbg_dp(panel->drm_dev, "width=%d hporch= %d %d %d\n", 628 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, 629 drm_mode->hsync_start - drm_mode->hdisplay, 630 drm_mode->hsync_end - drm_mode->hsync_start); 631 632 drm_dbg_dp(panel->drm_dev, "height=%d vporch= %d %d %d\n", 633 drm_mode->vdisplay, drm_mode->vtotal - drm_mode->vsync_end, 634 drm_mode->vsync_start - drm_mode->vdisplay, 635 drm_mode->vsync_end - drm_mode->vsync_start); 636 637 total_hor = drm_mode->htotal; 638 639 total_ver = drm_mode->vtotal; 640 641 data = total_ver; 642 data <<= 16; 643 data |= total_hor; 644 645 total = data; 646 647 data = (drm_mode->vtotal - drm_mode->vsync_start); 648 data <<= 16; 649 data |= (drm_mode->htotal - drm_mode->hsync_start); 650 651 sync_start = data; 652 653 data = drm_mode->vsync_end - drm_mode->vsync_start; 654 data <<= 16; 655 data |= (panel->msm_dp_panel.msm_dp_mode.v_active_low << 31); 656 data |= drm_mode->hsync_end - drm_mode->hsync_start; 657 data |= (panel->msm_dp_panel.msm_dp_mode.h_active_low << 15); 658 659 width_blanking = data; 660 661 data = drm_mode->vdisplay; 662 data <<= 16; 663 data |= drm_mode->hdisplay; 664 665 msm_dp_active = data; 666 667 msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); 668 msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); 669 msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); 670 msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); 671 672 reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); 673 if (wide_bus_en) 674 reg |= DP_INTF_CONFIG_DATABUS_WIDEN; 675 else 676 reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN; 677 678 drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); 679 680 msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); 681 682 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) 683 msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); 684 685 panel->panel_on = true; 686 687 return 0; 688 } 689 690 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) 691 { 692 struct drm_display_mode *drm_mode; 693 struct msm_dp_panel_private *panel; 694 695 drm_mode = &msm_dp_panel->msm_dp_mode.drm_mode; 696 697 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 698 699 /* 700 * print resolution info as this is a result 701 * of user initiated action of cable connection 702 */ 703 drm_dbg_dp(panel->drm_dev, "SET NEW RESOLUTION:\n"); 704 drm_dbg_dp(panel->drm_dev, "%dx%d@%dfps\n", 705 drm_mode->hdisplay, drm_mode->vdisplay, drm_mode_vrefresh(drm_mode)); 706 drm_dbg_dp(panel->drm_dev, 707 "h_porches(back|front|width) = (%d|%d|%d)\n", 708 drm_mode->htotal - drm_mode->hsync_end, 709 drm_mode->hsync_start - drm_mode->hdisplay, 710 drm_mode->hsync_end - drm_mode->hsync_start); 711 drm_dbg_dp(panel->drm_dev, 712 "v_porches(back|front|width) = (%d|%d|%d)\n", 713 drm_mode->vtotal - drm_mode->vsync_end, 714 drm_mode->vsync_start - drm_mode->vdisplay, 715 drm_mode->vsync_end - drm_mode->vsync_start); 716 drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n", 717 drm_mode->clock); 718 drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp); 719 720 msm_dp_panel->msm_dp_mode.bpp = msm_dp_panel_get_mode_bpp(msm_dp_panel, msm_dp_panel->msm_dp_mode.bpp, 721 msm_dp_panel->msm_dp_mode.drm_mode.clock); 722 723 drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n", 724 msm_dp_panel->msm_dp_mode.bpp); 725 726 return 0; 727 } 728 729 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, 730 struct msm_dp_link *link, 731 void __iomem *link_base, 732 void __iomem *p0_base) 733 { 734 struct msm_dp_panel_private *panel; 735 struct msm_dp_panel *msm_dp_panel; 736 737 if (!dev || !aux || !link) { 738 DRM_ERROR("invalid input\n"); 739 return ERR_PTR(-EINVAL); 740 } 741 742 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 743 if (!panel) 744 return ERR_PTR(-ENOMEM); 745 746 panel->dev = dev; 747 panel->aux = aux; 748 panel->link = link; 749 panel->link_base = link_base; 750 panel->p0_base = p0_base; 751 752 msm_dp_panel = &panel->msm_dp_panel; 753 msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; 754 755 return msm_dp_panel; 756 } 757 758 void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) 759 { 760 if (!msm_dp_panel) 761 return; 762 763 drm_edid_free(msm_dp_panel->drm_edid); 764 } 765