1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dp_panel.h" 7 #include "dp_reg.h" 8 #include "dp_utils.h" 9 10 #include <drm/drm_connector.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/io.h> 16 17 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) 18 19 struct msm_dp_panel_private { 20 struct device *dev; 21 struct drm_device *drm_dev; 22 struct msm_dp_panel msm_dp_panel; 23 struct drm_dp_aux *aux; 24 struct msm_dp_link *link; 25 void __iomem *link_base; 26 void __iomem *p0_base; 27 bool panel_on; 28 }; 29 30 static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) 31 { 32 return readl_relaxed(panel->link_base + offset); 33 } 34 35 static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, 36 u32 offset, u32 data) 37 { 38 /* 39 * To make sure link reg writes happens before any other operation, 40 * this function uses writel() instread of writel_relaxed() 41 */ 42 writel(data, panel->link_base + offset); 43 } 44 45 static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, 46 u32 offset, u32 data) 47 { 48 /* 49 * To make sure interface reg writes happens before any other operation, 50 * this function uses writel() instread of writel_relaxed() 51 */ 52 writel(data, panel->p0_base + offset); 53 } 54 55 static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, 56 u32 offset) 57 { 58 /* 59 * To make sure interface reg writes happens before any other operation, 60 * this function uses writel() instread of writel_relaxed() 61 */ 62 return readl_relaxed(panel->p0_base + offset); 63 } 64 65 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) 66 { 67 ssize_t rlen; 68 struct msm_dp_panel *msm_dp_panel; 69 70 msm_dp_panel = &panel->msm_dp_panel; 71 72 /* edp sink */ 73 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 74 rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT, 75 &msm_dp_panel->psr_cap, sizeof(msm_dp_panel->psr_cap)); 76 if (rlen == sizeof(msm_dp_panel->psr_cap)) { 77 drm_dbg_dp(panel->drm_dev, 78 "psr version: 0x%x, psr_cap: 0x%x\n", 79 msm_dp_panel->psr_cap.version, 80 msm_dp_panel->psr_cap.capabilities); 81 } else 82 DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen); 83 } 84 } 85 86 static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel) 87 { 88 int rc, max_lttpr_lanes, max_lttpr_rate; 89 struct msm_dp_panel_private *panel; 90 struct msm_dp_link_info *link_info; 91 struct msm_dp_link *link; 92 u8 *dpcd, major, minor; 93 94 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 95 dpcd = msm_dp_panel->dpcd; 96 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); 97 if (rc) 98 return rc; 99 100 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); 101 link_info = &msm_dp_panel->link_info; 102 link_info->revision = dpcd[DP_DPCD_REV]; 103 major = (link_info->revision >> 4) & 0x0f; 104 minor = link_info->revision & 0x0f; 105 106 link = panel->link; 107 drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n", 108 link->max_dp_lanes, link->max_dp_link_rate); 109 110 link_info->rate = drm_dp_max_link_rate(dpcd); 111 link_info->num_lanes = drm_dp_max_lane_count(dpcd); 112 113 /* Limit data lanes from data-lanes of endpoint property of dtsi */ 114 if (link_info->num_lanes > link->max_dp_lanes) 115 link_info->num_lanes = link->max_dp_lanes; 116 117 /* Limit link rate from link-frequencies of endpoint property of dtsi */ 118 if (link_info->rate > link->max_dp_link_rate) 119 link_info->rate = link->max_dp_link_rate; 120 121 /* Limit data lanes from LTTPR capabilities, if any */ 122 max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps); 123 if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes) 124 link_info->num_lanes = max_lttpr_lanes; 125 126 /* Limit link rate from LTTPR capabilities, if any */ 127 max_lttpr_rate = drm_dp_lttpr_max_link_rate(panel->link->lttpr_common_caps); 128 if (max_lttpr_rate && max_lttpr_rate < link_info->rate) 129 link_info->rate = max_lttpr_rate; 130 131 drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); 132 drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); 133 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); 134 135 if (drm_dp_enhanced_frame_cap(dpcd)) 136 link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; 137 138 msm_dp_panel_read_psr_cap(panel); 139 140 return rc; 141 } 142 143 static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, 144 u32 mode_edid_bpp, u32 mode_pclk_khz) 145 { 146 const struct msm_dp_link_info *link_info; 147 const u32 max_supported_bpp = 30, min_supported_bpp = 18; 148 u32 bpp, data_rate_khz; 149 150 bpp = min(mode_edid_bpp, max_supported_bpp); 151 152 link_info = &msm_dp_panel->link_info; 153 data_rate_khz = link_info->num_lanes * link_info->rate * 8; 154 155 do { 156 if (mode_pclk_khz * bpp <= data_rate_khz) 157 return bpp; 158 bpp -= 6; 159 } while (bpp > min_supported_bpp); 160 161 return min_supported_bpp; 162 } 163 164 int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, 165 struct drm_connector *connector) 166 { 167 int rc, bw_code; 168 int count; 169 struct msm_dp_panel_private *panel; 170 171 if (!msm_dp_panel || !connector) { 172 DRM_ERROR("invalid input\n"); 173 return -EINVAL; 174 } 175 176 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 177 178 rc = msm_dp_panel_read_dpcd(msm_dp_panel); 179 if (rc) { 180 DRM_ERROR("read dpcd failed %d\n", rc); 181 return rc; 182 } 183 184 bw_code = drm_dp_link_rate_to_bw_code(msm_dp_panel->link_info.rate); 185 if (!is_link_rate_valid(bw_code) || 186 !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || 187 (bw_code > msm_dp_panel->max_bw_code)) { 188 DRM_ERROR("Illegal link rate=%d lane=%d\n", msm_dp_panel->link_info.rate, 189 msm_dp_panel->link_info.num_lanes); 190 return -EINVAL; 191 } 192 193 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { 194 count = drm_dp_read_sink_count(panel->aux); 195 if (!count) { 196 panel->link->sink_count = 0; 197 return -ENOTCONN; 198 } 199 } 200 201 rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, 202 msm_dp_panel->downstream_ports); 203 if (rc) 204 return rc; 205 206 drm_edid_free(msm_dp_panel->drm_edid); 207 208 msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc); 209 210 drm_edid_connector_update(connector, msm_dp_panel->drm_edid); 211 212 if (!msm_dp_panel->drm_edid) { 213 DRM_ERROR("panel edid read failed\n"); 214 /* check edid read fail is due to unplug */ 215 if (!msm_dp_aux_is_link_connected(panel->aux)) { 216 rc = -ETIMEDOUT; 217 goto end; 218 } 219 } 220 221 end: 222 return rc; 223 } 224 225 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, 226 u32 mode_edid_bpp, u32 mode_pclk_khz) 227 { 228 struct msm_dp_panel_private *panel; 229 u32 bpp; 230 231 if (!msm_dp_panel || !mode_edid_bpp || !mode_pclk_khz) { 232 DRM_ERROR("invalid input\n"); 233 return 0; 234 } 235 236 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 237 238 if (msm_dp_panel->video_test) 239 bpp = msm_dp_link_bit_depth_to_bpp( 240 panel->link->test_video.test_bit_depth); 241 else 242 bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp, 243 mode_pclk_khz); 244 245 return bpp; 246 } 247 248 int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, 249 struct drm_connector *connector) 250 { 251 if (!msm_dp_panel) { 252 DRM_ERROR("invalid input\n"); 253 return -EINVAL; 254 } 255 256 if (msm_dp_panel->drm_edid) 257 return drm_edid_connector_add_modes(connector); 258 259 return 0; 260 } 261 262 static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) 263 { 264 edid += edid->extensions; 265 266 return edid->checksum; 267 } 268 269 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) 270 { 271 struct msm_dp_panel_private *panel; 272 273 if (!msm_dp_panel) { 274 DRM_ERROR("invalid input\n"); 275 return; 276 } 277 278 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 279 280 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { 281 /* FIXME: get rid of drm_edid_raw() */ 282 const struct edid *edid = drm_edid_raw(msm_dp_panel->drm_edid); 283 u8 checksum; 284 285 if (edid) 286 checksum = msm_dp_panel_get_edid_checksum(edid); 287 else 288 checksum = msm_dp_panel->connector->real_edid_checksum; 289 290 msm_dp_link_send_edid_checksum(panel->link, checksum); 291 msm_dp_link_send_test_response(panel->link); 292 } 293 } 294 295 static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, 296 struct drm_display_mode *drm_mode) 297 { 298 struct msm_dp_panel_private *panel = 299 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 300 u32 hsync_period, vsync_period; 301 u32 display_v_start, display_v_end; 302 u32 hsync_start_x, hsync_end_x; 303 u32 v_sync_width; 304 u32 hsync_ctl; 305 u32 display_hctl; 306 307 /* TPG config parameters*/ 308 hsync_period = drm_mode->htotal; 309 vsync_period = drm_mode->vtotal; 310 311 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * 312 hsync_period); 313 display_v_end = ((vsync_period - (drm_mode->vsync_start - 314 drm_mode->vdisplay)) 315 * hsync_period) - 1; 316 317 display_v_start += drm_mode->htotal - drm_mode->hsync_start; 318 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); 319 320 hsync_start_x = drm_mode->htotal - drm_mode->hsync_start; 321 hsync_end_x = hsync_period - (drm_mode->hsync_start - 322 drm_mode->hdisplay) - 1; 323 324 v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start; 325 326 hsync_ctl = (hsync_period << 16) | 327 (drm_mode->hsync_end - drm_mode->hsync_start); 328 display_hctl = (hsync_end_x << 16) | hsync_start_x; 329 330 331 msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); 332 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * 333 hsync_period); 334 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * 335 hsync_period); 336 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); 337 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); 338 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); 339 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); 340 msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); 341 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); 342 msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); 343 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); 344 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); 345 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); 346 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); 347 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); 348 msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); 349 350 msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 351 DP_TPG_CHECKERED_RECT_PATTERN); 352 msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, 353 DP_TPG_VIDEO_CONFIG_BPP_8BIT | 354 DP_TPG_VIDEO_CONFIG_RGB); 355 msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 356 DP_BIST_ENABLE_DPBIST_EN); 357 msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 358 DP_TIMING_ENGINE_EN_EN); 359 drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); 360 } 361 362 static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) 363 { 364 struct msm_dp_panel_private *panel = 365 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 366 367 msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); 368 msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); 369 msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); 370 } 371 372 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 373 { 374 struct msm_dp_panel_private *panel; 375 376 if (!msm_dp_panel) { 377 DRM_ERROR("invalid input\n"); 378 return; 379 } 380 381 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 382 383 if (!panel->panel_on) { 384 drm_dbg_dp(panel->drm_dev, 385 "DP panel not enabled, handle TPG on next on\n"); 386 return; 387 } 388 389 if (!enable) { 390 msm_dp_panel_tpg_disable(msm_dp_panel); 391 return; 392 } 393 394 drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n"); 395 msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.drm_mode); 396 } 397 398 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) 399 { 400 struct msm_dp_panel_private *panel = 401 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 402 403 msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); 404 } 405 406 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) 407 { 408 u32 header[2]; 409 u32 val; 410 int i; 411 412 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); 413 414 msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); 415 msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); 416 417 for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { 418 val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | 419 (vsc_sdp->db[i + 3] << 24)); 420 msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); 421 } 422 } 423 424 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) 425 { 426 u32 hw_revision = panel->msm_dp_panel.hw_revision; 427 428 if (hw_revision >= DP_HW_VERSION_1_0 && 429 hw_revision < DP_HW_VERSION_1_2) { 430 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); 431 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); 432 } 433 } 434 435 void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp) 436 { 437 struct msm_dp_panel_private *panel = 438 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 439 u32 cfg, cfg2, misc; 440 441 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 442 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 443 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 444 445 cfg |= GEN0_SDP_EN; 446 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 447 448 cfg2 |= GENERIC0_SDPSIZE_VALID; 449 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 450 451 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); 452 453 /* indicates presence of VSC (BIT(6) of MISC1) */ 454 misc |= DP_MISC1_VSC_SDP; 455 456 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); 457 458 pr_debug("misc settings = 0x%x\n", misc); 459 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 460 461 msm_dp_panel_update_sdp(panel); 462 } 463 464 void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) 465 { 466 struct msm_dp_panel_private *panel = 467 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 468 u32 cfg, cfg2, misc; 469 470 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 471 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 472 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 473 474 cfg &= ~GEN0_SDP_EN; 475 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 476 477 cfg2 &= ~GENERIC0_SDPSIZE_VALID; 478 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 479 480 /* switch back to MSA */ 481 misc &= ~DP_MISC1_VSC_SDP; 482 483 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); 484 485 pr_debug("misc settings = 0x%x\n", misc); 486 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 487 488 msm_dp_panel_update_sdp(panel); 489 } 490 491 static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 492 { 493 struct msm_dp_display_mode *msm_dp_mode; 494 struct drm_dp_vsc_sdp vsc_sdp_data; 495 struct dp_sdp vsc_sdp; 496 ssize_t len; 497 498 if (!msm_dp_panel) { 499 DRM_ERROR("invalid input\n"); 500 return -EINVAL; 501 } 502 503 msm_dp_mode = &msm_dp_panel->msm_dp_mode; 504 505 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); 506 507 /* VSC SDP header as per table 2-118 of DP 1.4 specification */ 508 vsc_sdp_data.sdp_type = DP_SDP_VSC; 509 vsc_sdp_data.revision = 0x05; 510 vsc_sdp_data.length = 0x13; 511 512 /* VSC SDP Payload for DB16 */ 513 vsc_sdp_data.pixelformat = DP_PIXELFORMAT_YUV420; 514 vsc_sdp_data.colorimetry = DP_COLORIMETRY_DEFAULT; 515 516 /* VSC SDP Payload for DB17 */ 517 vsc_sdp_data.bpc = msm_dp_mode->bpp / 3; 518 vsc_sdp_data.dynamic_range = DP_DYNAMIC_RANGE_CTA; 519 520 /* VSC SDP Payload for DB18 */ 521 vsc_sdp_data.content_type = DP_CONTENT_TYPE_GRAPHICS; 522 523 len = drm_dp_vsc_sdp_pack(&vsc_sdp_data, &vsc_sdp); 524 if (len < 0) { 525 DRM_ERROR("unable to pack vsc sdp\n"); 526 return len; 527 } 528 529 msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); 530 531 return 0; 532 } 533 534 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) 535 { 536 u32 data, total_ver, total_hor; 537 struct msm_dp_panel_private *panel; 538 struct drm_display_mode *drm_mode; 539 u32 width_blanking; 540 u32 sync_start; 541 u32 msm_dp_active; 542 u32 total; 543 u32 reg; 544 545 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 546 drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode; 547 548 drm_dbg_dp(panel->drm_dev, "width=%d hporch= %d %d %d\n", 549 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, 550 drm_mode->hsync_start - drm_mode->hdisplay, 551 drm_mode->hsync_end - drm_mode->hsync_start); 552 553 drm_dbg_dp(panel->drm_dev, "height=%d vporch= %d %d %d\n", 554 drm_mode->vdisplay, drm_mode->vtotal - drm_mode->vsync_end, 555 drm_mode->vsync_start - drm_mode->vdisplay, 556 drm_mode->vsync_end - drm_mode->vsync_start); 557 558 total_hor = drm_mode->htotal; 559 560 total_ver = drm_mode->vtotal; 561 562 data = total_ver; 563 data <<= 16; 564 data |= total_hor; 565 566 total = data; 567 568 data = (drm_mode->vtotal - drm_mode->vsync_start); 569 data <<= 16; 570 data |= (drm_mode->htotal - drm_mode->hsync_start); 571 572 sync_start = data; 573 574 data = drm_mode->vsync_end - drm_mode->vsync_start; 575 data <<= 16; 576 data |= (panel->msm_dp_panel.msm_dp_mode.v_active_low << 31); 577 data |= drm_mode->hsync_end - drm_mode->hsync_start; 578 data |= (panel->msm_dp_panel.msm_dp_mode.h_active_low << 15); 579 580 width_blanking = data; 581 582 data = drm_mode->vdisplay; 583 data <<= 16; 584 data |= drm_mode->hdisplay; 585 586 msm_dp_active = data; 587 588 msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); 589 msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); 590 msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); 591 msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); 592 593 reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); 594 if (wide_bus_en) 595 reg |= DP_INTF_CONFIG_DATABUS_WIDEN; 596 else 597 reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN; 598 599 drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); 600 601 msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); 602 603 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) 604 msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); 605 606 panel->panel_on = true; 607 608 return 0; 609 } 610 611 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) 612 { 613 struct drm_display_mode *drm_mode; 614 struct msm_dp_panel_private *panel; 615 616 drm_mode = &msm_dp_panel->msm_dp_mode.drm_mode; 617 618 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 619 620 /* 621 * print resolution info as this is a result 622 * of user initiated action of cable connection 623 */ 624 drm_dbg_dp(panel->drm_dev, "SET NEW RESOLUTION:\n"); 625 drm_dbg_dp(panel->drm_dev, "%dx%d@%dfps\n", 626 drm_mode->hdisplay, drm_mode->vdisplay, drm_mode_vrefresh(drm_mode)); 627 drm_dbg_dp(panel->drm_dev, 628 "h_porches(back|front|width) = (%d|%d|%d)\n", 629 drm_mode->htotal - drm_mode->hsync_end, 630 drm_mode->hsync_start - drm_mode->hdisplay, 631 drm_mode->hsync_end - drm_mode->hsync_start); 632 drm_dbg_dp(panel->drm_dev, 633 "v_porches(back|front|width) = (%d|%d|%d)\n", 634 drm_mode->vtotal - drm_mode->vsync_end, 635 drm_mode->vsync_start - drm_mode->vdisplay, 636 drm_mode->vsync_end - drm_mode->vsync_start); 637 drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n", 638 drm_mode->clock); 639 drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp); 640 641 msm_dp_panel->msm_dp_mode.bpp = msm_dp_panel_get_mode_bpp(msm_dp_panel, msm_dp_panel->msm_dp_mode.bpp, 642 msm_dp_panel->msm_dp_mode.drm_mode.clock); 643 644 drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n", 645 msm_dp_panel->msm_dp_mode.bpp); 646 647 return 0; 648 } 649 650 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, 651 struct msm_dp_link *link, 652 void __iomem *link_base, 653 void __iomem *p0_base) 654 { 655 struct msm_dp_panel_private *panel; 656 struct msm_dp_panel *msm_dp_panel; 657 658 if (!dev || !aux || !link) { 659 DRM_ERROR("invalid input\n"); 660 return ERR_PTR(-EINVAL); 661 } 662 663 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 664 if (!panel) 665 return ERR_PTR(-ENOMEM); 666 667 panel->dev = dev; 668 panel->aux = aux; 669 panel->link = link; 670 panel->link_base = link_base; 671 panel->p0_base = p0_base; 672 673 msm_dp_panel = &panel->msm_dp_panel; 674 msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; 675 676 return msm_dp_panel; 677 } 678 679 void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) 680 { 681 if (!msm_dp_panel) 682 return; 683 684 drm_edid_free(msm_dp_panel->drm_edid); 685 } 686