1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 #include <linux/string_choices.h> 15 16 #include <drm/display/drm_dp_helper.h> 17 #include <drm/drm_fixed.h> 18 #include <drm/drm_print.h> 19 20 #include "dp_reg.h" 21 #include "dp_ctrl.h" 22 #include "dp_link.h" 23 24 #define DP_KHZ_TO_HZ 1000 25 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 26 #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */ 27 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 28 29 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 30 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 31 32 #define MR_LINK_TRAINING1 0x8 33 #define MR_LINK_SYMBOL_ERM 0x80 34 #define MR_LINK_PRBS7 0x100 35 #define MR_LINK_CUSTOM80 0x200 36 #define MR_LINK_TRAINING4 0x40 37 38 enum { 39 DP_TRAINING_NONE, 40 DP_TRAINING_1, 41 DP_TRAINING_2, 42 }; 43 44 struct msm_dp_tu_calc_input { 45 u64 lclk; /* 162, 270, 540 and 810 */ 46 u64 pclk_khz; /* in KHz */ 47 u64 hactive; /* active h-width */ 48 u64 hporch; /* bp + fp + pulse */ 49 int nlanes; /* no.of.lanes */ 50 int bpp; /* bits */ 51 int pixel_enc; /* 444, 420, 422 */ 52 int dsc_en; /* dsc on/off */ 53 int async_en; /* async mode */ 54 int fec_en; /* fec */ 55 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 56 int num_of_dsc_slices; /* number of slices per line */ 57 }; 58 59 struct msm_dp_vc_tu_mapping_table { 60 u32 vic; 61 u8 lanes; 62 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 63 u8 bpp; 64 u8 valid_boundary_link; 65 u16 delay_start_link; 66 bool boundary_moderation_en; 67 u8 valid_lower_boundary_link; 68 u8 upper_boundary_count; 69 u8 lower_boundary_count; 70 u8 tu_size_minus1; 71 }; 72 73 struct msm_dp_ctrl_private { 74 struct msm_dp_ctrl msm_dp_ctrl; 75 struct drm_device *drm_dev; 76 struct device *dev; 77 struct drm_dp_aux *aux; 78 struct msm_dp_panel *panel; 79 struct msm_dp_link *link; 80 struct msm_dp_catalog *catalog; 81 82 struct phy *phy; 83 84 unsigned int num_core_clks; 85 struct clk_bulk_data *core_clks; 86 87 unsigned int num_link_clks; 88 struct clk_bulk_data *link_clks; 89 90 struct clk *pixel_clk; 91 92 union phy_configure_opts phy_opts; 93 94 struct completion idle_comp; 95 struct completion psr_op_comp; 96 struct completion video_comp; 97 98 bool core_clks_on; 99 bool link_clks_on; 100 bool stream_clks_on; 101 }; 102 103 static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, 104 struct msm_dp_link_info *link) 105 { 106 u8 values[2]; 107 int err; 108 109 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 110 values[1] = link->num_lanes; 111 112 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 113 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 114 115 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 116 if (err < 0) 117 return err; 118 119 return 0; 120 } 121 122 void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) 123 { 124 struct msm_dp_ctrl_private *ctrl; 125 126 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 127 128 reinit_completion(&ctrl->idle_comp); 129 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 130 131 if (!wait_for_completion_timeout(&ctrl->idle_comp, 132 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 133 pr_warn("PUSH_IDLE pattern timedout\n"); 134 135 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); 136 } 137 138 static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) 139 { 140 u32 config = 0, tbd; 141 const u8 *dpcd = ctrl->panel->dpcd; 142 143 /* Default-> LSCLK DIV: 1/4 LCLK */ 144 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 145 146 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 147 config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ 148 149 /* Scrambler reset enable */ 150 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 151 config |= DP_CONFIGURATION_CTRL_ASSR; 152 153 tbd = msm_dp_link_get_test_bits_depth(ctrl->link, 154 ctrl->panel->msm_dp_mode.bpp); 155 156 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 157 158 /* Num of Lanes */ 159 config |= ((ctrl->link->link_params.num_lanes - 1) 160 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 161 162 if (drm_dp_enhanced_frame_cap(dpcd)) 163 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 164 165 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 166 167 /* sync clock & static Mvid */ 168 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 169 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 170 171 if (ctrl->panel->psr_cap.version) 172 config |= DP_CONFIGURATION_CTRL_SEND_VSC; 173 174 msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 175 } 176 177 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) 178 { 179 u32 cc, tb; 180 181 msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); 182 msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); 183 184 msm_dp_ctrl_config_ctrl(ctrl); 185 186 tb = msm_dp_link_get_test_bits_depth(ctrl->link, 187 ctrl->panel->msm_dp_mode.bpp); 188 cc = msm_dp_link_get_colorimetry_config(ctrl->link); 189 msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 190 msm_dp_panel_timing_cfg(ctrl->panel); 191 } 192 193 /* 194 * The structure and few functions present below are IP/Hardware 195 * specific implementation. Most of the implementation will not 196 * have coding comments 197 */ 198 struct tu_algo_data { 199 s64 lclk_fp; 200 s64 pclk_fp; 201 s64 lwidth; 202 s64 lwidth_fp; 203 s64 hbp_relative_to_pclk; 204 s64 hbp_relative_to_pclk_fp; 205 int nlanes; 206 int bpp; 207 int pixelEnc; 208 int dsc_en; 209 int async_en; 210 int bpc; 211 212 uint delay_start_link_extra_pixclk; 213 int extra_buffer_margin; 214 s64 ratio_fp; 215 s64 original_ratio_fp; 216 217 s64 err_fp; 218 s64 n_err_fp; 219 s64 n_n_err_fp; 220 int tu_size; 221 int tu_size_desired; 222 int tu_size_minus1; 223 224 int valid_boundary_link; 225 s64 resulting_valid_fp; 226 s64 total_valid_fp; 227 s64 effective_valid_fp; 228 s64 effective_valid_recorded_fp; 229 int n_tus; 230 int n_tus_per_lane; 231 int paired_tus; 232 int remainder_tus; 233 int remainder_tus_upper; 234 int remainder_tus_lower; 235 int extra_bytes; 236 int filler_size; 237 int delay_start_link; 238 239 int extra_pclk_cycles; 240 int extra_pclk_cycles_in_link_clk; 241 s64 ratio_by_tu_fp; 242 s64 average_valid2_fp; 243 int new_valid_boundary_link; 244 int remainder_symbols_exist; 245 int n_symbols; 246 s64 n_remainder_symbols_per_lane_fp; 247 s64 last_partial_tu_fp; 248 s64 TU_ratio_err_fp; 249 250 int n_tus_incl_last_incomplete_tu; 251 int extra_pclk_cycles_tmp; 252 int extra_pclk_cycles_in_link_clk_tmp; 253 int extra_required_bytes_new_tmp; 254 int filler_size_tmp; 255 int lower_filler_size_tmp; 256 int delay_start_link_tmp; 257 258 bool boundary_moderation_en; 259 int boundary_mod_lower_err; 260 int upper_boundary_count; 261 int lower_boundary_count; 262 int i_upper_boundary_count; 263 int i_lower_boundary_count; 264 int valid_lower_boundary_link; 265 int even_distribution_BF; 266 int even_distribution_legacy; 267 int even_distribution; 268 int min_hblank_violated; 269 s64 delay_start_time_fp; 270 s64 hbp_time_fp; 271 s64 hactive_time_fp; 272 s64 diff_abs_fp; 273 274 s64 ratio; 275 }; 276 277 static int _tu_param_compare(s64 a, s64 b) 278 { 279 u32 a_sign; 280 u32 b_sign; 281 s64 a_temp, b_temp, minus_1; 282 283 if (a == b) 284 return 0; 285 286 minus_1 = drm_fixp_from_fraction(-1, 1); 287 288 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 289 290 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 291 292 if (a_sign > b_sign) 293 return 2; 294 else if (b_sign > a_sign) 295 return 1; 296 297 if (!a_sign && !b_sign) { /* positive */ 298 if (a > b) 299 return 1; 300 else 301 return 2; 302 } else { /* negative */ 303 a_temp = drm_fixp_mul(a, minus_1); 304 b_temp = drm_fixp_mul(b, minus_1); 305 306 if (a_temp > b_temp) 307 return 2; 308 else 309 return 1; 310 } 311 } 312 313 static void msm_dp_panel_update_tu_timings(struct msm_dp_tu_calc_input *in, 314 struct tu_algo_data *tu) 315 { 316 int nlanes = in->nlanes; 317 int dsc_num_slices = in->num_of_dsc_slices; 318 int dsc_num_bytes = 0; 319 int numerator; 320 s64 pclk_dsc_fp; 321 s64 dwidth_dsc_fp; 322 s64 hbp_dsc_fp; 323 324 int tot_num_eoc_symbols = 0; 325 int tot_num_hor_bytes = 0; 326 int tot_num_dummy_bytes = 0; 327 int dwidth_dsc_bytes = 0; 328 int eoc_bytes = 0; 329 330 s64 temp1_fp, temp2_fp, temp3_fp; 331 332 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 333 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 334 tu->lwidth = in->hactive; 335 tu->hbp_relative_to_pclk = in->hporch; 336 tu->nlanes = in->nlanes; 337 tu->bpp = in->bpp; 338 tu->pixelEnc = in->pixel_enc; 339 tu->dsc_en = in->dsc_en; 340 tu->async_en = in->async_en; 341 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 342 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 343 344 if (tu->pixelEnc == 420) { 345 temp1_fp = drm_fixp_from_fraction(2, 1); 346 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 347 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 348 tu->hbp_relative_to_pclk_fp = 349 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 350 } 351 352 if (tu->pixelEnc == 422) { 353 switch (tu->bpp) { 354 case 24: 355 tu->bpp = 16; 356 tu->bpc = 8; 357 break; 358 case 30: 359 tu->bpp = 20; 360 tu->bpc = 10; 361 break; 362 default: 363 tu->bpp = 16; 364 tu->bpc = 8; 365 break; 366 } 367 } else { 368 tu->bpc = tu->bpp/3; 369 } 370 371 if (!in->dsc_en) 372 goto fec_check; 373 374 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 375 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 376 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 377 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 378 379 temp1_fp = drm_fixp_from_fraction(8, 1); 380 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 381 382 numerator = drm_fixp2int(temp3_fp); 383 384 dsc_num_bytes = numerator / dsc_num_slices; 385 eoc_bytes = dsc_num_bytes % nlanes; 386 tot_num_eoc_symbols = nlanes * dsc_num_slices; 387 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 388 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 389 390 if (dsc_num_bytes == 0) 391 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 392 393 dwidth_dsc_bytes = (tot_num_hor_bytes + 394 tot_num_eoc_symbols + 395 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 396 397 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 398 399 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 400 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 401 pclk_dsc_fp = temp1_fp; 402 403 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 404 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 405 hbp_dsc_fp = temp2_fp; 406 407 /* output */ 408 tu->pclk_fp = pclk_dsc_fp; 409 tu->lwidth_fp = dwidth_dsc_fp; 410 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 411 412 fec_check: 413 if (in->fec_en) { 414 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 415 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 416 } 417 } 418 419 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 420 { 421 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 422 int compare_result_1, compare_result_2, compare_result_3; 423 424 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 425 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 426 427 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 428 429 temp = (tu->i_upper_boundary_count * 430 tu->new_valid_boundary_link + 431 tu->i_lower_boundary_count * 432 (tu->new_valid_boundary_link-1)); 433 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 434 (tu->i_upper_boundary_count + 435 tu->i_lower_boundary_count)); 436 437 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 438 temp2_fp = tu->lwidth_fp; 439 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 440 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 441 tu->n_tus = drm_fixp2int(temp2_fp); 442 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 443 tu->n_tus += 1; 444 445 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 446 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 447 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 448 temp2_fp = temp1_fp - temp2_fp; 449 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 450 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 451 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 452 453 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 454 tu->last_partial_tu_fp = 455 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 456 temp1_fp); 457 458 if (tu->n_remainder_symbols_per_lane_fp != 0) 459 tu->remainder_symbols_exist = 1; 460 else 461 tu->remainder_symbols_exist = 0; 462 463 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 464 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 465 466 tu->paired_tus = (int)((tu->n_tus_per_lane) / 467 (tu->i_upper_boundary_count + 468 tu->i_lower_boundary_count)); 469 470 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 471 (tu->i_upper_boundary_count + 472 tu->i_lower_boundary_count); 473 474 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 475 tu->remainder_tus_upper = tu->i_upper_boundary_count; 476 tu->remainder_tus_lower = tu->remainder_tus - 477 tu->i_upper_boundary_count; 478 } else { 479 tu->remainder_tus_upper = tu->remainder_tus; 480 tu->remainder_tus_lower = 0; 481 } 482 483 temp = tu->paired_tus * (tu->i_upper_boundary_count * 484 tu->new_valid_boundary_link + 485 tu->i_lower_boundary_count * 486 (tu->new_valid_boundary_link - 1)) + 487 (tu->remainder_tus_upper * 488 tu->new_valid_boundary_link) + 489 (tu->remainder_tus_lower * 490 (tu->new_valid_boundary_link - 1)); 491 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 492 493 if (tu->remainder_symbols_exist) { 494 temp1_fp = tu->total_valid_fp + 495 tu->n_remainder_symbols_per_lane_fp; 496 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 497 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 498 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 499 } else { 500 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 501 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 502 } 503 tu->effective_valid_fp = temp1_fp; 504 505 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 506 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 507 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 508 509 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 510 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 511 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 512 513 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 514 515 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 516 temp2_fp = tu->lwidth_fp; 517 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 518 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 519 520 if (temp2_fp) 521 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 522 else 523 tu->n_tus_incl_last_incomplete_tu = 0; 524 525 temp1 = 0; 526 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 527 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 528 temp1_fp = tu->average_valid2_fp - temp2_fp; 529 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 530 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 531 532 if (temp1_fp) 533 temp1 = drm_fixp2int_ceil(temp1_fp); 534 535 temp = tu->i_upper_boundary_count * tu->nlanes; 536 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 537 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 538 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 539 temp2_fp = temp1_fp - temp2_fp; 540 temp1_fp = drm_fixp_from_fraction(temp, 1); 541 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 542 543 if (temp2_fp) 544 temp2 = drm_fixp2int_ceil(temp2_fp); 545 else 546 temp2 = 0; 547 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 548 549 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 550 temp2_fp = drm_fixp_from_fraction( 551 tu->extra_required_bytes_new_tmp, 1); 552 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 553 554 if (temp1_fp) 555 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 556 else 557 tu->extra_pclk_cycles_tmp = 0; 558 559 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 560 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 561 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 562 563 if (temp1_fp) 564 tu->extra_pclk_cycles_in_link_clk_tmp = 565 drm_fixp2int_ceil(temp1_fp); 566 else 567 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 568 569 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 570 571 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 572 573 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 574 tu->lower_filler_size_tmp + 575 tu->extra_buffer_margin; 576 577 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 578 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 579 580 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 581 if (compare_result_1 == 2) 582 compare_result_1 = 1; 583 else 584 compare_result_1 = 0; 585 586 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 587 if (compare_result_2 == 2) 588 compare_result_2 = 1; 589 else 590 compare_result_2 = 0; 591 592 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 593 tu->delay_start_time_fp); 594 if (compare_result_3 == 2) 595 compare_result_3 = 0; 596 else 597 compare_result_3 = 1; 598 599 if (((tu->even_distribution == 1) || 600 ((tu->even_distribution_BF == 0) && 601 (tu->even_distribution_legacy == 0))) && 602 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 603 compare_result_2 && 604 (compare_result_1 || (tu->min_hblank_violated == 1)) && 605 (tu->new_valid_boundary_link - 1) > 0 && 606 compare_result_3 && 607 (tu->delay_start_link_tmp <= 1023)) { 608 tu->upper_boundary_count = tu->i_upper_boundary_count; 609 tu->lower_boundary_count = tu->i_lower_boundary_count; 610 tu->err_fp = tu->n_n_err_fp; 611 tu->boundary_moderation_en = true; 612 tu->tu_size_desired = tu->tu_size; 613 tu->valid_boundary_link = tu->new_valid_boundary_link; 614 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 615 tu->even_distribution_BF = 1; 616 tu->delay_start_link = tu->delay_start_link_tmp; 617 } else if (tu->boundary_mod_lower_err == 0) { 618 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 619 tu->diff_abs_fp); 620 if (compare_result_1 == 2) 621 tu->boundary_mod_lower_err = 1; 622 } 623 } 624 625 static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl, 626 struct msm_dp_tu_calc_input *in, 627 struct msm_dp_vc_tu_mapping_table *tu_table) 628 { 629 struct tu_algo_data *tu; 630 int compare_result_1, compare_result_2; 631 u64 temp = 0; 632 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 633 634 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 635 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 636 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 637 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 638 639 u8 DP_BRUTE_FORCE = 1; 640 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 641 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 642 uint HBLANK_MARGIN = 4; 643 644 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 645 if (!tu) 646 return; 647 648 msm_dp_panel_update_tu_timings(in, tu); 649 650 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 651 652 temp1_fp = drm_fixp_from_fraction(4, 1); 653 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 654 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 655 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 656 657 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 658 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 659 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 660 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 661 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 662 663 tu->original_ratio_fp = tu->ratio_fp; 664 tu->boundary_moderation_en = false; 665 tu->upper_boundary_count = 0; 666 tu->lower_boundary_count = 0; 667 tu->i_upper_boundary_count = 0; 668 tu->i_lower_boundary_count = 0; 669 tu->valid_lower_boundary_link = 0; 670 tu->even_distribution_BF = 0; 671 tu->even_distribution_legacy = 0; 672 tu->even_distribution = 0; 673 tu->delay_start_time_fp = 0; 674 675 tu->err_fp = drm_fixp_from_fraction(1000, 1); 676 tu->n_err_fp = 0; 677 tu->n_n_err_fp = 0; 678 679 tu->ratio = drm_fixp2int(tu->ratio_fp); 680 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 681 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 682 if (temp2_fp != 0 && 683 !tu->ratio && tu->dsc_en == 0) { 684 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 685 tu->ratio = drm_fixp2int(tu->ratio_fp); 686 if (tu->ratio) 687 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 688 } 689 690 if (tu->ratio > 1) 691 tu->ratio = 1; 692 693 if (tu->ratio == 1) 694 goto tu_size_calc; 695 696 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 697 if (!compare_result_1 || compare_result_1 == 1) 698 compare_result_1 = 1; 699 else 700 compare_result_1 = 0; 701 702 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 703 if (!compare_result_2 || compare_result_2 == 2) 704 compare_result_2 = 1; 705 else 706 compare_result_2 = 0; 707 708 if (tu->dsc_en && compare_result_1 && compare_result_2) { 709 HBLANK_MARGIN += 4; 710 drm_dbg_dp(ctrl->drm_dev, 711 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN); 712 } 713 714 tu_size_calc: 715 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 716 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 717 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 718 temp = drm_fixp2int_ceil(temp2_fp); 719 temp1_fp = drm_fixp_from_fraction(temp, 1); 720 tu->n_err_fp = temp1_fp - temp2_fp; 721 722 if (tu->n_err_fp < tu->err_fp) { 723 tu->err_fp = tu->n_err_fp; 724 tu->tu_size_desired = tu->tu_size; 725 } 726 } 727 728 tu->tu_size_minus1 = tu->tu_size_desired - 1; 729 730 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 731 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 732 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 733 734 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 735 temp2_fp = tu->lwidth_fp; 736 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 737 738 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 739 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 740 tu->n_tus = drm_fixp2int(temp2_fp); 741 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 742 tu->n_tus += 1; 743 744 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 745 746 drm_dbg_dp(ctrl->drm_dev, 747 "n_sym = %d, num_of_tus = %d\n", 748 tu->valid_boundary_link, tu->n_tus); 749 750 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 751 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 752 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 753 temp2_fp = temp1_fp - temp2_fp; 754 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 755 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 756 757 temp = drm_fixp2int(temp2_fp); 758 if (temp && temp2_fp) 759 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 760 else 761 tu->extra_bytes = 0; 762 763 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 764 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 765 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 766 767 if (temp && temp1_fp) 768 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 769 else 770 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 771 772 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 773 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 774 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 775 776 if (temp1_fp) 777 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 778 else 779 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 780 781 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 782 783 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 784 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 785 786 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 787 tu->filler_size + tu->extra_buffer_margin; 788 789 tu->resulting_valid_fp = 790 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 791 792 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 793 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 794 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 795 796 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 797 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 798 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 799 800 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 801 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 802 803 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 804 tu->delay_start_time_fp); 805 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 806 tu->min_hblank_violated = 1; 807 808 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 809 810 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 811 tu->delay_start_time_fp); 812 if (compare_result_2 == 2) 813 tu->min_hblank_violated = 1; 814 815 tu->delay_start_time_fp = 0; 816 817 /* brute force */ 818 819 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 820 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 821 822 temp = drm_fixp2int(tu->diff_abs_fp); 823 if (!temp && tu->diff_abs_fp <= 0xffff) 824 tu->diff_abs_fp = 0; 825 826 /* if(diff_abs < 0) diff_abs *= -1 */ 827 if (tu->diff_abs_fp < 0) 828 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 829 830 tu->boundary_mod_lower_err = 0; 831 if ((tu->diff_abs_fp != 0 && 832 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 833 (tu->even_distribution_legacy == 0) || 834 (DP_BRUTE_FORCE == 1))) || 835 (tu->min_hblank_violated == 1)) { 836 do { 837 tu->err_fp = drm_fixp_from_fraction(1000, 1); 838 839 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 840 temp2_fp = drm_fixp_from_fraction( 841 tu->delay_start_link_extra_pixclk, 1); 842 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 843 844 if (temp1_fp) 845 tu->extra_buffer_margin = 846 drm_fixp2int_ceil(temp1_fp); 847 else 848 tu->extra_buffer_margin = 0; 849 850 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 851 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 852 853 if (temp1_fp) 854 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 855 else 856 tu->n_symbols = 0; 857 858 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 859 for (tu->i_upper_boundary_count = 1; 860 tu->i_upper_boundary_count <= 15; 861 tu->i_upper_boundary_count++) { 862 for (tu->i_lower_boundary_count = 1; 863 tu->i_lower_boundary_count <= 15; 864 tu->i_lower_boundary_count++) { 865 _tu_valid_boundary_calc(tu); 866 } 867 } 868 } 869 tu->delay_start_link_extra_pixclk--; 870 } while (tu->boundary_moderation_en != true && 871 tu->boundary_mod_lower_err == 1 && 872 tu->delay_start_link_extra_pixclk != 0); 873 874 if (tu->boundary_moderation_en == true) { 875 temp1_fp = drm_fixp_from_fraction( 876 (tu->upper_boundary_count * 877 tu->valid_boundary_link + 878 tu->lower_boundary_count * 879 (tu->valid_boundary_link - 1)), 1); 880 temp2_fp = drm_fixp_from_fraction( 881 (tu->upper_boundary_count + 882 tu->lower_boundary_count), 1); 883 tu->resulting_valid_fp = 884 drm_fixp_div(temp1_fp, temp2_fp); 885 886 temp1_fp = drm_fixp_from_fraction( 887 tu->tu_size_desired, 1); 888 tu->ratio_by_tu_fp = 889 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 890 891 tu->valid_lower_boundary_link = 892 tu->valid_boundary_link - 1; 893 894 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 895 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 896 temp2_fp = drm_fixp_div(temp1_fp, 897 tu->resulting_valid_fp); 898 tu->n_tus = drm_fixp2int(temp2_fp); 899 900 tu->tu_size_minus1 = tu->tu_size_desired - 1; 901 tu->even_distribution_BF = 1; 902 903 temp1_fp = 904 drm_fixp_from_fraction(tu->tu_size_desired, 1); 905 temp2_fp = 906 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 907 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 908 } 909 } 910 911 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 912 913 if (temp2_fp) 914 temp = drm_fixp2int_ceil(temp2_fp); 915 else 916 temp = 0; 917 918 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 919 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 920 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 921 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 922 temp1_fp = drm_fixp_from_fraction(temp, 1); 923 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 924 temp = drm_fixp2int(temp2_fp); 925 926 if (tu->async_en) 927 tu->delay_start_link += (int)temp; 928 929 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 930 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 931 932 /* OUTPUTS */ 933 tu_table->valid_boundary_link = tu->valid_boundary_link; 934 tu_table->delay_start_link = tu->delay_start_link; 935 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 936 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 937 tu_table->upper_boundary_count = tu->upper_boundary_count; 938 tu_table->lower_boundary_count = tu->lower_boundary_count; 939 tu_table->tu_size_minus1 = tu->tu_size_minus1; 940 941 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", 942 tu_table->valid_boundary_link); 943 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", 944 tu_table->delay_start_link); 945 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", 946 tu_table->boundary_moderation_en); 947 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", 948 tu_table->valid_lower_boundary_link); 949 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", 950 tu_table->upper_boundary_count); 951 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", 952 tu_table->lower_boundary_count); 953 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", 954 tu_table->tu_size_minus1); 955 956 kfree(tu); 957 } 958 959 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl, 960 struct msm_dp_vc_tu_mapping_table *tu_table) 961 { 962 struct msm_dp_tu_calc_input in; 963 struct drm_display_mode *drm_mode; 964 965 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode; 966 967 in.lclk = ctrl->link->link_params.rate / 1000; 968 in.pclk_khz = drm_mode->clock; 969 in.hactive = drm_mode->hdisplay; 970 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 971 in.nlanes = ctrl->link->link_params.num_lanes; 972 in.bpp = ctrl->panel->msm_dp_mode.bpp; 973 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; 974 in.dsc_en = 0; 975 in.async_en = 0; 976 in.fec_en = 0; 977 in.num_of_dsc_slices = 0; 978 in.compress_ratio = 100; 979 980 _dp_ctrl_calc_tu(ctrl, &in, tu_table); 981 } 982 983 static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) 984 { 985 u32 msm_dp_tu = 0x0; 986 u32 valid_boundary = 0x0; 987 u32 valid_boundary2 = 0x0; 988 struct msm_dp_vc_tu_mapping_table tu_calc_table; 989 990 msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 991 992 msm_dp_tu |= tu_calc_table.tu_size_minus1; 993 valid_boundary |= tu_calc_table.valid_boundary_link; 994 valid_boundary |= (tu_calc_table.delay_start_link << 16); 995 996 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 997 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 998 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 999 1000 if (tu_calc_table.boundary_moderation_en) 1001 valid_boundary2 |= BIT(0); 1002 1003 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 1004 msm_dp_tu, valid_boundary, valid_boundary2); 1005 1006 msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 1007 msm_dp_tu, valid_boundary, valid_boundary2); 1008 } 1009 1010 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) 1011 { 1012 int ret = 0; 1013 1014 if (!wait_for_completion_timeout(&ctrl->video_comp, 1015 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 1016 DRM_ERROR("wait4video timedout\n"); 1017 ret = -ETIMEDOUT; 1018 } 1019 return ret; 1020 } 1021 1022 static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl, 1023 u8 v_level, u8 p_level) 1024 { 1025 union phy_configure_opts *phy_opts = &ctrl->phy_opts; 1026 1027 /* TODO: Update for all lanes instead of just first one */ 1028 phy_opts->dp.voltage[0] = v_level; 1029 phy_opts->dp.pre[0] = p_level; 1030 phy_opts->dp.set_voltages = 1; 1031 phy_configure(ctrl->phy, phy_opts); 1032 phy_opts->dp.set_voltages = 0; 1033 1034 return 0; 1035 } 1036 1037 static int msm_dp_ctrl_update_phy_vx_px(struct msm_dp_ctrl_private *ctrl, 1038 enum drm_dp_phy dp_phy) 1039 { 1040 struct msm_dp_link *link = ctrl->link; 1041 int lane, lane_cnt, reg; 1042 int ret = 0; 1043 u8 buf[4]; 1044 u32 max_level_reached = 0; 1045 u32 voltage_swing_level = link->phy_params.v_level; 1046 u32 pre_emphasis_level = link->phy_params.p_level; 1047 1048 drm_dbg_dp(ctrl->drm_dev, 1049 "voltage level: %d emphasis level: %d\n", 1050 voltage_swing_level, pre_emphasis_level); 1051 ret = msm_dp_ctrl_set_vx_px(ctrl, 1052 voltage_swing_level, pre_emphasis_level); 1053 1054 if (ret) 1055 return ret; 1056 1057 if (voltage_swing_level >= DP_TRAIN_LEVEL_MAX) { 1058 drm_dbg_dp(ctrl->drm_dev, 1059 "max. voltage swing level reached %d\n", 1060 voltage_swing_level); 1061 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1062 } 1063 1064 if (pre_emphasis_level >= DP_TRAIN_LEVEL_MAX) { 1065 drm_dbg_dp(ctrl->drm_dev, 1066 "max. pre-emphasis level reached %d\n", 1067 pre_emphasis_level); 1068 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1069 } 1070 1071 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1072 1073 lane_cnt = ctrl->link->link_params.num_lanes; 1074 for (lane = 0; lane < lane_cnt; lane++) 1075 buf[lane] = voltage_swing_level | pre_emphasis_level 1076 | max_level_reached; 1077 1078 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", 1079 voltage_swing_level | pre_emphasis_level); 1080 1081 if (dp_phy == DP_PHY_DPRX) 1082 reg = DP_TRAINING_LANE0_SET; 1083 else 1084 reg = DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 1085 1086 ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt); 1087 if (ret == lane_cnt) 1088 ret = 0; 1089 1090 return ret; 1091 } 1092 1093 static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl, 1094 u8 pattern, enum drm_dp_phy dp_phy) 1095 { 1096 u8 buf; 1097 int reg; 1098 int ret = 0; 1099 1100 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); 1101 1102 buf = pattern; 1103 1104 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1105 buf |= DP_LINK_SCRAMBLING_DISABLE; 1106 1107 if (dp_phy == DP_PHY_DPRX) 1108 reg = DP_TRAINING_PATTERN_SET; 1109 else 1110 reg = DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 1111 1112 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf); 1113 return ret == 1; 1114 } 1115 1116 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, 1117 int *training_step, enum drm_dp_phy dp_phy) 1118 { 1119 int delay_us; 1120 int tries, old_v_level, ret = 0; 1121 u8 link_status[DP_LINK_STATUS_SIZE]; 1122 int const maximum_retries = 4; 1123 1124 delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, 1125 ctrl->panel->dpcd, dp_phy, false); 1126 1127 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1128 1129 *training_step = DP_TRAINING_1; 1130 1131 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1132 if (ret) 1133 return ret; 1134 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1135 DP_LINK_SCRAMBLING_DISABLE, dp_phy); 1136 1137 msm_dp_link_reset_phy_params_vx_px(ctrl->link); 1138 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1139 if (ret) 1140 return ret; 1141 1142 tries = 0; 1143 old_v_level = ctrl->link->phy_params.v_level; 1144 for (tries = 0; tries < maximum_retries; tries++) { 1145 fsleep(delay_us); 1146 1147 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); 1148 if (ret) 1149 return ret; 1150 1151 if (drm_dp_clock_recovery_ok(link_status, 1152 ctrl->link->link_params.num_lanes)) { 1153 return 0; 1154 } 1155 1156 if (ctrl->link->phy_params.v_level >= 1157 DP_TRAIN_LEVEL_MAX) { 1158 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1159 return -EAGAIN; 1160 } 1161 1162 if (old_v_level != ctrl->link->phy_params.v_level) { 1163 tries = 0; 1164 old_v_level = ctrl->link->phy_params.v_level; 1165 } 1166 1167 msm_dp_link_adjust_levels(ctrl->link, link_status); 1168 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1169 if (ret) 1170 return ret; 1171 } 1172 1173 DRM_ERROR("max tries reached\n"); 1174 return -ETIMEDOUT; 1175 } 1176 1177 static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl) 1178 { 1179 int ret = 0; 1180 1181 switch (ctrl->link->link_params.rate) { 1182 case 810000: 1183 ctrl->link->link_params.rate = 540000; 1184 break; 1185 case 540000: 1186 ctrl->link->link_params.rate = 270000; 1187 break; 1188 case 270000: 1189 ctrl->link->link_params.rate = 162000; 1190 break; 1191 case 162000: 1192 default: 1193 ret = -EINVAL; 1194 break; 1195 } 1196 1197 if (!ret) { 1198 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", 1199 ctrl->link->link_params.rate); 1200 } 1201 1202 return ret; 1203 } 1204 1205 static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl) 1206 { 1207 1208 if (ctrl->link->link_params.num_lanes == 1) 1209 return -1; 1210 1211 ctrl->link->link_params.num_lanes /= 2; 1212 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1213 1214 ctrl->link->phy_params.p_level = 0; 1215 ctrl->link->phy_params.v_level = 0; 1216 1217 return 0; 1218 } 1219 1220 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl, 1221 enum drm_dp_phy dp_phy) 1222 { 1223 int delay_us; 1224 1225 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); 1226 1227 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, 1228 ctrl->panel->dpcd, dp_phy, false); 1229 fsleep(delay_us); 1230 } 1231 1232 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, 1233 int *training_step, enum drm_dp_phy dp_phy) 1234 { 1235 int delay_us; 1236 int tries = 0, ret = 0; 1237 u8 pattern; 1238 u32 state_ctrl_bit; 1239 int const maximum_retries = 5; 1240 u8 link_status[DP_LINK_STATUS_SIZE]; 1241 1242 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, 1243 ctrl->panel->dpcd, dp_phy, false); 1244 1245 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1246 1247 *training_step = DP_TRAINING_2; 1248 1249 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { 1250 pattern = DP_TRAINING_PATTERN_4; 1251 state_ctrl_bit = 4; 1252 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { 1253 pattern = DP_TRAINING_PATTERN_3; 1254 state_ctrl_bit = 3; 1255 } else { 1256 pattern = DP_TRAINING_PATTERN_2; 1257 state_ctrl_bit = 2; 1258 } 1259 1260 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1261 if (ret) 1262 return ret; 1263 1264 msm_dp_ctrl_train_pattern_set(ctrl, pattern, dp_phy); 1265 1266 for (tries = 0; tries <= maximum_retries; tries++) { 1267 fsleep(delay_us); 1268 1269 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); 1270 if (ret) 1271 return ret; 1272 1273 if (drm_dp_channel_eq_ok(link_status, 1274 ctrl->link->link_params.num_lanes)) { 1275 return 0; 1276 } 1277 1278 msm_dp_link_adjust_levels(ctrl->link, link_status); 1279 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1280 if (ret) 1281 return ret; 1282 1283 } 1284 1285 return -ETIMEDOUT; 1286 } 1287 1288 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, 1289 int *training_step, enum drm_dp_phy dp_phy) 1290 { 1291 int ret; 1292 1293 ret = msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy); 1294 if (ret) { 1295 DRM_ERROR("link training #1 on phy %d failed. ret=%d\n", dp_phy, ret); 1296 return ret; 1297 } 1298 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy); 1299 1300 ret = msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy); 1301 if (ret) { 1302 DRM_ERROR("link training #2 on phy %d failed. ret=%d\n", dp_phy, ret); 1303 return ret; 1304 } 1305 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy); 1306 1307 return 0; 1308 } 1309 1310 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, 1311 int *training_step) 1312 { 1313 int i; 1314 int ret = 0; 1315 const u8 *dpcd = ctrl->panel->dpcd; 1316 u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; 1317 u8 assr; 1318 struct msm_dp_link_info link_info = {0}; 1319 1320 msm_dp_ctrl_config_ctrl(ctrl); 1321 1322 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1323 link_info.rate = ctrl->link->link_params.rate; 1324 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1325 1326 msm_dp_aux_link_configure(ctrl->aux, &link_info); 1327 1328 if (drm_dp_max_downspread(dpcd)) 1329 encoding[0] |= DP_SPREAD_AMP_0_5; 1330 1331 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ 1332 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); 1333 1334 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { 1335 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 1336 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, 1337 &assr, 1); 1338 } 1339 1340 for (i = ctrl->link->lttpr_count - 1; i >= 0; i--) { 1341 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1342 1343 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy); 1344 msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy); 1345 1346 if (ret) 1347 break; 1348 } 1349 1350 if (ret) { 1351 DRM_ERROR("link training of LTTPR(s) failed. ret=%d\n", ret); 1352 goto end; 1353 } 1354 1355 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX); 1356 if (ret) { 1357 DRM_ERROR("link training on sink failed. ret=%d\n", ret); 1358 goto end; 1359 } 1360 1361 end: 1362 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1363 1364 return ret; 1365 } 1366 1367 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, 1368 int *training_step) 1369 { 1370 int ret = 0; 1371 1372 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1373 1374 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1375 return ret; 1376 1377 /* 1378 * As part of previous calls, DP controller state might have 1379 * transitioned to PUSH_IDLE. In order to start transmitting 1380 * a link training pattern, we have to first do soft reset. 1381 */ 1382 1383 ret = msm_dp_ctrl_link_train(ctrl, training_step); 1384 1385 return ret; 1386 } 1387 1388 int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1389 { 1390 struct msm_dp_ctrl_private *ctrl; 1391 int ret = 0; 1392 1393 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1394 1395 if (ctrl->core_clks_on) { 1396 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); 1397 return 0; 1398 } 1399 1400 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); 1401 if (ret) 1402 return ret; 1403 1404 ctrl->core_clks_on = true; 1405 1406 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); 1407 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1408 str_on_off(ctrl->stream_clks_on), 1409 str_on_off(ctrl->link_clks_on), 1410 str_on_off(ctrl->core_clks_on)); 1411 1412 return 0; 1413 } 1414 1415 void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1416 { 1417 struct msm_dp_ctrl_private *ctrl; 1418 1419 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1420 1421 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); 1422 1423 ctrl->core_clks_on = false; 1424 1425 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); 1426 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1427 str_on_off(ctrl->stream_clks_on), 1428 str_on_off(ctrl->link_clks_on), 1429 str_on_off(ctrl->core_clks_on)); 1430 } 1431 1432 static int msm_dp_ctrl_link_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1433 { 1434 struct msm_dp_ctrl_private *ctrl; 1435 int ret = 0; 1436 1437 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1438 1439 if (ctrl->link_clks_on) { 1440 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); 1441 return 0; 1442 } 1443 1444 if (!ctrl->core_clks_on) { 1445 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); 1446 1447 msm_dp_ctrl_core_clk_enable(msm_dp_ctrl); 1448 } 1449 1450 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); 1451 if (ret) 1452 return ret; 1453 1454 ctrl->link_clks_on = true; 1455 1456 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); 1457 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1458 str_on_off(ctrl->stream_clks_on), 1459 str_on_off(ctrl->link_clks_on), 1460 str_on_off(ctrl->core_clks_on)); 1461 1462 return 0; 1463 } 1464 1465 static void msm_dp_ctrl_link_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1466 { 1467 struct msm_dp_ctrl_private *ctrl; 1468 1469 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1470 1471 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); 1472 1473 ctrl->link_clks_on = false; 1474 1475 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); 1476 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1477 str_on_off(ctrl->stream_clks_on), 1478 str_on_off(ctrl->link_clks_on), 1479 str_on_off(ctrl->core_clks_on)); 1480 } 1481 1482 static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) 1483 { 1484 int ret = 0; 1485 struct phy *phy = ctrl->phy; 1486 const u8 *dpcd = ctrl->panel->dpcd; 1487 1488 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1489 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; 1490 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); 1491 1492 phy_configure(phy, &ctrl->phy_opts); 1493 phy_power_on(phy); 1494 1495 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); 1496 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); 1497 if (ret) 1498 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1499 1500 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); 1501 1502 return ret; 1503 } 1504 1505 void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enable) 1506 { 1507 struct msm_dp_ctrl_private *ctrl; 1508 1509 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1510 1511 msm_dp_catalog_ctrl_reset(ctrl->catalog); 1512 1513 /* 1514 * all dp controller programmable registers will not 1515 * be reset to default value after DP_SW_RESET 1516 * therefore interrupt mask bits have to be updated 1517 * to enable/disable interrupts 1518 */ 1519 msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1520 } 1521 1522 void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) 1523 { 1524 u8 cfg; 1525 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1526 struct msm_dp_ctrl_private, msm_dp_ctrl); 1527 1528 if (!ctrl->panel->psr_cap.version) 1529 return; 1530 1531 msm_dp_catalog_ctrl_config_psr(ctrl->catalog); 1532 1533 cfg = DP_PSR_ENABLE; 1534 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); 1535 } 1536 1537 void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) 1538 { 1539 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1540 struct msm_dp_ctrl_private, msm_dp_ctrl); 1541 1542 if (!ctrl->panel->psr_cap.version) 1543 return; 1544 1545 /* 1546 * When entering PSR, 1547 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT 1548 * 2. Turn off video 1549 * 3. Disable the mainlink 1550 * 1551 * When exiting PSR, 1552 * 1. Enable the mainlink 1553 * 2. Send the PSR exit SDP 1554 */ 1555 if (enter) { 1556 reinit_completion(&ctrl->psr_op_comp); 1557 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true); 1558 1559 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, 1560 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { 1561 DRM_ERROR("PSR_ENTRY timedout\n"); 1562 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1563 return; 1564 } 1565 1566 msm_dp_ctrl_push_idle(msm_dp_ctrl); 1567 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1568 1569 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); 1570 } else { 1571 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); 1572 1573 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1574 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1575 msm_dp_ctrl_wait4video_ready(ctrl); 1576 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1577 } 1578 } 1579 1580 void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) 1581 { 1582 struct msm_dp_ctrl_private *ctrl; 1583 struct phy *phy; 1584 1585 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1586 phy = ctrl->phy; 1587 1588 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); 1589 phy_init(phy); 1590 1591 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1592 phy, phy->init_count, phy->power_count); 1593 } 1594 1595 void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl) 1596 { 1597 struct msm_dp_ctrl_private *ctrl; 1598 struct phy *phy; 1599 1600 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1601 phy = ctrl->phy; 1602 1603 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); 1604 phy_exit(phy); 1605 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1606 phy, phy->init_count, phy->power_count); 1607 } 1608 1609 static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) 1610 { 1611 struct phy *phy = ctrl->phy; 1612 int ret = 0; 1613 1614 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1615 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1616 phy_configure(phy, &ctrl->phy_opts); 1617 /* 1618 * Disable and re-enable the mainlink clock since the 1619 * link clock might have been adjusted as part of the 1620 * link maintenance. 1621 */ 1622 dev_pm_opp_set_rate(ctrl->dev, 0); 1623 1624 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 1625 1626 phy_power_off(phy); 1627 /* hw recommended delay before re-enabling clocks */ 1628 msleep(20); 1629 1630 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 1631 if (ret) { 1632 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1633 return ret; 1634 } 1635 1636 return ret; 1637 } 1638 1639 static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) 1640 { 1641 struct phy *phy; 1642 1643 phy = ctrl->phy; 1644 1645 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1646 1647 msm_dp_catalog_ctrl_reset(ctrl->catalog); 1648 1649 dev_pm_opp_set_rate(ctrl->dev, 0); 1650 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 1651 1652 phy_power_off(phy); 1653 1654 /* aux channel down, reinit phy */ 1655 phy_exit(phy); 1656 phy_init(phy); 1657 1658 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1659 phy, phy->init_count, phy->power_count); 1660 return 0; 1661 } 1662 1663 static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) 1664 { 1665 int ret = 0; 1666 int training_step = DP_TRAINING_NONE; 1667 1668 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); 1669 1670 ctrl->link->phy_params.p_level = 0; 1671 ctrl->link->phy_params.v_level = 0; 1672 1673 ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1674 if (ret) 1675 goto end; 1676 1677 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); 1678 1679 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1680 1681 ret = msm_dp_ctrl_wait4video_ready(ctrl); 1682 end: 1683 return ret; 1684 } 1685 1686 static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) 1687 { 1688 bool success = false; 1689 u32 pattern_sent = 0x0; 1690 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1691 1692 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); 1693 1694 if (msm_dp_ctrl_set_vx_px(ctrl, 1695 ctrl->link->phy_params.v_level, 1696 ctrl->link->phy_params.p_level)) { 1697 DRM_ERROR("Failed to set v/p levels\n"); 1698 return false; 1699 } 1700 msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1701 msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); 1702 msm_dp_link_send_test_response(ctrl->link); 1703 1704 pattern_sent = msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1705 1706 switch (pattern_sent) { 1707 case MR_LINK_TRAINING1: 1708 success = (pattern_requested == 1709 DP_PHY_TEST_PATTERN_D10_2); 1710 break; 1711 case MR_LINK_SYMBOL_ERM: 1712 success = ((pattern_requested == 1713 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1714 (pattern_requested == 1715 DP_PHY_TEST_PATTERN_CP2520)); 1716 break; 1717 case MR_LINK_PRBS7: 1718 success = (pattern_requested == 1719 DP_PHY_TEST_PATTERN_PRBS7); 1720 break; 1721 case MR_LINK_CUSTOM80: 1722 success = (pattern_requested == 1723 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1724 break; 1725 case MR_LINK_TRAINING4: 1726 success = (pattern_requested == 1727 DP_PHY_TEST_PATTERN_SEL_MASK); 1728 break; 1729 default: 1730 success = false; 1731 } 1732 1733 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", 1734 success ? "success" : "failed", pattern_requested); 1735 return success; 1736 } 1737 1738 static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl) 1739 { 1740 int ret; 1741 unsigned long pixel_rate; 1742 1743 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1744 drm_dbg_dp(ctrl->drm_dev, 1745 "no test pattern selected by sink\n"); 1746 return 0; 1747 } 1748 1749 /* 1750 * The global reset will need DP link related clocks to be 1751 * running. Add the global reset just before disabling the 1752 * link clocks and core clocks. 1753 */ 1754 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); 1755 1756 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); 1757 if (ret) { 1758 DRM_ERROR("failed to enable DP link controller\n"); 1759 return ret; 1760 } 1761 1762 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; 1763 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1764 if (ret) { 1765 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1766 return ret; 1767 } 1768 1769 if (ctrl->stream_clks_on) { 1770 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 1771 } else { 1772 ret = clk_prepare_enable(ctrl->pixel_clk); 1773 if (ret) { 1774 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1775 return ret; 1776 } 1777 ctrl->stream_clks_on = true; 1778 } 1779 1780 msm_dp_ctrl_send_phy_test_pattern(ctrl); 1781 1782 return 0; 1783 } 1784 1785 void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl) 1786 { 1787 struct msm_dp_ctrl_private *ctrl; 1788 u32 sink_request = 0x0; 1789 1790 if (!msm_dp_ctrl) { 1791 DRM_ERROR("invalid input\n"); 1792 return; 1793 } 1794 1795 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1796 sink_request = ctrl->link->sink_request; 1797 1798 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1799 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); 1800 if (msm_dp_ctrl_process_phy_test_request(ctrl)) { 1801 DRM_ERROR("process phy_test_req failed\n"); 1802 return; 1803 } 1804 } 1805 1806 if (sink_request & DP_LINK_STATUS_UPDATED) { 1807 if (msm_dp_ctrl_link_maintenance(ctrl)) { 1808 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1809 return; 1810 } 1811 } 1812 1813 if (sink_request & DP_TEST_LINK_TRAINING) { 1814 msm_dp_link_send_test_response(ctrl->link); 1815 if (msm_dp_ctrl_link_maintenance(ctrl)) { 1816 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1817 return; 1818 } 1819 } 1820 } 1821 1822 static bool msm_dp_ctrl_clock_recovery_any_ok( 1823 const u8 link_status[DP_LINK_STATUS_SIZE], 1824 int lane_count) 1825 { 1826 int reduced_cnt; 1827 1828 if (lane_count <= 1) 1829 return false; 1830 1831 /* 1832 * only interested in the lane number after reduced 1833 * lane_count = 4, then only interested in 2 lanes 1834 * lane_count = 2, then only interested in 1 lane 1835 */ 1836 reduced_cnt = lane_count >> 1; 1837 1838 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 1839 } 1840 1841 static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) 1842 { 1843 u8 link_status[DP_LINK_STATUS_SIZE]; 1844 int num_lanes = ctrl->link->link_params.num_lanes; 1845 1846 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1847 1848 return drm_dp_channel_eq_ok(link_status, num_lanes); 1849 } 1850 1851 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) 1852 { 1853 int rc = 0; 1854 struct msm_dp_ctrl_private *ctrl; 1855 u32 rate; 1856 int link_train_max_retries = 5; 1857 u32 const phy_cts_pixel_clk_khz = 148500; 1858 u8 link_status[DP_LINK_STATUS_SIZE]; 1859 unsigned int training_step; 1860 unsigned long pixel_rate; 1861 1862 if (!msm_dp_ctrl) 1863 return -EINVAL; 1864 1865 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1866 1867 rate = ctrl->panel->link_info.rate; 1868 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; 1869 1870 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); 1871 1872 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1873 drm_dbg_dp(ctrl->drm_dev, 1874 "using phy test link parameters\n"); 1875 if (!pixel_rate) 1876 pixel_rate = phy_cts_pixel_clk_khz; 1877 } else { 1878 ctrl->link->link_params.rate = rate; 1879 ctrl->link->link_params.num_lanes = 1880 ctrl->panel->link_info.num_lanes; 1881 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 1882 pixel_rate >>= 1; 1883 } 1884 1885 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 1886 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, 1887 pixel_rate); 1888 1889 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 1890 if (rc) 1891 return rc; 1892 1893 while (--link_train_max_retries) { 1894 training_step = DP_TRAINING_NONE; 1895 rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1896 if (rc == 0) { 1897 /* training completed successfully */ 1898 break; 1899 } else if (training_step == DP_TRAINING_1) { 1900 /* link train_1 failed */ 1901 if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) 1902 break; 1903 1904 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1905 1906 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 1907 if (rc < 0) { /* already in RBR = 1.6G */ 1908 if (msm_dp_ctrl_clock_recovery_any_ok(link_status, 1909 ctrl->link->link_params.num_lanes)) { 1910 /* 1911 * some lanes are ready, 1912 * reduce lane number 1913 */ 1914 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); 1915 if (rc < 0) { /* lane == 1 already */ 1916 /* end with failure */ 1917 break; 1918 } 1919 } else { 1920 /* end with failure */ 1921 break; /* lane == 1 already */ 1922 } 1923 } 1924 } else if (training_step == DP_TRAINING_2) { 1925 /* link train_2 failed */ 1926 if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) 1927 break; 1928 1929 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1930 1931 if (!drm_dp_clock_recovery_ok(link_status, 1932 ctrl->link->link_params.num_lanes)) 1933 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 1934 else 1935 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); 1936 1937 if (rc < 0) { 1938 /* end with failure */ 1939 break; /* lane == 1 already */ 1940 } 1941 1942 /* stop link training before start re training */ 1943 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); 1944 } 1945 1946 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl); 1947 if (rc) { 1948 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); 1949 break; 1950 } 1951 } 1952 1953 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1954 return rc; 1955 1956 if (rc == 0) { /* link train successfully */ 1957 /* 1958 * do not stop train pattern here 1959 * stop link training at on_stream 1960 * to pass compliance test 1961 */ 1962 } else { 1963 /* 1964 * link training failed 1965 * end txing train pattern here 1966 */ 1967 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); 1968 1969 msm_dp_ctrl_deinitialize_mainlink(ctrl); 1970 rc = -ECONNRESET; 1971 } 1972 1973 return rc; 1974 } 1975 1976 static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) 1977 { 1978 int training_step = DP_TRAINING_NONE; 1979 1980 return msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1981 } 1982 1983 int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) 1984 { 1985 int ret = 0; 1986 bool mainlink_ready = false; 1987 struct msm_dp_ctrl_private *ctrl; 1988 unsigned long pixel_rate; 1989 unsigned long pixel_rate_orig; 1990 1991 if (!msm_dp_ctrl) 1992 return -EINVAL; 1993 1994 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1995 1996 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; 1997 1998 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 1999 pixel_rate >>= 1; 2000 2001 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 2002 ctrl->link->link_params.rate, 2003 ctrl->link->link_params.num_lanes, pixel_rate); 2004 2005 drm_dbg_dp(ctrl->drm_dev, 2006 "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", 2007 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); 2008 2009 if (!ctrl->link_clks_on) { /* link clk is off */ 2010 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 2011 if (ret) { 2012 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 2013 goto end; 2014 } 2015 } 2016 2017 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 2018 if (ret) { 2019 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 2020 goto end; 2021 } 2022 2023 if (ctrl->stream_clks_on) { 2024 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 2025 } else { 2026 ret = clk_prepare_enable(ctrl->pixel_clk); 2027 if (ret) { 2028 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 2029 goto end; 2030 } 2031 ctrl->stream_clks_on = true; 2032 } 2033 2034 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) 2035 msm_dp_ctrl_link_retrain(ctrl); 2036 2037 /* stop txing train pattern to end link training */ 2038 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); 2039 2040 /* 2041 * Set up transfer unit values and set controller state to send 2042 * video. 2043 */ 2044 reinit_completion(&ctrl->video_comp); 2045 2046 msm_dp_ctrl_configure_source_params(ctrl); 2047 2048 msm_dp_catalog_ctrl_config_msa(ctrl->catalog, 2049 ctrl->link->link_params.rate, 2050 pixel_rate_orig, 2051 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); 2052 2053 msm_dp_ctrl_setup_tr_unit(ctrl); 2054 2055 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 2056 2057 ret = msm_dp_ctrl_wait4video_ready(ctrl); 2058 if (ret) 2059 return ret; 2060 2061 mainlink_ready = msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 2062 drm_dbg_dp(ctrl->drm_dev, 2063 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 2064 2065 end: 2066 return ret; 2067 } 2068 2069 void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) 2070 { 2071 struct msm_dp_ctrl_private *ctrl; 2072 struct phy *phy; 2073 2074 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2075 phy = ctrl->phy; 2076 2077 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2078 2079 /* set dongle to D3 (power off) mode */ 2080 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 2081 2082 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2083 2084 if (ctrl->stream_clks_on) { 2085 clk_disable_unprepare(ctrl->pixel_clk); 2086 ctrl->stream_clks_on = false; 2087 } 2088 2089 dev_pm_opp_set_rate(ctrl->dev, 0); 2090 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2091 2092 phy_power_off(phy); 2093 2094 /* aux channel down, reinit phy */ 2095 phy_exit(phy); 2096 phy_init(phy); 2097 2098 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 2099 phy, phy->init_count, phy->power_count); 2100 } 2101 2102 void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) 2103 { 2104 struct msm_dp_ctrl_private *ctrl; 2105 struct phy *phy; 2106 2107 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2108 phy = ctrl->phy; 2109 2110 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2111 2112 dev_pm_opp_set_rate(ctrl->dev, 0); 2113 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2114 2115 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", 2116 phy, phy->init_count, phy->power_count); 2117 2118 phy_power_off(phy); 2119 2120 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", 2121 phy, phy->init_count, phy->power_count); 2122 } 2123 2124 void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) 2125 { 2126 struct msm_dp_ctrl_private *ctrl; 2127 struct phy *phy; 2128 2129 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2130 phy = ctrl->phy; 2131 2132 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2133 2134 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2135 2136 msm_dp_catalog_ctrl_reset(ctrl->catalog); 2137 2138 if (ctrl->stream_clks_on) { 2139 clk_disable_unprepare(ctrl->pixel_clk); 2140 ctrl->stream_clks_on = false; 2141 } 2142 2143 dev_pm_opp_set_rate(ctrl->dev, 0); 2144 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2145 2146 phy_power_off(phy); 2147 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 2148 phy, phy->init_count, phy->power_count); 2149 } 2150 2151 irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) 2152 { 2153 struct msm_dp_ctrl_private *ctrl; 2154 u32 isr; 2155 irqreturn_t ret = IRQ_NONE; 2156 2157 if (!msm_dp_ctrl) 2158 return IRQ_NONE; 2159 2160 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2161 2162 if (ctrl->panel->psr_cap.version) { 2163 isr = msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); 2164 2165 if (isr) 2166 complete(&ctrl->psr_op_comp); 2167 2168 if (isr & PSR_EXIT_INT) 2169 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); 2170 2171 if (isr & PSR_UPDATE_INT) 2172 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); 2173 2174 if (isr & PSR_CAPTURE_INT) 2175 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); 2176 } 2177 2178 isr = msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog); 2179 2180 2181 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 2182 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); 2183 complete(&ctrl->video_comp); 2184 ret = IRQ_HANDLED; 2185 } 2186 2187 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 2188 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); 2189 complete(&ctrl->idle_comp); 2190 ret = IRQ_HANDLED; 2191 } 2192 2193 return ret; 2194 } 2195 2196 static const char *core_clks[] = { 2197 "core_iface", 2198 "core_aux", 2199 }; 2200 2201 static const char *ctrl_clks[] = { 2202 "ctrl_link", 2203 "ctrl_link_iface", 2204 }; 2205 2206 static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) 2207 { 2208 struct msm_dp_ctrl_private *ctrl; 2209 struct device *dev; 2210 int i, rc; 2211 2212 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2213 dev = ctrl->dev; 2214 2215 ctrl->num_core_clks = ARRAY_SIZE(core_clks); 2216 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); 2217 if (!ctrl->core_clks) 2218 return -ENOMEM; 2219 2220 for (i = 0; i < ctrl->num_core_clks; i++) 2221 ctrl->core_clks[i].id = core_clks[i]; 2222 2223 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); 2224 if (rc) 2225 return rc; 2226 2227 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); 2228 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); 2229 if (!ctrl->link_clks) 2230 return -ENOMEM; 2231 2232 for (i = 0; i < ctrl->num_link_clks; i++) 2233 ctrl->link_clks[i].id = ctrl_clks[i]; 2234 2235 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); 2236 if (rc) 2237 return rc; 2238 2239 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); 2240 if (IS_ERR(ctrl->pixel_clk)) 2241 return PTR_ERR(ctrl->pixel_clk); 2242 2243 return 0; 2244 } 2245 2246 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, 2247 struct msm_dp_panel *panel, struct drm_dp_aux *aux, 2248 struct msm_dp_catalog *catalog, 2249 struct phy *phy) 2250 { 2251 struct msm_dp_ctrl_private *ctrl; 2252 int ret; 2253 2254 if (!dev || !panel || !aux || 2255 !link || !catalog) { 2256 DRM_ERROR("invalid input\n"); 2257 return ERR_PTR(-EINVAL); 2258 } 2259 2260 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 2261 if (!ctrl) { 2262 DRM_ERROR("Mem allocation failure\n"); 2263 return ERR_PTR(-ENOMEM); 2264 } 2265 2266 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 2267 if (ret) { 2268 dev_err(dev, "invalid DP OPP table in device tree\n"); 2269 /* caller do PTR_ERR(opp_table) */ 2270 return (struct msm_dp_ctrl *)ERR_PTR(ret); 2271 } 2272 2273 /* OPP table is optional */ 2274 ret = devm_pm_opp_of_add_table(dev); 2275 if (ret) 2276 dev_err(dev, "failed to add DP OPP table\n"); 2277 2278 init_completion(&ctrl->idle_comp); 2279 init_completion(&ctrl->psr_op_comp); 2280 init_completion(&ctrl->video_comp); 2281 2282 /* in parameters */ 2283 ctrl->panel = panel; 2284 ctrl->aux = aux; 2285 ctrl->link = link; 2286 ctrl->catalog = catalog; 2287 ctrl->dev = dev; 2288 ctrl->phy = phy; 2289 2290 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); 2291 if (ret) { 2292 dev_err(dev, "failed to init clocks\n"); 2293 return ERR_PTR(ret); 2294 } 2295 2296 return &ctrl->msm_dp_ctrl; 2297 } 2298