1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 15 #include <drm/display/drm_dp_helper.h> 16 #include <drm/drm_fixed.h> 17 #include <drm/drm_print.h> 18 19 #include "dp_reg.h" 20 #include "dp_ctrl.h" 21 #include "dp_link.h" 22 23 #define DP_KHZ_TO_HZ 1000 24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 25 #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */ 26 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 27 28 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 29 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 30 31 #define MR_LINK_TRAINING1 0x8 32 #define MR_LINK_SYMBOL_ERM 0x80 33 #define MR_LINK_PRBS7 0x100 34 #define MR_LINK_CUSTOM80 0x200 35 #define MR_LINK_TRAINING4 0x40 36 37 enum { 38 DP_TRAINING_NONE, 39 DP_TRAINING_1, 40 DP_TRAINING_2, 41 }; 42 43 struct dp_tu_calc_input { 44 u64 lclk; /* 162, 270, 540 and 810 */ 45 u64 pclk_khz; /* in KHz */ 46 u64 hactive; /* active h-width */ 47 u64 hporch; /* bp + fp + pulse */ 48 int nlanes; /* no.of.lanes */ 49 int bpp; /* bits */ 50 int pixel_enc; /* 444, 420, 422 */ 51 int dsc_en; /* dsc on/off */ 52 int async_en; /* async mode */ 53 int fec_en; /* fec */ 54 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 55 int num_of_dsc_slices; /* number of slices per line */ 56 }; 57 58 struct dp_vc_tu_mapping_table { 59 u32 vic; 60 u8 lanes; 61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 62 u8 bpp; 63 u8 valid_boundary_link; 64 u16 delay_start_link; 65 bool boundary_moderation_en; 66 u8 valid_lower_boundary_link; 67 u8 upper_boundary_count; 68 u8 lower_boundary_count; 69 u8 tu_size_minus1; 70 }; 71 72 struct dp_ctrl_private { 73 struct dp_ctrl dp_ctrl; 74 struct drm_device *drm_dev; 75 struct device *dev; 76 struct drm_dp_aux *aux; 77 struct dp_panel *panel; 78 struct dp_link *link; 79 struct dp_catalog *catalog; 80 81 struct phy *phy; 82 83 unsigned int num_core_clks; 84 struct clk_bulk_data *core_clks; 85 86 unsigned int num_link_clks; 87 struct clk_bulk_data *link_clks; 88 89 struct clk *pixel_clk; 90 91 union phy_configure_opts phy_opts; 92 93 struct completion idle_comp; 94 struct completion psr_op_comp; 95 struct completion video_comp; 96 97 bool core_clks_on; 98 bool link_clks_on; 99 bool stream_clks_on; 100 }; 101 102 static int dp_aux_link_configure(struct drm_dp_aux *aux, 103 struct dp_link_info *link) 104 { 105 u8 values[2]; 106 int err; 107 108 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 109 values[1] = link->num_lanes; 110 111 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 112 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 113 114 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 115 if (err < 0) 116 return err; 117 118 return 0; 119 } 120 121 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 122 { 123 struct dp_ctrl_private *ctrl; 124 125 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 126 127 reinit_completion(&ctrl->idle_comp); 128 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 129 130 if (!wait_for_completion_timeout(&ctrl->idle_comp, 131 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 132 pr_warn("PUSH_IDLE pattern timedout\n"); 133 134 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); 135 } 136 137 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 138 { 139 u32 config = 0, tbd; 140 const u8 *dpcd = ctrl->panel->dpcd; 141 142 /* Default-> LSCLK DIV: 1/4 LCLK */ 143 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 144 145 /* Scrambler reset enable */ 146 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 147 config |= DP_CONFIGURATION_CTRL_ASSR; 148 149 tbd = dp_link_get_test_bits_depth(ctrl->link, 150 ctrl->panel->dp_mode.bpp); 151 152 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 153 154 /* Num of Lanes */ 155 config |= ((ctrl->link->link_params.num_lanes - 1) 156 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 157 158 if (drm_dp_enhanced_frame_cap(dpcd)) 159 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 160 161 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 162 163 /* sync clock & static Mvid */ 164 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 165 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 166 167 if (ctrl->panel->psr_cap.version) 168 config |= DP_CONFIGURATION_CTRL_SEND_VSC; 169 170 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 171 } 172 173 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 174 { 175 u32 cc, tb; 176 177 dp_catalog_ctrl_lane_mapping(ctrl->catalog); 178 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 179 180 dp_ctrl_config_ctrl(ctrl); 181 182 tb = dp_link_get_test_bits_depth(ctrl->link, 183 ctrl->panel->dp_mode.bpp); 184 cc = dp_link_get_colorimetry_config(ctrl->link); 185 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 186 dp_panel_timing_cfg(ctrl->panel); 187 } 188 189 /* 190 * The structure and few functions present below are IP/Hardware 191 * specific implementation. Most of the implementation will not 192 * have coding comments 193 */ 194 struct tu_algo_data { 195 s64 lclk_fp; 196 s64 pclk_fp; 197 s64 lwidth; 198 s64 lwidth_fp; 199 s64 hbp_relative_to_pclk; 200 s64 hbp_relative_to_pclk_fp; 201 int nlanes; 202 int bpp; 203 int pixelEnc; 204 int dsc_en; 205 int async_en; 206 int bpc; 207 208 uint delay_start_link_extra_pixclk; 209 int extra_buffer_margin; 210 s64 ratio_fp; 211 s64 original_ratio_fp; 212 213 s64 err_fp; 214 s64 n_err_fp; 215 s64 n_n_err_fp; 216 int tu_size; 217 int tu_size_desired; 218 int tu_size_minus1; 219 220 int valid_boundary_link; 221 s64 resulting_valid_fp; 222 s64 total_valid_fp; 223 s64 effective_valid_fp; 224 s64 effective_valid_recorded_fp; 225 int n_tus; 226 int n_tus_per_lane; 227 int paired_tus; 228 int remainder_tus; 229 int remainder_tus_upper; 230 int remainder_tus_lower; 231 int extra_bytes; 232 int filler_size; 233 int delay_start_link; 234 235 int extra_pclk_cycles; 236 int extra_pclk_cycles_in_link_clk; 237 s64 ratio_by_tu_fp; 238 s64 average_valid2_fp; 239 int new_valid_boundary_link; 240 int remainder_symbols_exist; 241 int n_symbols; 242 s64 n_remainder_symbols_per_lane_fp; 243 s64 last_partial_tu_fp; 244 s64 TU_ratio_err_fp; 245 246 int n_tus_incl_last_incomplete_tu; 247 int extra_pclk_cycles_tmp; 248 int extra_pclk_cycles_in_link_clk_tmp; 249 int extra_required_bytes_new_tmp; 250 int filler_size_tmp; 251 int lower_filler_size_tmp; 252 int delay_start_link_tmp; 253 254 bool boundary_moderation_en; 255 int boundary_mod_lower_err; 256 int upper_boundary_count; 257 int lower_boundary_count; 258 int i_upper_boundary_count; 259 int i_lower_boundary_count; 260 int valid_lower_boundary_link; 261 int even_distribution_BF; 262 int even_distribution_legacy; 263 int even_distribution; 264 int min_hblank_violated; 265 s64 delay_start_time_fp; 266 s64 hbp_time_fp; 267 s64 hactive_time_fp; 268 s64 diff_abs_fp; 269 270 s64 ratio; 271 }; 272 273 static int _tu_param_compare(s64 a, s64 b) 274 { 275 u32 a_sign; 276 u32 b_sign; 277 s64 a_temp, b_temp, minus_1; 278 279 if (a == b) 280 return 0; 281 282 minus_1 = drm_fixp_from_fraction(-1, 1); 283 284 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 285 286 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 287 288 if (a_sign > b_sign) 289 return 2; 290 else if (b_sign > a_sign) 291 return 1; 292 293 if (!a_sign && !b_sign) { /* positive */ 294 if (a > b) 295 return 1; 296 else 297 return 2; 298 } else { /* negative */ 299 a_temp = drm_fixp_mul(a, minus_1); 300 b_temp = drm_fixp_mul(b, minus_1); 301 302 if (a_temp > b_temp) 303 return 2; 304 else 305 return 1; 306 } 307 } 308 309 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 310 struct tu_algo_data *tu) 311 { 312 int nlanes = in->nlanes; 313 int dsc_num_slices = in->num_of_dsc_slices; 314 int dsc_num_bytes = 0; 315 int numerator; 316 s64 pclk_dsc_fp; 317 s64 dwidth_dsc_fp; 318 s64 hbp_dsc_fp; 319 320 int tot_num_eoc_symbols = 0; 321 int tot_num_hor_bytes = 0; 322 int tot_num_dummy_bytes = 0; 323 int dwidth_dsc_bytes = 0; 324 int eoc_bytes = 0; 325 326 s64 temp1_fp, temp2_fp, temp3_fp; 327 328 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 329 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 330 tu->lwidth = in->hactive; 331 tu->hbp_relative_to_pclk = in->hporch; 332 tu->nlanes = in->nlanes; 333 tu->bpp = in->bpp; 334 tu->pixelEnc = in->pixel_enc; 335 tu->dsc_en = in->dsc_en; 336 tu->async_en = in->async_en; 337 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 338 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 339 340 if (tu->pixelEnc == 420) { 341 temp1_fp = drm_fixp_from_fraction(2, 1); 342 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 343 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 344 tu->hbp_relative_to_pclk_fp = 345 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 346 } 347 348 if (tu->pixelEnc == 422) { 349 switch (tu->bpp) { 350 case 24: 351 tu->bpp = 16; 352 tu->bpc = 8; 353 break; 354 case 30: 355 tu->bpp = 20; 356 tu->bpc = 10; 357 break; 358 default: 359 tu->bpp = 16; 360 tu->bpc = 8; 361 break; 362 } 363 } else { 364 tu->bpc = tu->bpp/3; 365 } 366 367 if (!in->dsc_en) 368 goto fec_check; 369 370 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 371 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 372 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 373 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 374 375 temp1_fp = drm_fixp_from_fraction(8, 1); 376 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 377 378 numerator = drm_fixp2int(temp3_fp); 379 380 dsc_num_bytes = numerator / dsc_num_slices; 381 eoc_bytes = dsc_num_bytes % nlanes; 382 tot_num_eoc_symbols = nlanes * dsc_num_slices; 383 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 384 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 385 386 if (dsc_num_bytes == 0) 387 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 388 389 dwidth_dsc_bytes = (tot_num_hor_bytes + 390 tot_num_eoc_symbols + 391 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 392 393 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 394 395 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 396 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 397 pclk_dsc_fp = temp1_fp; 398 399 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 400 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 401 hbp_dsc_fp = temp2_fp; 402 403 /* output */ 404 tu->pclk_fp = pclk_dsc_fp; 405 tu->lwidth_fp = dwidth_dsc_fp; 406 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 407 408 fec_check: 409 if (in->fec_en) { 410 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 411 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 412 } 413 } 414 415 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 416 { 417 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 418 int compare_result_1, compare_result_2, compare_result_3; 419 420 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 421 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 422 423 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 424 425 temp = (tu->i_upper_boundary_count * 426 tu->new_valid_boundary_link + 427 tu->i_lower_boundary_count * 428 (tu->new_valid_boundary_link-1)); 429 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 430 (tu->i_upper_boundary_count + 431 tu->i_lower_boundary_count)); 432 433 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 434 temp2_fp = tu->lwidth_fp; 435 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 436 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 437 tu->n_tus = drm_fixp2int(temp2_fp); 438 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 439 tu->n_tus += 1; 440 441 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 442 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 443 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 444 temp2_fp = temp1_fp - temp2_fp; 445 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 446 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 447 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 448 449 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 450 tu->last_partial_tu_fp = 451 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 452 temp1_fp); 453 454 if (tu->n_remainder_symbols_per_lane_fp != 0) 455 tu->remainder_symbols_exist = 1; 456 else 457 tu->remainder_symbols_exist = 0; 458 459 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 460 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 461 462 tu->paired_tus = (int)((tu->n_tus_per_lane) / 463 (tu->i_upper_boundary_count + 464 tu->i_lower_boundary_count)); 465 466 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 467 (tu->i_upper_boundary_count + 468 tu->i_lower_boundary_count); 469 470 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 471 tu->remainder_tus_upper = tu->i_upper_boundary_count; 472 tu->remainder_tus_lower = tu->remainder_tus - 473 tu->i_upper_boundary_count; 474 } else { 475 tu->remainder_tus_upper = tu->remainder_tus; 476 tu->remainder_tus_lower = 0; 477 } 478 479 temp = tu->paired_tus * (tu->i_upper_boundary_count * 480 tu->new_valid_boundary_link + 481 tu->i_lower_boundary_count * 482 (tu->new_valid_boundary_link - 1)) + 483 (tu->remainder_tus_upper * 484 tu->new_valid_boundary_link) + 485 (tu->remainder_tus_lower * 486 (tu->new_valid_boundary_link - 1)); 487 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 488 489 if (tu->remainder_symbols_exist) { 490 temp1_fp = tu->total_valid_fp + 491 tu->n_remainder_symbols_per_lane_fp; 492 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 493 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 494 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 495 } else { 496 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 497 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 498 } 499 tu->effective_valid_fp = temp1_fp; 500 501 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 502 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 503 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 504 505 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 506 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 507 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 508 509 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 510 511 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 512 temp2_fp = tu->lwidth_fp; 513 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 514 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 515 516 if (temp2_fp) 517 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 518 else 519 tu->n_tus_incl_last_incomplete_tu = 0; 520 521 temp1 = 0; 522 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 523 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 524 temp1_fp = tu->average_valid2_fp - temp2_fp; 525 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 526 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 527 528 if (temp1_fp) 529 temp1 = drm_fixp2int_ceil(temp1_fp); 530 531 temp = tu->i_upper_boundary_count * tu->nlanes; 532 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 533 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 534 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 535 temp2_fp = temp1_fp - temp2_fp; 536 temp1_fp = drm_fixp_from_fraction(temp, 1); 537 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 538 539 if (temp2_fp) 540 temp2 = drm_fixp2int_ceil(temp2_fp); 541 else 542 temp2 = 0; 543 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 544 545 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 546 temp2_fp = drm_fixp_from_fraction( 547 tu->extra_required_bytes_new_tmp, 1); 548 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 549 550 if (temp1_fp) 551 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 552 else 553 tu->extra_pclk_cycles_tmp = 0; 554 555 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 556 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 557 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 558 559 if (temp1_fp) 560 tu->extra_pclk_cycles_in_link_clk_tmp = 561 drm_fixp2int_ceil(temp1_fp); 562 else 563 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 564 565 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 566 567 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 568 569 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 570 tu->lower_filler_size_tmp + 571 tu->extra_buffer_margin; 572 573 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 574 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 575 576 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 577 if (compare_result_1 == 2) 578 compare_result_1 = 1; 579 else 580 compare_result_1 = 0; 581 582 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 583 if (compare_result_2 == 2) 584 compare_result_2 = 1; 585 else 586 compare_result_2 = 0; 587 588 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 589 tu->delay_start_time_fp); 590 if (compare_result_3 == 2) 591 compare_result_3 = 0; 592 else 593 compare_result_3 = 1; 594 595 if (((tu->even_distribution == 1) || 596 ((tu->even_distribution_BF == 0) && 597 (tu->even_distribution_legacy == 0))) && 598 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 599 compare_result_2 && 600 (compare_result_1 || (tu->min_hblank_violated == 1)) && 601 (tu->new_valid_boundary_link - 1) > 0 && 602 compare_result_3 && 603 (tu->delay_start_link_tmp <= 1023)) { 604 tu->upper_boundary_count = tu->i_upper_boundary_count; 605 tu->lower_boundary_count = tu->i_lower_boundary_count; 606 tu->err_fp = tu->n_n_err_fp; 607 tu->boundary_moderation_en = true; 608 tu->tu_size_desired = tu->tu_size; 609 tu->valid_boundary_link = tu->new_valid_boundary_link; 610 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 611 tu->even_distribution_BF = 1; 612 tu->delay_start_link = tu->delay_start_link_tmp; 613 } else if (tu->boundary_mod_lower_err == 0) { 614 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 615 tu->diff_abs_fp); 616 if (compare_result_1 == 2) 617 tu->boundary_mod_lower_err = 1; 618 } 619 } 620 621 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl, 622 struct dp_tu_calc_input *in, 623 struct dp_vc_tu_mapping_table *tu_table) 624 { 625 struct tu_algo_data *tu; 626 int compare_result_1, compare_result_2; 627 u64 temp = 0; 628 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 629 630 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 631 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 632 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 633 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 634 635 u8 DP_BRUTE_FORCE = 1; 636 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 637 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 638 uint HBLANK_MARGIN = 4; 639 640 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 641 if (!tu) 642 return; 643 644 dp_panel_update_tu_timings(in, tu); 645 646 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 647 648 temp1_fp = drm_fixp_from_fraction(4, 1); 649 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 650 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 651 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 652 653 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 654 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 655 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 656 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 657 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 658 659 tu->original_ratio_fp = tu->ratio_fp; 660 tu->boundary_moderation_en = false; 661 tu->upper_boundary_count = 0; 662 tu->lower_boundary_count = 0; 663 tu->i_upper_boundary_count = 0; 664 tu->i_lower_boundary_count = 0; 665 tu->valid_lower_boundary_link = 0; 666 tu->even_distribution_BF = 0; 667 tu->even_distribution_legacy = 0; 668 tu->even_distribution = 0; 669 tu->delay_start_time_fp = 0; 670 671 tu->err_fp = drm_fixp_from_fraction(1000, 1); 672 tu->n_err_fp = 0; 673 tu->n_n_err_fp = 0; 674 675 tu->ratio = drm_fixp2int(tu->ratio_fp); 676 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 677 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 678 if (temp2_fp != 0 && 679 !tu->ratio && tu->dsc_en == 0) { 680 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 681 tu->ratio = drm_fixp2int(tu->ratio_fp); 682 if (tu->ratio) 683 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 684 } 685 686 if (tu->ratio > 1) 687 tu->ratio = 1; 688 689 if (tu->ratio == 1) 690 goto tu_size_calc; 691 692 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 693 if (!compare_result_1 || compare_result_1 == 1) 694 compare_result_1 = 1; 695 else 696 compare_result_1 = 0; 697 698 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 699 if (!compare_result_2 || compare_result_2 == 2) 700 compare_result_2 = 1; 701 else 702 compare_result_2 = 0; 703 704 if (tu->dsc_en && compare_result_1 && compare_result_2) { 705 HBLANK_MARGIN += 4; 706 drm_dbg_dp(ctrl->drm_dev, 707 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN); 708 } 709 710 tu_size_calc: 711 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 712 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 713 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 714 temp = drm_fixp2int_ceil(temp2_fp); 715 temp1_fp = drm_fixp_from_fraction(temp, 1); 716 tu->n_err_fp = temp1_fp - temp2_fp; 717 718 if (tu->n_err_fp < tu->err_fp) { 719 tu->err_fp = tu->n_err_fp; 720 tu->tu_size_desired = tu->tu_size; 721 } 722 } 723 724 tu->tu_size_minus1 = tu->tu_size_desired - 1; 725 726 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 727 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 728 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 729 730 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 731 temp2_fp = tu->lwidth_fp; 732 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 733 734 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 735 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 736 tu->n_tus = drm_fixp2int(temp2_fp); 737 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 738 tu->n_tus += 1; 739 740 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 741 742 drm_dbg_dp(ctrl->drm_dev, 743 "n_sym = %d, num_of_tus = %d\n", 744 tu->valid_boundary_link, tu->n_tus); 745 746 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 747 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 748 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 749 temp2_fp = temp1_fp - temp2_fp; 750 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 751 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 752 753 temp = drm_fixp2int(temp2_fp); 754 if (temp && temp2_fp) 755 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 756 else 757 tu->extra_bytes = 0; 758 759 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 760 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 761 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 762 763 if (temp && temp1_fp) 764 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 765 else 766 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 767 768 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 769 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 770 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 771 772 if (temp1_fp) 773 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 774 else 775 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 776 777 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 778 779 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 780 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 781 782 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 783 tu->filler_size + tu->extra_buffer_margin; 784 785 tu->resulting_valid_fp = 786 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 787 788 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 789 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 790 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 791 792 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 793 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 794 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 795 796 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 797 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 798 799 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 800 tu->delay_start_time_fp); 801 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 802 tu->min_hblank_violated = 1; 803 804 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 805 806 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 807 tu->delay_start_time_fp); 808 if (compare_result_2 == 2) 809 tu->min_hblank_violated = 1; 810 811 tu->delay_start_time_fp = 0; 812 813 /* brute force */ 814 815 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 816 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 817 818 temp = drm_fixp2int(tu->diff_abs_fp); 819 if (!temp && tu->diff_abs_fp <= 0xffff) 820 tu->diff_abs_fp = 0; 821 822 /* if(diff_abs < 0) diff_abs *= -1 */ 823 if (tu->diff_abs_fp < 0) 824 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 825 826 tu->boundary_mod_lower_err = 0; 827 if ((tu->diff_abs_fp != 0 && 828 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 829 (tu->even_distribution_legacy == 0) || 830 (DP_BRUTE_FORCE == 1))) || 831 (tu->min_hblank_violated == 1)) { 832 do { 833 tu->err_fp = drm_fixp_from_fraction(1000, 1); 834 835 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 836 temp2_fp = drm_fixp_from_fraction( 837 tu->delay_start_link_extra_pixclk, 1); 838 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 839 840 if (temp1_fp) 841 tu->extra_buffer_margin = 842 drm_fixp2int_ceil(temp1_fp); 843 else 844 tu->extra_buffer_margin = 0; 845 846 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 847 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 848 849 if (temp1_fp) 850 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 851 else 852 tu->n_symbols = 0; 853 854 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 855 for (tu->i_upper_boundary_count = 1; 856 tu->i_upper_boundary_count <= 15; 857 tu->i_upper_boundary_count++) { 858 for (tu->i_lower_boundary_count = 1; 859 tu->i_lower_boundary_count <= 15; 860 tu->i_lower_boundary_count++) { 861 _tu_valid_boundary_calc(tu); 862 } 863 } 864 } 865 tu->delay_start_link_extra_pixclk--; 866 } while (tu->boundary_moderation_en != true && 867 tu->boundary_mod_lower_err == 1 && 868 tu->delay_start_link_extra_pixclk != 0); 869 870 if (tu->boundary_moderation_en == true) { 871 temp1_fp = drm_fixp_from_fraction( 872 (tu->upper_boundary_count * 873 tu->valid_boundary_link + 874 tu->lower_boundary_count * 875 (tu->valid_boundary_link - 1)), 1); 876 temp2_fp = drm_fixp_from_fraction( 877 (tu->upper_boundary_count + 878 tu->lower_boundary_count), 1); 879 tu->resulting_valid_fp = 880 drm_fixp_div(temp1_fp, temp2_fp); 881 882 temp1_fp = drm_fixp_from_fraction( 883 tu->tu_size_desired, 1); 884 tu->ratio_by_tu_fp = 885 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 886 887 tu->valid_lower_boundary_link = 888 tu->valid_boundary_link - 1; 889 890 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 891 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 892 temp2_fp = drm_fixp_div(temp1_fp, 893 tu->resulting_valid_fp); 894 tu->n_tus = drm_fixp2int(temp2_fp); 895 896 tu->tu_size_minus1 = tu->tu_size_desired - 1; 897 tu->even_distribution_BF = 1; 898 899 temp1_fp = 900 drm_fixp_from_fraction(tu->tu_size_desired, 1); 901 temp2_fp = 902 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 903 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 904 } 905 } 906 907 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 908 909 if (temp2_fp) 910 temp = drm_fixp2int_ceil(temp2_fp); 911 else 912 temp = 0; 913 914 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 915 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 916 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 917 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 918 temp1_fp = drm_fixp_from_fraction(temp, 1); 919 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 920 temp = drm_fixp2int(temp2_fp); 921 922 if (tu->async_en) 923 tu->delay_start_link += (int)temp; 924 925 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 926 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 927 928 /* OUTPUTS */ 929 tu_table->valid_boundary_link = tu->valid_boundary_link; 930 tu_table->delay_start_link = tu->delay_start_link; 931 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 932 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 933 tu_table->upper_boundary_count = tu->upper_boundary_count; 934 tu_table->lower_boundary_count = tu->lower_boundary_count; 935 tu_table->tu_size_minus1 = tu->tu_size_minus1; 936 937 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", 938 tu_table->valid_boundary_link); 939 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", 940 tu_table->delay_start_link); 941 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", 942 tu_table->boundary_moderation_en); 943 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", 944 tu_table->valid_lower_boundary_link); 945 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", 946 tu_table->upper_boundary_count); 947 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", 948 tu_table->lower_boundary_count); 949 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", 950 tu_table->tu_size_minus1); 951 952 kfree(tu); 953 } 954 955 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 956 struct dp_vc_tu_mapping_table *tu_table) 957 { 958 struct dp_tu_calc_input in; 959 struct drm_display_mode *drm_mode; 960 961 drm_mode = &ctrl->panel->dp_mode.drm_mode; 962 963 in.lclk = ctrl->link->link_params.rate / 1000; 964 in.pclk_khz = drm_mode->clock; 965 in.hactive = drm_mode->hdisplay; 966 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 967 in.nlanes = ctrl->link->link_params.num_lanes; 968 in.bpp = ctrl->panel->dp_mode.bpp; 969 in.pixel_enc = 444; 970 in.dsc_en = 0; 971 in.async_en = 0; 972 in.fec_en = 0; 973 in.num_of_dsc_slices = 0; 974 in.compress_ratio = 100; 975 976 _dp_ctrl_calc_tu(ctrl, &in, tu_table); 977 } 978 979 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 980 { 981 u32 dp_tu = 0x0; 982 u32 valid_boundary = 0x0; 983 u32 valid_boundary2 = 0x0; 984 struct dp_vc_tu_mapping_table tu_calc_table; 985 986 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 987 988 dp_tu |= tu_calc_table.tu_size_minus1; 989 valid_boundary |= tu_calc_table.valid_boundary_link; 990 valid_boundary |= (tu_calc_table.delay_start_link << 16); 991 992 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 993 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 994 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 995 996 if (tu_calc_table.boundary_moderation_en) 997 valid_boundary2 |= BIT(0); 998 999 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 1000 dp_tu, valid_boundary, valid_boundary2); 1001 1002 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 1003 dp_tu, valid_boundary, valid_boundary2); 1004 } 1005 1006 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 1007 { 1008 int ret = 0; 1009 1010 if (!wait_for_completion_timeout(&ctrl->video_comp, 1011 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 1012 DRM_ERROR("wait4video timedout\n"); 1013 ret = -ETIMEDOUT; 1014 } 1015 return ret; 1016 } 1017 1018 static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, 1019 u8 v_level, u8 p_level) 1020 { 1021 union phy_configure_opts *phy_opts = &ctrl->phy_opts; 1022 1023 /* TODO: Update for all lanes instead of just first one */ 1024 phy_opts->dp.voltage[0] = v_level; 1025 phy_opts->dp.pre[0] = p_level; 1026 phy_opts->dp.set_voltages = 1; 1027 phy_configure(ctrl->phy, phy_opts); 1028 phy_opts->dp.set_voltages = 0; 1029 1030 return 0; 1031 } 1032 1033 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1034 { 1035 struct dp_link *link = ctrl->link; 1036 int ret = 0, lane, lane_cnt; 1037 u8 buf[4]; 1038 u32 max_level_reached = 0; 1039 u32 voltage_swing_level = link->phy_params.v_level; 1040 u32 pre_emphasis_level = link->phy_params.p_level; 1041 1042 drm_dbg_dp(ctrl->drm_dev, 1043 "voltage level: %d emphasis level: %d\n", 1044 voltage_swing_level, pre_emphasis_level); 1045 ret = dp_ctrl_set_vx_px(ctrl, 1046 voltage_swing_level, pre_emphasis_level); 1047 1048 if (ret) 1049 return ret; 1050 1051 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { 1052 drm_dbg_dp(ctrl->drm_dev, 1053 "max. voltage swing level reached %d\n", 1054 voltage_swing_level); 1055 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1056 } 1057 1058 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { 1059 drm_dbg_dp(ctrl->drm_dev, 1060 "max. pre-emphasis level reached %d\n", 1061 pre_emphasis_level); 1062 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1063 } 1064 1065 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1066 1067 lane_cnt = ctrl->link->link_params.num_lanes; 1068 for (lane = 0; lane < lane_cnt; lane++) 1069 buf[lane] = voltage_swing_level | pre_emphasis_level 1070 | max_level_reached; 1071 1072 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", 1073 voltage_swing_level | pre_emphasis_level); 1074 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, 1075 buf, lane_cnt); 1076 if (ret == lane_cnt) 1077 ret = 0; 1078 1079 return ret; 1080 } 1081 1082 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1083 u8 pattern) 1084 { 1085 u8 buf; 1086 int ret = 0; 1087 1088 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); 1089 1090 buf = pattern; 1091 1092 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1093 buf |= DP_LINK_SCRAMBLING_DISABLE; 1094 1095 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); 1096 return ret == 1; 1097 } 1098 1099 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1100 u8 *link_status) 1101 { 1102 int ret = 0, len; 1103 1104 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1105 if (len != DP_LINK_STATUS_SIZE) { 1106 DRM_ERROR("DP link status read failed, err: %d\n", len); 1107 ret = -EINVAL; 1108 } 1109 1110 return ret; 1111 } 1112 1113 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1114 int *training_step) 1115 { 1116 int tries, old_v_level, ret = 0; 1117 u8 link_status[DP_LINK_STATUS_SIZE]; 1118 int const maximum_retries = 4; 1119 1120 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1121 1122 *training_step = DP_TRAINING_1; 1123 1124 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1125 if (ret) 1126 return ret; 1127 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1128 DP_LINK_SCRAMBLING_DISABLE); 1129 1130 ret = dp_ctrl_update_vx_px(ctrl); 1131 if (ret) 1132 return ret; 1133 1134 tries = 0; 1135 old_v_level = ctrl->link->phy_params.v_level; 1136 for (tries = 0; tries < maximum_retries; tries++) { 1137 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); 1138 1139 ret = dp_ctrl_read_link_status(ctrl, link_status); 1140 if (ret) 1141 return ret; 1142 1143 if (drm_dp_clock_recovery_ok(link_status, 1144 ctrl->link->link_params.num_lanes)) { 1145 return 0; 1146 } 1147 1148 if (ctrl->link->phy_params.v_level >= 1149 DP_TRAIN_VOLTAGE_SWING_MAX) { 1150 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1151 return -EAGAIN; 1152 } 1153 1154 if (old_v_level != ctrl->link->phy_params.v_level) { 1155 tries = 0; 1156 old_v_level = ctrl->link->phy_params.v_level; 1157 } 1158 1159 dp_link_adjust_levels(ctrl->link, link_status); 1160 ret = dp_ctrl_update_vx_px(ctrl); 1161 if (ret) 1162 return ret; 1163 } 1164 1165 DRM_ERROR("max tries reached\n"); 1166 return -ETIMEDOUT; 1167 } 1168 1169 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1170 { 1171 int ret = 0; 1172 1173 switch (ctrl->link->link_params.rate) { 1174 case 810000: 1175 ctrl->link->link_params.rate = 540000; 1176 break; 1177 case 540000: 1178 ctrl->link->link_params.rate = 270000; 1179 break; 1180 case 270000: 1181 ctrl->link->link_params.rate = 162000; 1182 break; 1183 case 162000: 1184 default: 1185 ret = -EINVAL; 1186 break; 1187 } 1188 1189 if (!ret) { 1190 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", 1191 ctrl->link->link_params.rate); 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1198 { 1199 1200 if (ctrl->link->link_params.num_lanes == 1) 1201 return -1; 1202 1203 ctrl->link->link_params.num_lanes /= 2; 1204 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1205 1206 ctrl->link->phy_params.p_level = 0; 1207 ctrl->link->phy_params.v_level = 0; 1208 1209 return 0; 1210 } 1211 1212 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1213 { 1214 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1215 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1216 } 1217 1218 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1219 int *training_step) 1220 { 1221 int tries = 0, ret = 0; 1222 u8 pattern; 1223 u32 state_ctrl_bit; 1224 int const maximum_retries = 5; 1225 u8 link_status[DP_LINK_STATUS_SIZE]; 1226 1227 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1228 1229 *training_step = DP_TRAINING_2; 1230 1231 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { 1232 pattern = DP_TRAINING_PATTERN_4; 1233 state_ctrl_bit = 4; 1234 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { 1235 pattern = DP_TRAINING_PATTERN_3; 1236 state_ctrl_bit = 3; 1237 } else { 1238 pattern = DP_TRAINING_PATTERN_2; 1239 state_ctrl_bit = 2; 1240 } 1241 1242 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1243 if (ret) 1244 return ret; 1245 1246 dp_ctrl_train_pattern_set(ctrl, pattern); 1247 1248 for (tries = 0; tries <= maximum_retries; tries++) { 1249 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1250 1251 ret = dp_ctrl_read_link_status(ctrl, link_status); 1252 if (ret) 1253 return ret; 1254 1255 if (drm_dp_channel_eq_ok(link_status, 1256 ctrl->link->link_params.num_lanes)) { 1257 return 0; 1258 } 1259 1260 dp_link_adjust_levels(ctrl->link, link_status); 1261 ret = dp_ctrl_update_vx_px(ctrl); 1262 if (ret) 1263 return ret; 1264 1265 } 1266 1267 return -ETIMEDOUT; 1268 } 1269 1270 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1271 int *training_step) 1272 { 1273 int ret = 0; 1274 const u8 *dpcd = ctrl->panel->dpcd; 1275 u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; 1276 u8 assr; 1277 struct dp_link_info link_info = {0}; 1278 1279 dp_ctrl_config_ctrl(ctrl); 1280 1281 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1282 link_info.rate = ctrl->link->link_params.rate; 1283 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1284 1285 dp_aux_link_configure(ctrl->aux, &link_info); 1286 1287 if (drm_dp_max_downspread(dpcd)) 1288 encoding[0] |= DP_SPREAD_AMP_0_5; 1289 1290 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ 1291 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); 1292 1293 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { 1294 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 1295 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, 1296 &assr, 1); 1297 } 1298 1299 ret = dp_ctrl_link_train_1(ctrl, training_step); 1300 if (ret) { 1301 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1302 goto end; 1303 } 1304 1305 /* print success info as this is a result of user initiated action */ 1306 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n"); 1307 1308 ret = dp_ctrl_link_train_2(ctrl, training_step); 1309 if (ret) { 1310 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1311 goto end; 1312 } 1313 1314 /* print success info as this is a result of user initiated action */ 1315 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n"); 1316 1317 end: 1318 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1319 1320 return ret; 1321 } 1322 1323 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1324 int *training_step) 1325 { 1326 int ret = 0; 1327 1328 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1329 1330 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1331 return ret; 1332 1333 /* 1334 * As part of previous calls, DP controller state might have 1335 * transitioned to PUSH_IDLE. In order to start transmitting 1336 * a link training pattern, we have to first do soft reset. 1337 */ 1338 1339 ret = dp_ctrl_link_train(ctrl, training_step); 1340 1341 return ret; 1342 } 1343 1344 int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl) 1345 { 1346 struct dp_ctrl_private *ctrl; 1347 int ret = 0; 1348 1349 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1350 1351 if (ctrl->core_clks_on) { 1352 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); 1353 return 0; 1354 } 1355 1356 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); 1357 if (ret) 1358 return ret; 1359 1360 ctrl->core_clks_on = true; 1361 1362 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); 1363 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1364 ctrl->stream_clks_on ? "on" : "off", 1365 ctrl->link_clks_on ? "on" : "off", 1366 ctrl->core_clks_on ? "on" : "off"); 1367 1368 return 0; 1369 } 1370 1371 void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl) 1372 { 1373 struct dp_ctrl_private *ctrl; 1374 1375 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1376 1377 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); 1378 1379 ctrl->core_clks_on = false; 1380 1381 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); 1382 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1383 ctrl->stream_clks_on ? "on" : "off", 1384 ctrl->link_clks_on ? "on" : "off", 1385 ctrl->core_clks_on ? "on" : "off"); 1386 } 1387 1388 static int dp_ctrl_link_clk_enable(struct dp_ctrl *dp_ctrl) 1389 { 1390 struct dp_ctrl_private *ctrl; 1391 int ret = 0; 1392 1393 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1394 1395 if (ctrl->link_clks_on) { 1396 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); 1397 return 0; 1398 } 1399 1400 if (!ctrl->core_clks_on) { 1401 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); 1402 1403 dp_ctrl_core_clk_enable(dp_ctrl); 1404 } 1405 1406 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); 1407 if (ret) 1408 return ret; 1409 1410 ctrl->link_clks_on = true; 1411 1412 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); 1413 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1414 ctrl->stream_clks_on ? "on" : "off", 1415 ctrl->link_clks_on ? "on" : "off", 1416 ctrl->core_clks_on ? "on" : "off"); 1417 1418 return 0; 1419 } 1420 1421 static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl) 1422 { 1423 struct dp_ctrl_private *ctrl; 1424 1425 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1426 1427 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); 1428 1429 ctrl->link_clks_on = false; 1430 1431 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); 1432 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1433 ctrl->stream_clks_on ? "on" : "off", 1434 ctrl->link_clks_on ? "on" : "off", 1435 ctrl->core_clks_on ? "on" : "off"); 1436 } 1437 1438 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1439 { 1440 int ret = 0; 1441 struct phy *phy = ctrl->phy; 1442 const u8 *dpcd = ctrl->panel->dpcd; 1443 1444 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1445 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; 1446 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); 1447 1448 phy_configure(phy, &ctrl->phy_opts); 1449 phy_power_on(phy); 1450 1451 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); 1452 ret = dp_ctrl_link_clk_enable(&ctrl->dp_ctrl); 1453 if (ret) 1454 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1455 1456 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); 1457 1458 return ret; 1459 } 1460 1461 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) 1462 { 1463 struct dp_ctrl_private *ctrl; 1464 1465 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1466 1467 dp_catalog_ctrl_reset(ctrl->catalog); 1468 1469 /* 1470 * all dp controller programmable registers will not 1471 * be reset to default value after DP_SW_RESET 1472 * therefore interrupt mask bits have to be updated 1473 * to enable/disable interrupts 1474 */ 1475 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1476 } 1477 1478 void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl) 1479 { 1480 u8 cfg; 1481 struct dp_ctrl_private *ctrl = container_of(dp_ctrl, 1482 struct dp_ctrl_private, dp_ctrl); 1483 1484 if (!ctrl->panel->psr_cap.version) 1485 return; 1486 1487 dp_catalog_ctrl_config_psr(ctrl->catalog); 1488 1489 cfg = DP_PSR_ENABLE; 1490 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); 1491 } 1492 1493 void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter) 1494 { 1495 struct dp_ctrl_private *ctrl = container_of(dp_ctrl, 1496 struct dp_ctrl_private, dp_ctrl); 1497 1498 if (!ctrl->panel->psr_cap.version) 1499 return; 1500 1501 /* 1502 * When entering PSR, 1503 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT 1504 * 2. Turn off video 1505 * 3. Disable the mainlink 1506 * 1507 * When exiting PSR, 1508 * 1. Enable the mainlink 1509 * 2. Send the PSR exit SDP 1510 */ 1511 if (enter) { 1512 reinit_completion(&ctrl->psr_op_comp); 1513 dp_catalog_ctrl_set_psr(ctrl->catalog, true); 1514 1515 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, 1516 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { 1517 DRM_ERROR("PSR_ENTRY timedout\n"); 1518 dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1519 return; 1520 } 1521 1522 dp_ctrl_push_idle(dp_ctrl); 1523 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1524 1525 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); 1526 } else { 1527 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); 1528 1529 dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1530 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1531 dp_ctrl_wait4video_ready(ctrl); 1532 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1533 } 1534 } 1535 1536 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) 1537 { 1538 struct dp_ctrl_private *ctrl; 1539 struct phy *phy; 1540 1541 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1542 phy = ctrl->phy; 1543 1544 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1545 phy_init(phy); 1546 1547 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1548 phy, phy->init_count, phy->power_count); 1549 } 1550 1551 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) 1552 { 1553 struct dp_ctrl_private *ctrl; 1554 struct phy *phy; 1555 1556 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1557 phy = ctrl->phy; 1558 1559 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1560 phy_exit(phy); 1561 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1562 phy, phy->init_count, phy->power_count); 1563 } 1564 1565 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) 1566 { 1567 const u8 *dpcd = ctrl->panel->dpcd; 1568 1569 /* 1570 * For better interop experience, used a fixed NVID=0x8000 1571 * whenever connected to a VGA dongle downstream. 1572 */ 1573 if (drm_dp_is_branch(dpcd)) 1574 return (drm_dp_has_quirk(&ctrl->panel->desc, 1575 DP_DPCD_QUIRK_CONSTANT_N)); 1576 1577 return false; 1578 } 1579 1580 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1581 { 1582 struct phy *phy = ctrl->phy; 1583 int ret = 0; 1584 1585 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1586 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1587 phy_configure(phy, &ctrl->phy_opts); 1588 /* 1589 * Disable and re-enable the mainlink clock since the 1590 * link clock might have been adjusted as part of the 1591 * link maintenance. 1592 */ 1593 dev_pm_opp_set_rate(ctrl->dev, 0); 1594 1595 dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 1596 1597 phy_power_off(phy); 1598 /* hw recommended delay before re-enabling clocks */ 1599 msleep(20); 1600 1601 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1602 if (ret) { 1603 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1604 return ret; 1605 } 1606 1607 return ret; 1608 } 1609 1610 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1611 { 1612 struct phy *phy; 1613 1614 phy = ctrl->phy; 1615 1616 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1617 1618 dp_catalog_ctrl_reset(ctrl->catalog); 1619 1620 dev_pm_opp_set_rate(ctrl->dev, 0); 1621 dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 1622 1623 phy_power_off(phy); 1624 1625 /* aux channel down, reinit phy */ 1626 phy_exit(phy); 1627 phy_init(phy); 1628 1629 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1630 phy, phy->init_count, phy->power_count); 1631 return 0; 1632 } 1633 1634 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1635 { 1636 int ret = 0; 1637 int training_step = DP_TRAINING_NONE; 1638 1639 dp_ctrl_push_idle(&ctrl->dp_ctrl); 1640 1641 ctrl->link->phy_params.p_level = 0; 1642 ctrl->link->phy_params.v_level = 0; 1643 1644 ret = dp_ctrl_setup_main_link(ctrl, &training_step); 1645 if (ret) 1646 goto end; 1647 1648 dp_ctrl_clear_training_pattern(ctrl); 1649 1650 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1651 1652 ret = dp_ctrl_wait4video_ready(ctrl); 1653 end: 1654 return ret; 1655 } 1656 1657 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1658 { 1659 bool success = false; 1660 u32 pattern_sent = 0x0; 1661 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1662 1663 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); 1664 1665 if (dp_ctrl_set_vx_px(ctrl, 1666 ctrl->link->phy_params.v_level, 1667 ctrl->link->phy_params.p_level)) { 1668 DRM_ERROR("Failed to set v/p levels\n"); 1669 return false; 1670 } 1671 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1672 dp_ctrl_update_vx_px(ctrl); 1673 dp_link_send_test_response(ctrl->link); 1674 1675 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1676 1677 switch (pattern_sent) { 1678 case MR_LINK_TRAINING1: 1679 success = (pattern_requested == 1680 DP_PHY_TEST_PATTERN_D10_2); 1681 break; 1682 case MR_LINK_SYMBOL_ERM: 1683 success = ((pattern_requested == 1684 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1685 (pattern_requested == 1686 DP_PHY_TEST_PATTERN_CP2520)); 1687 break; 1688 case MR_LINK_PRBS7: 1689 success = (pattern_requested == 1690 DP_PHY_TEST_PATTERN_PRBS7); 1691 break; 1692 case MR_LINK_CUSTOM80: 1693 success = (pattern_requested == 1694 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1695 break; 1696 case MR_LINK_TRAINING4: 1697 success = (pattern_requested == 1698 DP_PHY_TEST_PATTERN_SEL_MASK); 1699 break; 1700 default: 1701 success = false; 1702 } 1703 1704 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", 1705 success ? "success" : "failed", pattern_requested); 1706 return success; 1707 } 1708 1709 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1710 { 1711 int ret; 1712 unsigned long pixel_rate; 1713 1714 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1715 drm_dbg_dp(ctrl->drm_dev, 1716 "no test pattern selected by sink\n"); 1717 return 0; 1718 } 1719 1720 /* 1721 * The global reset will need DP link related clocks to be 1722 * running. Add the global reset just before disabling the 1723 * link clocks and core clocks. 1724 */ 1725 dp_ctrl_off(&ctrl->dp_ctrl); 1726 1727 ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1728 if (ret) { 1729 DRM_ERROR("failed to enable DP link controller\n"); 1730 return ret; 1731 } 1732 1733 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1734 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1735 if (ret) { 1736 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1737 return ret; 1738 } 1739 1740 if (ctrl->stream_clks_on) { 1741 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 1742 } else { 1743 ret = clk_prepare_enable(ctrl->pixel_clk); 1744 if (ret) { 1745 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1746 return ret; 1747 } 1748 ctrl->stream_clks_on = true; 1749 } 1750 1751 dp_ctrl_send_phy_test_pattern(ctrl); 1752 1753 return 0; 1754 } 1755 1756 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1757 { 1758 struct dp_ctrl_private *ctrl; 1759 u32 sink_request = 0x0; 1760 1761 if (!dp_ctrl) { 1762 DRM_ERROR("invalid input\n"); 1763 return; 1764 } 1765 1766 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1767 sink_request = ctrl->link->sink_request; 1768 1769 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1770 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); 1771 if (dp_ctrl_process_phy_test_request(ctrl)) { 1772 DRM_ERROR("process phy_test_req failed\n"); 1773 return; 1774 } 1775 } 1776 1777 if (sink_request & DP_LINK_STATUS_UPDATED) { 1778 if (dp_ctrl_link_maintenance(ctrl)) { 1779 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1780 return; 1781 } 1782 } 1783 1784 if (sink_request & DP_TEST_LINK_TRAINING) { 1785 dp_link_send_test_response(ctrl->link); 1786 if (dp_ctrl_link_maintenance(ctrl)) { 1787 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1788 return; 1789 } 1790 } 1791 } 1792 1793 static bool dp_ctrl_clock_recovery_any_ok( 1794 const u8 link_status[DP_LINK_STATUS_SIZE], 1795 int lane_count) 1796 { 1797 int reduced_cnt; 1798 1799 if (lane_count <= 1) 1800 return false; 1801 1802 /* 1803 * only interested in the lane number after reduced 1804 * lane_count = 4, then only interested in 2 lanes 1805 * lane_count = 2, then only interested in 1 lane 1806 */ 1807 reduced_cnt = lane_count >> 1; 1808 1809 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 1810 } 1811 1812 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl) 1813 { 1814 u8 link_status[DP_LINK_STATUS_SIZE]; 1815 int num_lanes = ctrl->link->link_params.num_lanes; 1816 1817 dp_ctrl_read_link_status(ctrl, link_status); 1818 1819 return drm_dp_channel_eq_ok(link_status, num_lanes); 1820 } 1821 1822 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1823 { 1824 int rc = 0; 1825 struct dp_ctrl_private *ctrl; 1826 u32 rate; 1827 int link_train_max_retries = 5; 1828 u32 const phy_cts_pixel_clk_khz = 148500; 1829 u8 link_status[DP_LINK_STATUS_SIZE]; 1830 unsigned int training_step; 1831 unsigned long pixel_rate; 1832 1833 if (!dp_ctrl) 1834 return -EINVAL; 1835 1836 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1837 1838 rate = ctrl->panel->link_info.rate; 1839 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1840 1841 dp_ctrl_core_clk_enable(&ctrl->dp_ctrl); 1842 1843 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1844 drm_dbg_dp(ctrl->drm_dev, 1845 "using phy test link parameters\n"); 1846 if (!pixel_rate) 1847 pixel_rate = phy_cts_pixel_clk_khz; 1848 } else { 1849 ctrl->link->link_params.rate = rate; 1850 ctrl->link->link_params.num_lanes = 1851 ctrl->panel->link_info.num_lanes; 1852 } 1853 1854 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 1855 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, 1856 pixel_rate); 1857 1858 rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1859 if (rc) 1860 return rc; 1861 1862 while (--link_train_max_retries) { 1863 training_step = DP_TRAINING_NONE; 1864 rc = dp_ctrl_setup_main_link(ctrl, &training_step); 1865 if (rc == 0) { 1866 /* training completed successfully */ 1867 break; 1868 } else if (training_step == DP_TRAINING_1) { 1869 /* link train_1 failed */ 1870 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1871 break; 1872 1873 dp_ctrl_read_link_status(ctrl, link_status); 1874 1875 rc = dp_ctrl_link_rate_down_shift(ctrl); 1876 if (rc < 0) { /* already in RBR = 1.6G */ 1877 if (dp_ctrl_clock_recovery_any_ok(link_status, 1878 ctrl->link->link_params.num_lanes)) { 1879 /* 1880 * some lanes are ready, 1881 * reduce lane number 1882 */ 1883 rc = dp_ctrl_link_lane_down_shift(ctrl); 1884 if (rc < 0) { /* lane == 1 already */ 1885 /* end with failure */ 1886 break; 1887 } 1888 } else { 1889 /* end with failure */ 1890 break; /* lane == 1 already */ 1891 } 1892 } 1893 } else if (training_step == DP_TRAINING_2) { 1894 /* link train_2 failed */ 1895 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1896 break; 1897 1898 dp_ctrl_read_link_status(ctrl, link_status); 1899 1900 if (!drm_dp_clock_recovery_ok(link_status, 1901 ctrl->link->link_params.num_lanes)) 1902 rc = dp_ctrl_link_rate_down_shift(ctrl); 1903 else 1904 rc = dp_ctrl_link_lane_down_shift(ctrl); 1905 1906 if (rc < 0) { 1907 /* end with failure */ 1908 break; /* lane == 1 already */ 1909 } 1910 1911 /* stop link training before start re training */ 1912 dp_ctrl_clear_training_pattern(ctrl); 1913 } 1914 1915 rc = dp_ctrl_reinitialize_mainlink(ctrl); 1916 if (rc) { 1917 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); 1918 break; 1919 } 1920 } 1921 1922 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1923 return rc; 1924 1925 if (rc == 0) { /* link train successfully */ 1926 /* 1927 * do not stop train pattern here 1928 * stop link training at on_stream 1929 * to pass compliance test 1930 */ 1931 } else { 1932 /* 1933 * link training failed 1934 * end txing train pattern here 1935 */ 1936 dp_ctrl_clear_training_pattern(ctrl); 1937 1938 dp_ctrl_deinitialize_mainlink(ctrl); 1939 rc = -ECONNRESET; 1940 } 1941 1942 return rc; 1943 } 1944 1945 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) 1946 { 1947 int training_step = DP_TRAINING_NONE; 1948 1949 return dp_ctrl_setup_main_link(ctrl, &training_step); 1950 } 1951 1952 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) 1953 { 1954 int ret = 0; 1955 bool mainlink_ready = false; 1956 struct dp_ctrl_private *ctrl; 1957 unsigned long pixel_rate; 1958 unsigned long pixel_rate_orig; 1959 1960 if (!dp_ctrl) 1961 return -EINVAL; 1962 1963 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1964 1965 pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; 1966 1967 if (dp_ctrl->wide_bus_en) 1968 pixel_rate >>= 1; 1969 1970 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 1971 ctrl->link->link_params.rate, 1972 ctrl->link->link_params.num_lanes, pixel_rate); 1973 1974 drm_dbg_dp(ctrl->drm_dev, 1975 "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", 1976 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); 1977 1978 if (!ctrl->link_clks_on) { /* link clk is off */ 1979 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1980 if (ret) { 1981 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1982 goto end; 1983 } 1984 } 1985 1986 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1987 if (ret) { 1988 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1989 goto end; 1990 } 1991 1992 if (ctrl->stream_clks_on) { 1993 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); 1994 } else { 1995 ret = clk_prepare_enable(ctrl->pixel_clk); 1996 if (ret) { 1997 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1998 goto end; 1999 } 2000 ctrl->stream_clks_on = true; 2001 } 2002 2003 if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) 2004 dp_ctrl_link_retrain(ctrl); 2005 2006 /* stop txing train pattern to end link training */ 2007 dp_ctrl_clear_training_pattern(ctrl); 2008 2009 /* 2010 * Set up transfer unit values and set controller state to send 2011 * video. 2012 */ 2013 reinit_completion(&ctrl->video_comp); 2014 2015 dp_ctrl_configure_source_params(ctrl); 2016 2017 dp_catalog_ctrl_config_msa(ctrl->catalog, 2018 ctrl->link->link_params.rate, 2019 pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl)); 2020 2021 dp_ctrl_setup_tr_unit(ctrl); 2022 2023 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 2024 2025 ret = dp_ctrl_wait4video_ready(ctrl); 2026 if (ret) 2027 return ret; 2028 2029 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 2030 drm_dbg_dp(ctrl->drm_dev, 2031 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 2032 2033 end: 2034 return ret; 2035 } 2036 2037 void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 2038 { 2039 struct dp_ctrl_private *ctrl; 2040 struct phy *phy; 2041 2042 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2043 phy = ctrl->phy; 2044 2045 /* set dongle to D3 (power off) mode */ 2046 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 2047 2048 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2049 2050 if (ctrl->stream_clks_on) { 2051 clk_disable_unprepare(ctrl->pixel_clk); 2052 ctrl->stream_clks_on = false; 2053 } 2054 2055 dev_pm_opp_set_rate(ctrl->dev, 0); 2056 dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2057 2058 phy_power_off(phy); 2059 2060 /* aux channel down, reinit phy */ 2061 phy_exit(phy); 2062 phy_init(phy); 2063 2064 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 2065 phy, phy->init_count, phy->power_count); 2066 } 2067 2068 void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) 2069 { 2070 struct dp_ctrl_private *ctrl; 2071 struct phy *phy; 2072 2073 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2074 phy = ctrl->phy; 2075 2076 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2077 2078 dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2079 2080 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", 2081 phy, phy->init_count, phy->power_count); 2082 2083 phy_power_off(phy); 2084 2085 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", 2086 phy, phy->init_count, phy->power_count); 2087 } 2088 2089 void dp_ctrl_off(struct dp_ctrl *dp_ctrl) 2090 { 2091 struct dp_ctrl_private *ctrl; 2092 struct phy *phy; 2093 2094 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2095 phy = ctrl->phy; 2096 2097 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2098 2099 dp_catalog_ctrl_reset(ctrl->catalog); 2100 2101 if (ctrl->stream_clks_on) { 2102 clk_disable_unprepare(ctrl->pixel_clk); 2103 ctrl->stream_clks_on = false; 2104 } 2105 2106 dev_pm_opp_set_rate(ctrl->dev, 0); 2107 dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2108 2109 phy_power_off(phy); 2110 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 2111 phy, phy->init_count, phy->power_count); 2112 } 2113 2114 irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 2115 { 2116 struct dp_ctrl_private *ctrl; 2117 u32 isr; 2118 irqreturn_t ret = IRQ_NONE; 2119 2120 if (!dp_ctrl) 2121 return IRQ_NONE; 2122 2123 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2124 2125 if (ctrl->panel->psr_cap.version) { 2126 isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); 2127 2128 if (isr) 2129 complete(&ctrl->psr_op_comp); 2130 2131 if (isr & PSR_EXIT_INT) 2132 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); 2133 2134 if (isr & PSR_UPDATE_INT) 2135 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); 2136 2137 if (isr & PSR_CAPTURE_INT) 2138 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); 2139 } 2140 2141 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 2142 2143 2144 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 2145 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); 2146 complete(&ctrl->video_comp); 2147 ret = IRQ_HANDLED; 2148 } 2149 2150 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 2151 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); 2152 complete(&ctrl->idle_comp); 2153 ret = IRQ_HANDLED; 2154 } 2155 2156 return ret; 2157 } 2158 2159 static const char *core_clks[] = { 2160 "core_iface", 2161 "core_aux", 2162 }; 2163 2164 static const char *ctrl_clks[] = { 2165 "ctrl_link", 2166 "ctrl_link_iface", 2167 }; 2168 2169 static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl) 2170 { 2171 struct dp_ctrl_private *ctrl; 2172 struct device *dev; 2173 int i, rc; 2174 2175 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2176 dev = ctrl->dev; 2177 2178 ctrl->num_core_clks = ARRAY_SIZE(core_clks); 2179 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); 2180 if (!ctrl->core_clks) 2181 return -ENOMEM; 2182 2183 for (i = 0; i < ctrl->num_core_clks; i++) 2184 ctrl->core_clks[i].id = core_clks[i]; 2185 2186 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); 2187 if (rc) 2188 return rc; 2189 2190 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); 2191 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); 2192 if (!ctrl->link_clks) 2193 return -ENOMEM; 2194 2195 for (i = 0; i < ctrl->num_link_clks; i++) 2196 ctrl->link_clks[i].id = ctrl_clks[i]; 2197 2198 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); 2199 if (rc) 2200 return rc; 2201 2202 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); 2203 if (IS_ERR(ctrl->pixel_clk)) 2204 return PTR_ERR(ctrl->pixel_clk); 2205 2206 return 0; 2207 } 2208 2209 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 2210 struct dp_panel *panel, struct drm_dp_aux *aux, 2211 struct dp_catalog *catalog, 2212 struct phy *phy) 2213 { 2214 struct dp_ctrl_private *ctrl; 2215 int ret; 2216 2217 if (!dev || !panel || !aux || 2218 !link || !catalog) { 2219 DRM_ERROR("invalid input\n"); 2220 return ERR_PTR(-EINVAL); 2221 } 2222 2223 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 2224 if (!ctrl) { 2225 DRM_ERROR("Mem allocation failure\n"); 2226 return ERR_PTR(-ENOMEM); 2227 } 2228 2229 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 2230 if (ret) { 2231 dev_err(dev, "invalid DP OPP table in device tree\n"); 2232 /* caller do PTR_ERR(opp_table) */ 2233 return (struct dp_ctrl *)ERR_PTR(ret); 2234 } 2235 2236 /* OPP table is optional */ 2237 ret = devm_pm_opp_of_add_table(dev); 2238 if (ret) 2239 dev_err(dev, "failed to add DP OPP table\n"); 2240 2241 init_completion(&ctrl->idle_comp); 2242 init_completion(&ctrl->psr_op_comp); 2243 init_completion(&ctrl->video_comp); 2244 2245 /* in parameters */ 2246 ctrl->panel = panel; 2247 ctrl->aux = aux; 2248 ctrl->link = link; 2249 ctrl->catalog = catalog; 2250 ctrl->dev = dev; 2251 ctrl->phy = phy; 2252 2253 ret = dp_ctrl_clk_init(&ctrl->dp_ctrl); 2254 if (ret) { 2255 dev_err(dev, "failed to init clocks\n"); 2256 return ERR_PTR(ret); 2257 } 2258 2259 return &ctrl->dp_ctrl; 2260 } 2261