1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 15 #include <drm/display/drm_dp_helper.h> 16 #include <drm/drm_fixed.h> 17 #include <drm/drm_print.h> 18 19 #include "dp_reg.h" 20 #include "dp_ctrl.h" 21 #include "dp_link.h" 22 23 #define DP_KHZ_TO_HZ 1000 24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 25 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 26 27 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 28 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 29 30 #define MR_LINK_TRAINING1 0x8 31 #define MR_LINK_SYMBOL_ERM 0x80 32 #define MR_LINK_PRBS7 0x100 33 #define MR_LINK_CUSTOM80 0x200 34 #define MR_LINK_TRAINING4 0x40 35 36 enum { 37 DP_TRAINING_NONE, 38 DP_TRAINING_1, 39 DP_TRAINING_2, 40 }; 41 42 struct dp_tu_calc_input { 43 u64 lclk; /* 162, 270, 540 and 810 */ 44 u64 pclk_khz; /* in KHz */ 45 u64 hactive; /* active h-width */ 46 u64 hporch; /* bp + fp + pulse */ 47 int nlanes; /* no.of.lanes */ 48 int bpp; /* bits */ 49 int pixel_enc; /* 444, 420, 422 */ 50 int dsc_en; /* dsc on/off */ 51 int async_en; /* async mode */ 52 int fec_en; /* fec */ 53 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 54 int num_of_dsc_slices; /* number of slices per line */ 55 }; 56 57 struct dp_vc_tu_mapping_table { 58 u32 vic; 59 u8 lanes; 60 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 61 u8 bpp; 62 u8 valid_boundary_link; 63 u16 delay_start_link; 64 bool boundary_moderation_en; 65 u8 valid_lower_boundary_link; 66 u8 upper_boundary_count; 67 u8 lower_boundary_count; 68 u8 tu_size_minus1; 69 }; 70 71 struct dp_ctrl_private { 72 struct dp_ctrl dp_ctrl; 73 struct device *dev; 74 struct drm_dp_aux *aux; 75 struct dp_panel *panel; 76 struct dp_link *link; 77 struct dp_power *power; 78 struct dp_parser *parser; 79 struct dp_catalog *catalog; 80 81 struct completion idle_comp; 82 struct completion video_comp; 83 }; 84 85 static int dp_aux_link_configure(struct drm_dp_aux *aux, 86 struct dp_link_info *link) 87 { 88 u8 values[2]; 89 int err; 90 91 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 92 values[1] = link->num_lanes; 93 94 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 95 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 96 97 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 98 if (err < 0) 99 return err; 100 101 return 0; 102 } 103 104 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 105 { 106 struct dp_ctrl_private *ctrl; 107 108 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 109 110 reinit_completion(&ctrl->idle_comp); 111 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 112 113 if (!wait_for_completion_timeout(&ctrl->idle_comp, 114 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 115 pr_warn("PUSH_IDLE pattern timedout\n"); 116 117 DRM_DEBUG_DP("mainlink off done\n"); 118 } 119 120 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 121 { 122 u32 config = 0, tbd; 123 const u8 *dpcd = ctrl->panel->dpcd; 124 125 /* Default-> LSCLK DIV: 1/4 LCLK */ 126 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 127 128 /* Scrambler reset enable */ 129 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 130 config |= DP_CONFIGURATION_CTRL_ASSR; 131 132 tbd = dp_link_get_test_bits_depth(ctrl->link, 133 ctrl->panel->dp_mode.bpp); 134 135 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) { 136 pr_debug("BIT_DEPTH not set. Configure default\n"); 137 tbd = DP_TEST_BIT_DEPTH_8; 138 } 139 140 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 141 142 /* Num of Lanes */ 143 config |= ((ctrl->link->link_params.num_lanes - 1) 144 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 145 146 if (drm_dp_enhanced_frame_cap(dpcd)) 147 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 148 149 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 150 151 /* sync clock & static Mvid */ 152 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 153 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 154 155 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 156 } 157 158 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 159 { 160 u32 cc, tb; 161 162 dp_catalog_ctrl_lane_mapping(ctrl->catalog); 163 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 164 165 dp_ctrl_config_ctrl(ctrl); 166 167 tb = dp_link_get_test_bits_depth(ctrl->link, 168 ctrl->panel->dp_mode.bpp); 169 cc = dp_link_get_colorimetry_config(ctrl->link); 170 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 171 dp_panel_timing_cfg(ctrl->panel); 172 } 173 174 /* 175 * The structure and few functions present below are IP/Hardware 176 * specific implementation. Most of the implementation will not 177 * have coding comments 178 */ 179 struct tu_algo_data { 180 s64 lclk_fp; 181 s64 pclk_fp; 182 s64 lwidth; 183 s64 lwidth_fp; 184 s64 hbp_relative_to_pclk; 185 s64 hbp_relative_to_pclk_fp; 186 int nlanes; 187 int bpp; 188 int pixelEnc; 189 int dsc_en; 190 int async_en; 191 int bpc; 192 193 uint delay_start_link_extra_pixclk; 194 int extra_buffer_margin; 195 s64 ratio_fp; 196 s64 original_ratio_fp; 197 198 s64 err_fp; 199 s64 n_err_fp; 200 s64 n_n_err_fp; 201 int tu_size; 202 int tu_size_desired; 203 int tu_size_minus1; 204 205 int valid_boundary_link; 206 s64 resulting_valid_fp; 207 s64 total_valid_fp; 208 s64 effective_valid_fp; 209 s64 effective_valid_recorded_fp; 210 int n_tus; 211 int n_tus_per_lane; 212 int paired_tus; 213 int remainder_tus; 214 int remainder_tus_upper; 215 int remainder_tus_lower; 216 int extra_bytes; 217 int filler_size; 218 int delay_start_link; 219 220 int extra_pclk_cycles; 221 int extra_pclk_cycles_in_link_clk; 222 s64 ratio_by_tu_fp; 223 s64 average_valid2_fp; 224 int new_valid_boundary_link; 225 int remainder_symbols_exist; 226 int n_symbols; 227 s64 n_remainder_symbols_per_lane_fp; 228 s64 last_partial_tu_fp; 229 s64 TU_ratio_err_fp; 230 231 int n_tus_incl_last_incomplete_tu; 232 int extra_pclk_cycles_tmp; 233 int extra_pclk_cycles_in_link_clk_tmp; 234 int extra_required_bytes_new_tmp; 235 int filler_size_tmp; 236 int lower_filler_size_tmp; 237 int delay_start_link_tmp; 238 239 bool boundary_moderation_en; 240 int boundary_mod_lower_err; 241 int upper_boundary_count; 242 int lower_boundary_count; 243 int i_upper_boundary_count; 244 int i_lower_boundary_count; 245 int valid_lower_boundary_link; 246 int even_distribution_BF; 247 int even_distribution_legacy; 248 int even_distribution; 249 int min_hblank_violated; 250 s64 delay_start_time_fp; 251 s64 hbp_time_fp; 252 s64 hactive_time_fp; 253 s64 diff_abs_fp; 254 255 s64 ratio; 256 }; 257 258 static int _tu_param_compare(s64 a, s64 b) 259 { 260 u32 a_sign; 261 u32 b_sign; 262 s64 a_temp, b_temp, minus_1; 263 264 if (a == b) 265 return 0; 266 267 minus_1 = drm_fixp_from_fraction(-1, 1); 268 269 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 270 271 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 272 273 if (a_sign > b_sign) 274 return 2; 275 else if (b_sign > a_sign) 276 return 1; 277 278 if (!a_sign && !b_sign) { /* positive */ 279 if (a > b) 280 return 1; 281 else 282 return 2; 283 } else { /* negative */ 284 a_temp = drm_fixp_mul(a, minus_1); 285 b_temp = drm_fixp_mul(b, minus_1); 286 287 if (a_temp > b_temp) 288 return 2; 289 else 290 return 1; 291 } 292 } 293 294 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 295 struct tu_algo_data *tu) 296 { 297 int nlanes = in->nlanes; 298 int dsc_num_slices = in->num_of_dsc_slices; 299 int dsc_num_bytes = 0; 300 int numerator; 301 s64 pclk_dsc_fp; 302 s64 dwidth_dsc_fp; 303 s64 hbp_dsc_fp; 304 305 int tot_num_eoc_symbols = 0; 306 int tot_num_hor_bytes = 0; 307 int tot_num_dummy_bytes = 0; 308 int dwidth_dsc_bytes = 0; 309 int eoc_bytes = 0; 310 311 s64 temp1_fp, temp2_fp, temp3_fp; 312 313 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 314 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 315 tu->lwidth = in->hactive; 316 tu->hbp_relative_to_pclk = in->hporch; 317 tu->nlanes = in->nlanes; 318 tu->bpp = in->bpp; 319 tu->pixelEnc = in->pixel_enc; 320 tu->dsc_en = in->dsc_en; 321 tu->async_en = in->async_en; 322 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 323 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 324 325 if (tu->pixelEnc == 420) { 326 temp1_fp = drm_fixp_from_fraction(2, 1); 327 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 328 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 329 tu->hbp_relative_to_pclk_fp = 330 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 331 } 332 333 if (tu->pixelEnc == 422) { 334 switch (tu->bpp) { 335 case 24: 336 tu->bpp = 16; 337 tu->bpc = 8; 338 break; 339 case 30: 340 tu->bpp = 20; 341 tu->bpc = 10; 342 break; 343 default: 344 tu->bpp = 16; 345 tu->bpc = 8; 346 break; 347 } 348 } else { 349 tu->bpc = tu->bpp/3; 350 } 351 352 if (!in->dsc_en) 353 goto fec_check; 354 355 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 356 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 357 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 358 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 359 360 temp1_fp = drm_fixp_from_fraction(8, 1); 361 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 362 363 numerator = drm_fixp2int(temp3_fp); 364 365 dsc_num_bytes = numerator / dsc_num_slices; 366 eoc_bytes = dsc_num_bytes % nlanes; 367 tot_num_eoc_symbols = nlanes * dsc_num_slices; 368 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 369 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 370 371 if (dsc_num_bytes == 0) 372 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 373 374 dwidth_dsc_bytes = (tot_num_hor_bytes + 375 tot_num_eoc_symbols + 376 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 377 378 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 379 380 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 381 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 382 pclk_dsc_fp = temp1_fp; 383 384 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 385 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 386 hbp_dsc_fp = temp2_fp; 387 388 /* output */ 389 tu->pclk_fp = pclk_dsc_fp; 390 tu->lwidth_fp = dwidth_dsc_fp; 391 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 392 393 fec_check: 394 if (in->fec_en) { 395 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 396 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 397 } 398 } 399 400 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 401 { 402 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 403 int compare_result_1, compare_result_2, compare_result_3; 404 405 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 406 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 407 408 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 409 410 temp = (tu->i_upper_boundary_count * 411 tu->new_valid_boundary_link + 412 tu->i_lower_boundary_count * 413 (tu->new_valid_boundary_link-1)); 414 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 415 (tu->i_upper_boundary_count + 416 tu->i_lower_boundary_count)); 417 418 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 419 temp2_fp = tu->lwidth_fp; 420 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 421 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 422 tu->n_tus = drm_fixp2int(temp2_fp); 423 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 424 tu->n_tus += 1; 425 426 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 427 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 428 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 429 temp2_fp = temp1_fp - temp2_fp; 430 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 431 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 432 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 433 434 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 435 tu->last_partial_tu_fp = 436 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 437 temp1_fp); 438 439 if (tu->n_remainder_symbols_per_lane_fp != 0) 440 tu->remainder_symbols_exist = 1; 441 else 442 tu->remainder_symbols_exist = 0; 443 444 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 445 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 446 447 tu->paired_tus = (int)((tu->n_tus_per_lane) / 448 (tu->i_upper_boundary_count + 449 tu->i_lower_boundary_count)); 450 451 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 452 (tu->i_upper_boundary_count + 453 tu->i_lower_boundary_count); 454 455 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 456 tu->remainder_tus_upper = tu->i_upper_boundary_count; 457 tu->remainder_tus_lower = tu->remainder_tus - 458 tu->i_upper_boundary_count; 459 } else { 460 tu->remainder_tus_upper = tu->remainder_tus; 461 tu->remainder_tus_lower = 0; 462 } 463 464 temp = tu->paired_tus * (tu->i_upper_boundary_count * 465 tu->new_valid_boundary_link + 466 tu->i_lower_boundary_count * 467 (tu->new_valid_boundary_link - 1)) + 468 (tu->remainder_tus_upper * 469 tu->new_valid_boundary_link) + 470 (tu->remainder_tus_lower * 471 (tu->new_valid_boundary_link - 1)); 472 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 473 474 if (tu->remainder_symbols_exist) { 475 temp1_fp = tu->total_valid_fp + 476 tu->n_remainder_symbols_per_lane_fp; 477 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 478 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 479 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 480 } else { 481 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 482 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 483 } 484 tu->effective_valid_fp = temp1_fp; 485 486 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 487 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 488 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 489 490 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 491 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 492 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 493 494 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 495 496 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 497 temp2_fp = tu->lwidth_fp; 498 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 499 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 500 501 if (temp2_fp) 502 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 503 else 504 tu->n_tus_incl_last_incomplete_tu = 0; 505 506 temp1 = 0; 507 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 508 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 509 temp1_fp = tu->average_valid2_fp - temp2_fp; 510 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 511 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 512 513 if (temp1_fp) 514 temp1 = drm_fixp2int_ceil(temp1_fp); 515 516 temp = tu->i_upper_boundary_count * tu->nlanes; 517 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 518 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 519 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 520 temp2_fp = temp1_fp - temp2_fp; 521 temp1_fp = drm_fixp_from_fraction(temp, 1); 522 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 523 524 if (temp2_fp) 525 temp2 = drm_fixp2int_ceil(temp2_fp); 526 else 527 temp2 = 0; 528 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 529 530 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 531 temp2_fp = drm_fixp_from_fraction( 532 tu->extra_required_bytes_new_tmp, 1); 533 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 534 535 if (temp1_fp) 536 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 537 else 538 tu->extra_pclk_cycles_tmp = 0; 539 540 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 541 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 542 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 543 544 if (temp1_fp) 545 tu->extra_pclk_cycles_in_link_clk_tmp = 546 drm_fixp2int_ceil(temp1_fp); 547 else 548 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 549 550 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 551 552 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 553 554 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 555 tu->lower_filler_size_tmp + 556 tu->extra_buffer_margin; 557 558 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 559 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 560 561 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 562 if (compare_result_1 == 2) 563 compare_result_1 = 1; 564 else 565 compare_result_1 = 0; 566 567 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 568 if (compare_result_2 == 2) 569 compare_result_2 = 1; 570 else 571 compare_result_2 = 0; 572 573 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 574 tu->delay_start_time_fp); 575 if (compare_result_3 == 2) 576 compare_result_3 = 0; 577 else 578 compare_result_3 = 1; 579 580 if (((tu->even_distribution == 1) || 581 ((tu->even_distribution_BF == 0) && 582 (tu->even_distribution_legacy == 0))) && 583 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 584 compare_result_2 && 585 (compare_result_1 || (tu->min_hblank_violated == 1)) && 586 (tu->new_valid_boundary_link - 1) > 0 && 587 compare_result_3 && 588 (tu->delay_start_link_tmp <= 1023)) { 589 tu->upper_boundary_count = tu->i_upper_boundary_count; 590 tu->lower_boundary_count = tu->i_lower_boundary_count; 591 tu->err_fp = tu->n_n_err_fp; 592 tu->boundary_moderation_en = true; 593 tu->tu_size_desired = tu->tu_size; 594 tu->valid_boundary_link = tu->new_valid_boundary_link; 595 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 596 tu->even_distribution_BF = 1; 597 tu->delay_start_link = tu->delay_start_link_tmp; 598 } else if (tu->boundary_mod_lower_err == 0) { 599 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 600 tu->diff_abs_fp); 601 if (compare_result_1 == 2) 602 tu->boundary_mod_lower_err = 1; 603 } 604 } 605 606 static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in, 607 struct dp_vc_tu_mapping_table *tu_table) 608 { 609 struct tu_algo_data *tu; 610 int compare_result_1, compare_result_2; 611 u64 temp = 0; 612 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 613 614 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 615 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 616 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 617 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 618 619 u8 DP_BRUTE_FORCE = 1; 620 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 621 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 622 uint HBLANK_MARGIN = 4; 623 624 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 625 if (!tu) 626 return; 627 628 dp_panel_update_tu_timings(in, tu); 629 630 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 631 632 temp1_fp = drm_fixp_from_fraction(4, 1); 633 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 634 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 635 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 636 637 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 638 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 639 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 640 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 641 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 642 643 tu->original_ratio_fp = tu->ratio_fp; 644 tu->boundary_moderation_en = false; 645 tu->upper_boundary_count = 0; 646 tu->lower_boundary_count = 0; 647 tu->i_upper_boundary_count = 0; 648 tu->i_lower_boundary_count = 0; 649 tu->valid_lower_boundary_link = 0; 650 tu->even_distribution_BF = 0; 651 tu->even_distribution_legacy = 0; 652 tu->even_distribution = 0; 653 tu->delay_start_time_fp = 0; 654 655 tu->err_fp = drm_fixp_from_fraction(1000, 1); 656 tu->n_err_fp = 0; 657 tu->n_n_err_fp = 0; 658 659 tu->ratio = drm_fixp2int(tu->ratio_fp); 660 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 661 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 662 if (temp2_fp != 0 && 663 !tu->ratio && tu->dsc_en == 0) { 664 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 665 tu->ratio = drm_fixp2int(tu->ratio_fp); 666 if (tu->ratio) 667 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 668 } 669 670 if (tu->ratio > 1) 671 tu->ratio = 1; 672 673 if (tu->ratio == 1) 674 goto tu_size_calc; 675 676 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 677 if (!compare_result_1 || compare_result_1 == 1) 678 compare_result_1 = 1; 679 else 680 compare_result_1 = 0; 681 682 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 683 if (!compare_result_2 || compare_result_2 == 2) 684 compare_result_2 = 1; 685 else 686 compare_result_2 = 0; 687 688 if (tu->dsc_en && compare_result_1 && compare_result_2) { 689 HBLANK_MARGIN += 4; 690 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n", 691 HBLANK_MARGIN); 692 } 693 694 tu_size_calc: 695 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 696 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 697 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 698 temp = drm_fixp2int_ceil(temp2_fp); 699 temp1_fp = drm_fixp_from_fraction(temp, 1); 700 tu->n_err_fp = temp1_fp - temp2_fp; 701 702 if (tu->n_err_fp < tu->err_fp) { 703 tu->err_fp = tu->n_err_fp; 704 tu->tu_size_desired = tu->tu_size; 705 } 706 } 707 708 tu->tu_size_minus1 = tu->tu_size_desired - 1; 709 710 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 711 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 712 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 713 714 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 715 temp2_fp = tu->lwidth_fp; 716 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 717 718 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 719 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 720 tu->n_tus = drm_fixp2int(temp2_fp); 721 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 722 tu->n_tus += 1; 723 724 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 725 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n", 726 tu->valid_boundary_link, tu->n_tus); 727 728 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 729 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 730 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 731 temp2_fp = temp1_fp - temp2_fp; 732 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 733 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 734 735 temp = drm_fixp2int(temp2_fp); 736 if (temp && temp2_fp) 737 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 738 else 739 tu->extra_bytes = 0; 740 741 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 742 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 743 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 744 745 if (temp && temp1_fp) 746 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 747 else 748 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 749 750 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 751 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 752 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 753 754 if (temp1_fp) 755 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 756 else 757 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 758 759 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 760 761 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 762 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 763 764 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 765 tu->filler_size + tu->extra_buffer_margin; 766 767 tu->resulting_valid_fp = 768 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 769 770 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 771 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 772 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 773 774 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 775 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 776 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 777 778 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 779 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 780 781 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 782 tu->delay_start_time_fp); 783 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 784 tu->min_hblank_violated = 1; 785 786 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 787 788 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 789 tu->delay_start_time_fp); 790 if (compare_result_2 == 2) 791 tu->min_hblank_violated = 1; 792 793 tu->delay_start_time_fp = 0; 794 795 /* brute force */ 796 797 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 798 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 799 800 temp = drm_fixp2int(tu->diff_abs_fp); 801 if (!temp && tu->diff_abs_fp <= 0xffff) 802 tu->diff_abs_fp = 0; 803 804 /* if(diff_abs < 0) diff_abs *= -1 */ 805 if (tu->diff_abs_fp < 0) 806 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 807 808 tu->boundary_mod_lower_err = 0; 809 if ((tu->diff_abs_fp != 0 && 810 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 811 (tu->even_distribution_legacy == 0) || 812 (DP_BRUTE_FORCE == 1))) || 813 (tu->min_hblank_violated == 1)) { 814 do { 815 tu->err_fp = drm_fixp_from_fraction(1000, 1); 816 817 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 818 temp2_fp = drm_fixp_from_fraction( 819 tu->delay_start_link_extra_pixclk, 1); 820 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 821 822 if (temp1_fp) 823 tu->extra_buffer_margin = 824 drm_fixp2int_ceil(temp1_fp); 825 else 826 tu->extra_buffer_margin = 0; 827 828 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 829 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 830 831 if (temp1_fp) 832 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 833 else 834 tu->n_symbols = 0; 835 836 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 837 for (tu->i_upper_boundary_count = 1; 838 tu->i_upper_boundary_count <= 15; 839 tu->i_upper_boundary_count++) { 840 for (tu->i_lower_boundary_count = 1; 841 tu->i_lower_boundary_count <= 15; 842 tu->i_lower_boundary_count++) { 843 _tu_valid_boundary_calc(tu); 844 } 845 } 846 } 847 tu->delay_start_link_extra_pixclk--; 848 } while (tu->boundary_moderation_en != true && 849 tu->boundary_mod_lower_err == 1 && 850 tu->delay_start_link_extra_pixclk != 0); 851 852 if (tu->boundary_moderation_en == true) { 853 temp1_fp = drm_fixp_from_fraction( 854 (tu->upper_boundary_count * 855 tu->valid_boundary_link + 856 tu->lower_boundary_count * 857 (tu->valid_boundary_link - 1)), 1); 858 temp2_fp = drm_fixp_from_fraction( 859 (tu->upper_boundary_count + 860 tu->lower_boundary_count), 1); 861 tu->resulting_valid_fp = 862 drm_fixp_div(temp1_fp, temp2_fp); 863 864 temp1_fp = drm_fixp_from_fraction( 865 tu->tu_size_desired, 1); 866 tu->ratio_by_tu_fp = 867 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 868 869 tu->valid_lower_boundary_link = 870 tu->valid_boundary_link - 1; 871 872 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 873 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 874 temp2_fp = drm_fixp_div(temp1_fp, 875 tu->resulting_valid_fp); 876 tu->n_tus = drm_fixp2int(temp2_fp); 877 878 tu->tu_size_minus1 = tu->tu_size_desired - 1; 879 tu->even_distribution_BF = 1; 880 881 temp1_fp = 882 drm_fixp_from_fraction(tu->tu_size_desired, 1); 883 temp2_fp = 884 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 885 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 886 } 887 } 888 889 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 890 891 if (temp2_fp) 892 temp = drm_fixp2int_ceil(temp2_fp); 893 else 894 temp = 0; 895 896 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 897 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 898 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 899 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 900 temp1_fp = drm_fixp_from_fraction(temp, 1); 901 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 902 temp = drm_fixp2int(temp2_fp); 903 904 if (tu->async_en) 905 tu->delay_start_link += (int)temp; 906 907 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 908 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 909 910 /* OUTPUTS */ 911 tu_table->valid_boundary_link = tu->valid_boundary_link; 912 tu_table->delay_start_link = tu->delay_start_link; 913 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 914 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 915 tu_table->upper_boundary_count = tu->upper_boundary_count; 916 tu_table->lower_boundary_count = tu->lower_boundary_count; 917 tu_table->tu_size_minus1 = tu->tu_size_minus1; 918 919 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n", 920 tu_table->valid_boundary_link); 921 DRM_DEBUG_DP("TU: delay_start_link: %d\n", 922 tu_table->delay_start_link); 923 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n", 924 tu_table->boundary_moderation_en); 925 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n", 926 tu_table->valid_lower_boundary_link); 927 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n", 928 tu_table->upper_boundary_count); 929 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n", 930 tu_table->lower_boundary_count); 931 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); 932 933 kfree(tu); 934 } 935 936 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 937 struct dp_vc_tu_mapping_table *tu_table) 938 { 939 struct dp_tu_calc_input in; 940 struct drm_display_mode *drm_mode; 941 942 drm_mode = &ctrl->panel->dp_mode.drm_mode; 943 944 in.lclk = ctrl->link->link_params.rate / 1000; 945 in.pclk_khz = drm_mode->clock; 946 in.hactive = drm_mode->hdisplay; 947 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 948 in.nlanes = ctrl->link->link_params.num_lanes; 949 in.bpp = ctrl->panel->dp_mode.bpp; 950 in.pixel_enc = 444; 951 in.dsc_en = 0; 952 in.async_en = 0; 953 in.fec_en = 0; 954 in.num_of_dsc_slices = 0; 955 in.compress_ratio = 100; 956 957 _dp_ctrl_calc_tu(&in, tu_table); 958 } 959 960 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 961 { 962 u32 dp_tu = 0x0; 963 u32 valid_boundary = 0x0; 964 u32 valid_boundary2 = 0x0; 965 struct dp_vc_tu_mapping_table tu_calc_table; 966 967 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 968 969 dp_tu |= tu_calc_table.tu_size_minus1; 970 valid_boundary |= tu_calc_table.valid_boundary_link; 971 valid_boundary |= (tu_calc_table.delay_start_link << 16); 972 973 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 974 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 975 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 976 977 if (tu_calc_table.boundary_moderation_en) 978 valid_boundary2 |= BIT(0); 979 980 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 981 dp_tu, valid_boundary, valid_boundary2); 982 983 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 984 dp_tu, valid_boundary, valid_boundary2); 985 } 986 987 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 988 { 989 int ret = 0; 990 991 if (!wait_for_completion_timeout(&ctrl->video_comp, 992 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 993 DRM_ERROR("wait4video timedout\n"); 994 ret = -ETIMEDOUT; 995 } 996 return ret; 997 } 998 999 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1000 { 1001 struct dp_link *link = ctrl->link; 1002 int ret = 0, lane, lane_cnt; 1003 u8 buf[4]; 1004 u32 max_level_reached = 0; 1005 u32 voltage_swing_level = link->phy_params.v_level; 1006 u32 pre_emphasis_level = link->phy_params.p_level; 1007 1008 DRM_DEBUG_DP("voltage level: %d emphasis level: %d\n", voltage_swing_level, 1009 pre_emphasis_level); 1010 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1011 voltage_swing_level, pre_emphasis_level); 1012 1013 if (ret) 1014 return ret; 1015 1016 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { 1017 DRM_DEBUG_DP("max. voltage swing level reached %d\n", 1018 voltage_swing_level); 1019 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1020 } 1021 1022 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { 1023 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n", 1024 pre_emphasis_level); 1025 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1026 } 1027 1028 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1029 1030 lane_cnt = ctrl->link->link_params.num_lanes; 1031 for (lane = 0; lane < lane_cnt; lane++) 1032 buf[lane] = voltage_swing_level | pre_emphasis_level 1033 | max_level_reached; 1034 1035 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level 1036 | pre_emphasis_level); 1037 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, 1038 buf, lane_cnt); 1039 if (ret == lane_cnt) 1040 ret = 0; 1041 1042 return ret; 1043 } 1044 1045 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1046 u8 pattern) 1047 { 1048 u8 buf; 1049 int ret = 0; 1050 1051 DRM_DEBUG_DP("sink: pattern=%x\n", pattern); 1052 1053 buf = pattern; 1054 1055 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1056 buf |= DP_LINK_SCRAMBLING_DISABLE; 1057 1058 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); 1059 return ret == 1; 1060 } 1061 1062 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1063 u8 *link_status) 1064 { 1065 int ret = 0, len; 1066 1067 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1068 if (len != DP_LINK_STATUS_SIZE) { 1069 DRM_ERROR("DP link status read failed, err: %d\n", len); 1070 ret = -EINVAL; 1071 } 1072 1073 return ret; 1074 } 1075 1076 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1077 int *training_step) 1078 { 1079 int tries, old_v_level, ret = 0; 1080 u8 link_status[DP_LINK_STATUS_SIZE]; 1081 int const maximum_retries = 4; 1082 1083 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1084 1085 *training_step = DP_TRAINING_1; 1086 1087 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1088 if (ret) 1089 return ret; 1090 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1091 DP_LINK_SCRAMBLING_DISABLE); 1092 1093 ret = dp_ctrl_update_vx_px(ctrl); 1094 if (ret) 1095 return ret; 1096 1097 tries = 0; 1098 old_v_level = ctrl->link->phy_params.v_level; 1099 for (tries = 0; tries < maximum_retries; tries++) { 1100 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); 1101 1102 ret = dp_ctrl_read_link_status(ctrl, link_status); 1103 if (ret) 1104 return ret; 1105 1106 if (drm_dp_clock_recovery_ok(link_status, 1107 ctrl->link->link_params.num_lanes)) { 1108 return 0; 1109 } 1110 1111 if (ctrl->link->phy_params.v_level >= 1112 DP_TRAIN_VOLTAGE_SWING_MAX) { 1113 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1114 return -EAGAIN; 1115 } 1116 1117 if (old_v_level != ctrl->link->phy_params.v_level) { 1118 tries = 0; 1119 old_v_level = ctrl->link->phy_params.v_level; 1120 } 1121 1122 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n"); 1123 1124 dp_link_adjust_levels(ctrl->link, link_status); 1125 ret = dp_ctrl_update_vx_px(ctrl); 1126 if (ret) 1127 return ret; 1128 } 1129 1130 DRM_ERROR("max tries reached\n"); 1131 return -ETIMEDOUT; 1132 } 1133 1134 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1135 { 1136 int ret = 0; 1137 1138 switch (ctrl->link->link_params.rate) { 1139 case 810000: 1140 ctrl->link->link_params.rate = 540000; 1141 break; 1142 case 540000: 1143 ctrl->link->link_params.rate = 270000; 1144 break; 1145 case 270000: 1146 ctrl->link->link_params.rate = 162000; 1147 break; 1148 case 162000: 1149 default: 1150 ret = -EINVAL; 1151 break; 1152 } 1153 1154 if (!ret) 1155 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); 1156 1157 return ret; 1158 } 1159 1160 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1161 { 1162 1163 if (ctrl->link->link_params.num_lanes == 1) 1164 return -1; 1165 1166 ctrl->link->link_params.num_lanes /= 2; 1167 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1168 1169 ctrl->link->phy_params.p_level = 0; 1170 ctrl->link->phy_params.v_level = 0; 1171 1172 return 0; 1173 } 1174 1175 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1176 { 1177 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1178 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1179 } 1180 1181 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1182 int *training_step) 1183 { 1184 int tries = 0, ret = 0; 1185 u8 pattern; 1186 u32 state_ctrl_bit; 1187 int const maximum_retries = 5; 1188 u8 link_status[DP_LINK_STATUS_SIZE]; 1189 1190 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1191 1192 *training_step = DP_TRAINING_2; 1193 1194 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { 1195 pattern = DP_TRAINING_PATTERN_4; 1196 state_ctrl_bit = 4; 1197 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { 1198 pattern = DP_TRAINING_PATTERN_3; 1199 state_ctrl_bit = 3; 1200 } else { 1201 pattern = DP_TRAINING_PATTERN_2; 1202 state_ctrl_bit = 2; 1203 } 1204 1205 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1206 if (ret) 1207 return ret; 1208 1209 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); 1210 1211 for (tries = 0; tries <= maximum_retries; tries++) { 1212 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1213 1214 ret = dp_ctrl_read_link_status(ctrl, link_status); 1215 if (ret) 1216 return ret; 1217 1218 if (drm_dp_channel_eq_ok(link_status, 1219 ctrl->link->link_params.num_lanes)) { 1220 return 0; 1221 } 1222 1223 dp_link_adjust_levels(ctrl->link, link_status); 1224 ret = dp_ctrl_update_vx_px(ctrl); 1225 if (ret) 1226 return ret; 1227 1228 } 1229 1230 return -ETIMEDOUT; 1231 } 1232 1233 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl); 1234 1235 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1236 int *training_step) 1237 { 1238 int ret = 0; 1239 const u8 *dpcd = ctrl->panel->dpcd; 1240 u8 encoding = DP_SET_ANSI_8B10B; 1241 u8 ssc; 1242 u8 assr; 1243 struct dp_link_info link_info = {0}; 1244 1245 dp_ctrl_config_ctrl(ctrl); 1246 1247 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1248 link_info.rate = ctrl->link->link_params.rate; 1249 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1250 1251 dp_aux_link_configure(ctrl->aux, &link_info); 1252 1253 if (drm_dp_max_downspread(dpcd)) { 1254 ssc = DP_SPREAD_AMP_0_5; 1255 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1); 1256 } 1257 1258 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 1259 &encoding, 1); 1260 1261 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { 1262 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 1263 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, 1264 &assr, 1); 1265 } 1266 1267 ret = dp_ctrl_link_train_1(ctrl, training_step); 1268 if (ret) { 1269 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1270 goto end; 1271 } 1272 1273 /* print success info as this is a result of user initiated action */ 1274 DRM_DEBUG_DP("link training #1 successful\n"); 1275 1276 ret = dp_ctrl_link_train_2(ctrl, training_step); 1277 if (ret) { 1278 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1279 goto end; 1280 } 1281 1282 /* print success info as this is a result of user initiated action */ 1283 DRM_DEBUG_DP("link training #2 successful\n"); 1284 1285 end: 1286 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1287 1288 return ret; 1289 } 1290 1291 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1292 int *training_step) 1293 { 1294 int ret = 0; 1295 1296 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1297 1298 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1299 return ret; 1300 1301 /* 1302 * As part of previous calls, DP controller state might have 1303 * transitioned to PUSH_IDLE. In order to start transmitting 1304 * a link training pattern, we have to first do soft reset. 1305 */ 1306 1307 ret = dp_ctrl_link_train(ctrl, training_step); 1308 1309 return ret; 1310 } 1311 1312 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, 1313 enum dp_pm_type module, char *name, unsigned long rate) 1314 { 1315 u32 num = ctrl->parser->mp[module].num_clk; 1316 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; 1317 1318 while (num && strcmp(cfg->clk_name, name)) { 1319 num--; 1320 cfg++; 1321 } 1322 1323 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); 1324 1325 if (num) 1326 cfg->rate = rate; 1327 else 1328 DRM_ERROR("%s clock doesn't exit to set rate %lu\n", 1329 name, rate); 1330 } 1331 1332 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1333 { 1334 int ret = 0; 1335 struct dp_io *dp_io = &ctrl->parser->io; 1336 struct phy *phy = dp_io->phy; 1337 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1338 const u8 *dpcd = ctrl->panel->dpcd; 1339 1340 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1341 opts_dp->link_rate = ctrl->link->link_params.rate / 100; 1342 opts_dp->ssc = drm_dp_max_downspread(dpcd); 1343 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", 1344 ctrl->link->link_params.rate * 1000); 1345 1346 phy_configure(phy, &dp_io->phy_opts); 1347 phy_power_on(phy); 1348 1349 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); 1350 if (ret) 1351 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1352 1353 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1354 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1355 1356 return ret; 1357 } 1358 1359 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) 1360 { 1361 int ret = 0; 1362 1363 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", 1364 ctrl->dp_ctrl.pixel_rate * 1000); 1365 1366 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); 1367 if (ret) 1368 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret); 1369 1370 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1371 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1372 1373 return ret; 1374 } 1375 1376 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) 1377 { 1378 struct dp_ctrl_private *ctrl; 1379 1380 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1381 1382 dp_catalog_ctrl_reset(ctrl->catalog); 1383 1384 if (enable) 1385 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1386 } 1387 1388 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) 1389 { 1390 struct dp_ctrl_private *ctrl; 1391 struct dp_io *dp_io; 1392 struct phy *phy; 1393 1394 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1395 dp_io = &ctrl->parser->io; 1396 phy = dp_io->phy; 1397 1398 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1399 phy_init(phy); 1400 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n", 1401 phy, phy->init_count, phy->power_count); 1402 } 1403 1404 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) 1405 { 1406 struct dp_ctrl_private *ctrl; 1407 struct dp_io *dp_io; 1408 struct phy *phy; 1409 1410 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1411 dp_io = &ctrl->parser->io; 1412 phy = dp_io->phy; 1413 1414 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1415 phy_exit(phy); 1416 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n", 1417 phy, phy->init_count, phy->power_count); 1418 } 1419 1420 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) 1421 { 1422 const u8 *dpcd = ctrl->panel->dpcd; 1423 1424 /* 1425 * For better interop experience, used a fixed NVID=0x8000 1426 * whenever connected to a VGA dongle downstream. 1427 */ 1428 if (drm_dp_is_branch(dpcd)) 1429 return (drm_dp_has_quirk(&ctrl->panel->desc, 1430 DP_DPCD_QUIRK_CONSTANT_N)); 1431 1432 return false; 1433 } 1434 1435 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1436 { 1437 int ret = 0; 1438 struct dp_io *dp_io = &ctrl->parser->io; 1439 struct phy *phy = dp_io->phy; 1440 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1441 1442 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1443 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1444 phy_configure(phy, &dp_io->phy_opts); 1445 /* 1446 * Disable and re-enable the mainlink clock since the 1447 * link clock might have been adjusted as part of the 1448 * link maintenance. 1449 */ 1450 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1451 if (ret) { 1452 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); 1453 return ret; 1454 } 1455 phy_power_off(phy); 1456 /* hw recommended delay before re-enabling clocks */ 1457 msleep(20); 1458 1459 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1460 if (ret) { 1461 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1462 return ret; 1463 } 1464 1465 return ret; 1466 } 1467 1468 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1469 { 1470 struct dp_io *dp_io; 1471 struct phy *phy; 1472 int ret; 1473 1474 dp_io = &ctrl->parser->io; 1475 phy = dp_io->phy; 1476 1477 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1478 1479 dp_catalog_ctrl_reset(ctrl->catalog); 1480 1481 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1482 if (ret) { 1483 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1484 } 1485 1486 phy_power_off(phy); 1487 1488 /* aux channel down, reinit phy */ 1489 phy_exit(phy); 1490 phy_init(phy); 1491 1492 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n", 1493 phy, phy->init_count, phy->power_count); 1494 return 0; 1495 } 1496 1497 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1498 { 1499 int ret = 0; 1500 int training_step = DP_TRAINING_NONE; 1501 1502 dp_ctrl_push_idle(&ctrl->dp_ctrl); 1503 1504 ctrl->link->phy_params.p_level = 0; 1505 ctrl->link->phy_params.v_level = 0; 1506 1507 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1508 1509 ret = dp_ctrl_setup_main_link(ctrl, &training_step); 1510 if (ret) 1511 goto end; 1512 1513 dp_ctrl_clear_training_pattern(ctrl); 1514 1515 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1516 1517 ret = dp_ctrl_wait4video_ready(ctrl); 1518 end: 1519 return ret; 1520 } 1521 1522 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1523 { 1524 int ret = 0; 1525 1526 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1527 DRM_DEBUG_DP("no test pattern selected by sink\n"); 1528 return ret; 1529 } 1530 1531 /* 1532 * The global reset will need DP link related clocks to be 1533 * running. Add the global reset just before disabling the 1534 * link clocks and core clocks. 1535 */ 1536 ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl); 1537 if (ret) { 1538 DRM_ERROR("failed to disable DP controller\n"); 1539 return ret; 1540 } 1541 1542 ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1543 if (!ret) 1544 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl); 1545 else 1546 DRM_ERROR("failed to enable DP link controller\n"); 1547 1548 return ret; 1549 } 1550 1551 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1552 { 1553 bool success = false; 1554 u32 pattern_sent = 0x0; 1555 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1556 1557 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested); 1558 1559 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1560 ctrl->link->phy_params.v_level, 1561 ctrl->link->phy_params.p_level)) { 1562 DRM_ERROR("Failed to set v/p levels\n"); 1563 return false; 1564 } 1565 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1566 dp_ctrl_update_vx_px(ctrl); 1567 dp_link_send_test_response(ctrl->link); 1568 1569 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1570 1571 switch (pattern_sent) { 1572 case MR_LINK_TRAINING1: 1573 success = (pattern_requested == 1574 DP_PHY_TEST_PATTERN_D10_2); 1575 break; 1576 case MR_LINK_SYMBOL_ERM: 1577 success = ((pattern_requested == 1578 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1579 (pattern_requested == 1580 DP_PHY_TEST_PATTERN_CP2520)); 1581 break; 1582 case MR_LINK_PRBS7: 1583 success = (pattern_requested == 1584 DP_PHY_TEST_PATTERN_PRBS7); 1585 break; 1586 case MR_LINK_CUSTOM80: 1587 success = (pattern_requested == 1588 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1589 break; 1590 case MR_LINK_TRAINING4: 1591 success = (pattern_requested == 1592 DP_PHY_TEST_PATTERN_SEL_MASK); 1593 break; 1594 default: 1595 success = false; 1596 } 1597 1598 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed", 1599 pattern_requested); 1600 return success; 1601 } 1602 1603 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1604 { 1605 struct dp_ctrl_private *ctrl; 1606 u32 sink_request = 0x0; 1607 1608 if (!dp_ctrl) { 1609 DRM_ERROR("invalid input\n"); 1610 return; 1611 } 1612 1613 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1614 sink_request = ctrl->link->sink_request; 1615 1616 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1617 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n"); 1618 if (dp_ctrl_process_phy_test_request(ctrl)) { 1619 DRM_ERROR("process phy_test_req failed\n"); 1620 return; 1621 } 1622 } 1623 1624 if (sink_request & DP_LINK_STATUS_UPDATED) { 1625 if (dp_ctrl_link_maintenance(ctrl)) { 1626 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1627 return; 1628 } 1629 } 1630 1631 if (sink_request & DP_TEST_LINK_TRAINING) { 1632 dp_link_send_test_response(ctrl->link); 1633 if (dp_ctrl_link_maintenance(ctrl)) { 1634 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1635 return; 1636 } 1637 } 1638 } 1639 1640 static bool dp_ctrl_clock_recovery_any_ok( 1641 const u8 link_status[DP_LINK_STATUS_SIZE], 1642 int lane_count) 1643 { 1644 int reduced_cnt; 1645 1646 if (lane_count <= 1) 1647 return false; 1648 1649 /* 1650 * only interested in the lane number after reduced 1651 * lane_count = 4, then only interested in 2 lanes 1652 * lane_count = 2, then only interested in 1 lane 1653 */ 1654 reduced_cnt = lane_count >> 1; 1655 1656 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 1657 } 1658 1659 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl) 1660 { 1661 u8 link_status[DP_LINK_STATUS_SIZE]; 1662 int num_lanes = ctrl->link->link_params.num_lanes; 1663 1664 dp_ctrl_read_link_status(ctrl, link_status); 1665 1666 return drm_dp_channel_eq_ok(link_status, num_lanes); 1667 } 1668 1669 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1670 { 1671 int rc = 0; 1672 struct dp_ctrl_private *ctrl; 1673 u32 rate = 0; 1674 int link_train_max_retries = 5; 1675 u32 const phy_cts_pixel_clk_khz = 148500; 1676 u8 link_status[DP_LINK_STATUS_SIZE]; 1677 unsigned int training_step; 1678 1679 if (!dp_ctrl) 1680 return -EINVAL; 1681 1682 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1683 1684 rate = ctrl->panel->link_info.rate; 1685 1686 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); 1687 1688 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1689 DRM_DEBUG_DP("using phy test link parameters\n"); 1690 if (!ctrl->panel->dp_mode.drm_mode.clock) 1691 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz; 1692 } else { 1693 ctrl->link->link_params.rate = rate; 1694 ctrl->link->link_params.num_lanes = 1695 ctrl->panel->link_info.num_lanes; 1696 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1697 } 1698 1699 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1700 ctrl->link->link_params.rate, 1701 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1702 1703 ctrl->link->phy_params.p_level = 0; 1704 ctrl->link->phy_params.v_level = 0; 1705 1706 rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1707 if (rc) 1708 return rc; 1709 1710 while (--link_train_max_retries) { 1711 rc = dp_ctrl_reinitialize_mainlink(ctrl); 1712 if (rc) { 1713 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", 1714 rc); 1715 break; 1716 } 1717 1718 training_step = DP_TRAINING_NONE; 1719 rc = dp_ctrl_setup_main_link(ctrl, &training_step); 1720 if (rc == 0) { 1721 /* training completed successfully */ 1722 break; 1723 } else if (training_step == DP_TRAINING_1) { 1724 /* link train_1 failed */ 1725 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1726 break; 1727 1728 dp_ctrl_read_link_status(ctrl, link_status); 1729 1730 rc = dp_ctrl_link_rate_down_shift(ctrl); 1731 if (rc < 0) { /* already in RBR = 1.6G */ 1732 if (dp_ctrl_clock_recovery_any_ok(link_status, 1733 ctrl->link->link_params.num_lanes)) { 1734 /* 1735 * some lanes are ready, 1736 * reduce lane number 1737 */ 1738 rc = dp_ctrl_link_lane_down_shift(ctrl); 1739 if (rc < 0) { /* lane == 1 already */ 1740 /* end with failure */ 1741 break; 1742 } 1743 } else { 1744 /* end with failure */ 1745 break; /* lane == 1 already */ 1746 } 1747 } 1748 } else if (training_step == DP_TRAINING_2) { 1749 /* link train_2 failed */ 1750 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1751 break; 1752 1753 dp_ctrl_read_link_status(ctrl, link_status); 1754 1755 if (!drm_dp_clock_recovery_ok(link_status, 1756 ctrl->link->link_params.num_lanes)) 1757 rc = dp_ctrl_link_rate_down_shift(ctrl); 1758 else 1759 rc = dp_ctrl_link_lane_down_shift(ctrl); 1760 1761 if (rc < 0) { 1762 /* end with failure */ 1763 break; /* lane == 1 already */ 1764 } 1765 1766 /* stop link training before start re training */ 1767 dp_ctrl_clear_training_pattern(ctrl); 1768 } 1769 } 1770 1771 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1772 return rc; 1773 1774 if (rc == 0) { /* link train successfully */ 1775 /* 1776 * do not stop train pattern here 1777 * stop link training at on_stream 1778 * to pass compliance test 1779 */ 1780 } else { 1781 /* 1782 * link training failed 1783 * end txing train pattern here 1784 */ 1785 dp_ctrl_clear_training_pattern(ctrl); 1786 1787 dp_ctrl_deinitialize_mainlink(ctrl); 1788 rc = -ECONNRESET; 1789 } 1790 1791 return rc; 1792 } 1793 1794 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) 1795 { 1796 int training_step = DP_TRAINING_NONE; 1797 1798 return dp_ctrl_setup_main_link(ctrl, &training_step); 1799 } 1800 1801 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 1802 { 1803 int ret = 0; 1804 bool mainlink_ready = false; 1805 struct dp_ctrl_private *ctrl; 1806 1807 if (!dp_ctrl) 1808 return -EINVAL; 1809 1810 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1811 1812 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1813 1814 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1815 ctrl->link->link_params.rate, 1816 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1817 1818 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ 1819 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1820 if (ret) { 1821 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1822 goto end; 1823 } 1824 } 1825 1826 if (!dp_ctrl_channel_eq_ok(ctrl)) 1827 dp_ctrl_link_retrain(ctrl); 1828 1829 /* stop txing train pattern to end link training */ 1830 dp_ctrl_clear_training_pattern(ctrl); 1831 1832 ret = dp_ctrl_enable_stream_clocks(ctrl); 1833 if (ret) { 1834 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1835 goto end; 1836 } 1837 1838 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1839 dp_ctrl_send_phy_test_pattern(ctrl); 1840 return 0; 1841 } 1842 1843 /* 1844 * Set up transfer unit values and set controller state to send 1845 * video. 1846 */ 1847 reinit_completion(&ctrl->video_comp); 1848 1849 dp_ctrl_configure_source_params(ctrl); 1850 1851 dp_catalog_ctrl_config_msa(ctrl->catalog, 1852 ctrl->link->link_params.rate, 1853 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); 1854 1855 dp_ctrl_setup_tr_unit(ctrl); 1856 1857 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1858 1859 ret = dp_ctrl_wait4video_ready(ctrl); 1860 if (ret) 1861 return ret; 1862 1863 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 1864 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 1865 1866 end: 1867 return ret; 1868 } 1869 1870 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 1871 { 1872 struct dp_ctrl_private *ctrl; 1873 struct dp_io *dp_io; 1874 struct phy *phy; 1875 int ret; 1876 1877 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1878 dp_io = &ctrl->parser->io; 1879 phy = dp_io->phy; 1880 1881 /* set dongle to D3 (power off) mode */ 1882 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 1883 1884 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1885 1886 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { 1887 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1888 if (ret) { 1889 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); 1890 return ret; 1891 } 1892 } 1893 1894 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1895 if (ret) { 1896 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1897 return ret; 1898 } 1899 1900 DRM_DEBUG_DP("Before, phy=%x init_count=%d power_on=%d\n", 1901 (u32)(uintptr_t)phy, phy->init_count, phy->power_count); 1902 1903 phy_power_off(phy); 1904 1905 /* aux channel down, reinit phy */ 1906 phy_exit(phy); 1907 phy_init(phy); 1908 1909 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n", 1910 phy, phy->init_count, phy->power_count); 1911 return ret; 1912 } 1913 1914 int dp_ctrl_off(struct dp_ctrl *dp_ctrl) 1915 { 1916 struct dp_ctrl_private *ctrl; 1917 struct dp_io *dp_io; 1918 struct phy *phy; 1919 int ret = 0; 1920 1921 if (!dp_ctrl) 1922 return -EINVAL; 1923 1924 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1925 dp_io = &ctrl->parser->io; 1926 phy = dp_io->phy; 1927 1928 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1929 1930 dp_catalog_ctrl_reset(ctrl->catalog); 1931 1932 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1933 if (ret) 1934 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); 1935 1936 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1937 if (ret) { 1938 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1939 } 1940 1941 phy_power_off(phy); 1942 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n", 1943 phy, phy->init_count, phy->power_count); 1944 1945 return ret; 1946 } 1947 1948 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 1949 { 1950 struct dp_ctrl_private *ctrl; 1951 u32 isr; 1952 1953 if (!dp_ctrl) 1954 return; 1955 1956 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1957 1958 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 1959 1960 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 1961 DRM_DEBUG_DP("dp_video_ready\n"); 1962 complete(&ctrl->video_comp); 1963 } 1964 1965 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 1966 DRM_DEBUG_DP("idle_patterns_sent\n"); 1967 complete(&ctrl->idle_comp); 1968 } 1969 } 1970 1971 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 1972 struct dp_panel *panel, struct drm_dp_aux *aux, 1973 struct dp_power *power, struct dp_catalog *catalog, 1974 struct dp_parser *parser) 1975 { 1976 struct dp_ctrl_private *ctrl; 1977 int ret; 1978 1979 if (!dev || !panel || !aux || 1980 !link || !catalog) { 1981 DRM_ERROR("invalid input\n"); 1982 return ERR_PTR(-EINVAL); 1983 } 1984 1985 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1986 if (!ctrl) { 1987 DRM_ERROR("Mem allocation failure\n"); 1988 return ERR_PTR(-ENOMEM); 1989 } 1990 1991 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 1992 if (ret) { 1993 dev_err(dev, "invalid DP OPP table in device tree\n"); 1994 /* caller do PTR_ERR(opp_table) */ 1995 return (struct dp_ctrl *)ERR_PTR(ret); 1996 } 1997 1998 /* OPP table is optional */ 1999 ret = devm_pm_opp_of_add_table(dev); 2000 if (ret) 2001 dev_err(dev, "failed to add DP OPP table\n"); 2002 2003 init_completion(&ctrl->idle_comp); 2004 init_completion(&ctrl->video_comp); 2005 2006 /* in parameters */ 2007 ctrl->parser = parser; 2008 ctrl->panel = panel; 2009 ctrl->power = power; 2010 ctrl->aux = aux; 2011 ctrl->link = link; 2012 ctrl->catalog = catalog; 2013 ctrl->dev = dev; 2014 2015 return &ctrl->dp_ctrl; 2016 } 2017