1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/phy/phy.h> 14 #include <linux/phy/phy-dp.h> 15 #include <linux/pm_opp.h> 16 #include <linux/rational.h> 17 #include <linux/string_choices.h> 18 19 #include <drm/display/drm_dp_helper.h> 20 #include <drm/drm_device.h> 21 #include <drm/drm_fixed.h> 22 #include <drm/drm_print.h> 23 24 #include "dp_reg.h" 25 #include "dp_ctrl.h" 26 #include "dp_link.h" 27 28 #define POLLING_SLEEP_US 1000 29 #define POLLING_TIMEOUT_US 10000 30 31 #define DP_KHZ_TO_HZ 1000 32 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 33 #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */ 34 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 35 36 #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 37 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 38 39 #define DP_INTERRUPT_STATUS1 \ 40 (DP_INTR_AUX_XFER_DONE| \ 41 DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ 42 DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \ 43 DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \ 44 DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR) 45 46 #define DP_INTERRUPT_STATUS1_ACK \ 47 (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT) 48 #define DP_INTERRUPT_STATUS1_MASK \ 49 (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT) 50 51 #define DP_INTERRUPT_STATUS2 \ 52 (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \ 53 DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED) 54 55 #define DP_INTERRUPT_STATUS2_ACK \ 56 (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT) 57 #define DP_INTERRUPT_STATUS2_MASK \ 58 (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) 59 60 #define DP_INTERRUPT_STATUS4 \ 61 (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \ 62 PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT) 63 64 #define DP_INTERRUPT_MASK4 \ 65 (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ 66 PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) 67 68 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 69 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 70 71 #define MR_LINK_TRAINING1 0x8 72 #define MR_LINK_SYMBOL_ERM 0x80 73 #define MR_LINK_PRBS7 0x100 74 #define MR_LINK_CUSTOM80 0x200 75 #define MR_LINK_TRAINING4 0x40 76 77 enum { 78 DP_TRAINING_NONE, 79 DP_TRAINING_1, 80 DP_TRAINING_2, 81 }; 82 83 struct msm_dp_tu_calc_input { 84 u64 lclk; /* 162, 270, 540 and 810 */ 85 u64 pclk_khz; /* in KHz */ 86 u64 hactive; /* active h-width */ 87 u64 hporch; /* bp + fp + pulse */ 88 int nlanes; /* no.of.lanes */ 89 int bpp; /* bits */ 90 int pixel_enc; /* 444, 420, 422 */ 91 int dsc_en; /* dsc on/off */ 92 int async_en; /* async mode */ 93 int fec_en; /* fec */ 94 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 95 int num_of_dsc_slices; /* number of slices per line */ 96 }; 97 98 struct msm_dp_vc_tu_mapping_table { 99 u32 vic; 100 u8 lanes; 101 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 102 u8 bpp; 103 u8 valid_boundary_link; 104 u16 delay_start_link; 105 bool boundary_moderation_en; 106 u8 valid_lower_boundary_link; 107 u8 upper_boundary_count; 108 u8 lower_boundary_count; 109 u8 tu_size_minus1; 110 }; 111 112 struct msm_dp_ctrl_private { 113 struct msm_dp_ctrl msm_dp_ctrl; 114 struct drm_device *drm_dev; 115 struct device *dev; 116 struct drm_dp_aux *aux; 117 struct msm_dp_link *link; 118 void __iomem *ahb_base; 119 void __iomem *link_base; 120 void __iomem *mst2link_base; 121 void __iomem *mst3link_base; 122 123 struct phy *phy; 124 125 unsigned int num_core_clks; 126 struct clk_bulk_data *core_clks; 127 128 unsigned int num_link_clks; 129 struct clk_bulk_data *link_clks; 130 131 struct clk *pixel_clk[DP_STREAM_MAX]; 132 unsigned int num_pixel_clks; 133 134 union phy_configure_opts phy_opts; 135 136 struct completion idle_comp; 137 struct completion psr_op_comp; 138 struct completion video_comp; 139 140 u32 hw_revision; 141 142 bool core_clks_on; 143 bool link_clks_on; 144 bool stream_clks_on[DP_STREAM_MAX]; 145 }; 146 147 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) 148 { 149 return readl_relaxed(ctrl->ahb_base + offset); 150 } 151 152 static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, 153 u32 offset, u32 data) 154 { 155 /* 156 * To make sure phy reg writes happens before any other operation, 157 * this function uses writel() instread of writel_relaxed() 158 */ 159 writel(data, ctrl->ahb_base + offset); 160 } 161 162 static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) 163 { 164 return readl_relaxed(ctrl->link_base + offset); 165 } 166 167 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, 168 u32 offset, u32 data) 169 { 170 /* 171 * To make sure link reg writes happens before any other operation, 172 * this function uses writel() instread of writel_relaxed() 173 */ 174 writel(data, ctrl->link_base + offset); 175 } 176 177 static inline u32 msm_dp_read_stream_link(struct msm_dp_ctrl_private *ctrl, 178 enum msm_dp_stream_id stream_id, u32 offset) 179 { 180 offset = msm_dp_stream_reg(stream_id, offset); 181 switch (stream_id) { 182 case DP_STREAM_0: 183 case DP_STREAM_1: 184 return readl_relaxed(ctrl->link_base + offset); 185 case DP_STREAM_2: 186 return readl_relaxed(ctrl->mst2link_base + offset); 187 case DP_STREAM_3: 188 return readl_relaxed(ctrl->mst3link_base + offset); 189 default: 190 DRM_ERROR("error stream_id\n"); 191 return 0; 192 } 193 } 194 195 static inline void msm_dp_write_stream_link(struct msm_dp_ctrl_private *ctrl, 196 enum msm_dp_stream_id stream_id, u32 offset, u32 data) 197 { 198 /* 199 * To make sure link reg writes happens before any other operation, 200 * this function uses writel() instread of writel_relaxed() 201 */ 202 offset = msm_dp_stream_reg(stream_id, offset); 203 switch (stream_id) { 204 case DP_STREAM_0: 205 case DP_STREAM_1: 206 writel(data, ctrl->link_base + offset); 207 break; 208 case DP_STREAM_2: 209 writel(data, ctrl->mst2link_base + offset); 210 break; 211 case DP_STREAM_3: 212 writel(data, ctrl->mst3link_base + offset); 213 break; 214 default: 215 DRM_ERROR("error stream_id\n"); 216 break; 217 } 218 } 219 220 static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, 221 struct msm_dp_link_info *link) 222 { 223 u8 lane_count, bw_code; 224 int err; 225 226 lane_count = link->num_lanes; 227 228 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 229 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 230 231 err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count); 232 if (err < 0) 233 return err; 234 235 if (link->use_rate_set) { 236 DRM_DEBUG_DP("using LINK_RATE_SET: 0x%02x", link->rate_set); 237 err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set); 238 } else { 239 bw_code = drm_dp_link_rate_to_bw_code(link->rate); 240 DRM_DEBUG_DP("using LINK_BW_SET: 0x%02x", bw_code); 241 err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code); 242 } 243 244 return err; 245 } 246 247 /* 248 * NOTE: resetting DP controller will also clear any pending HPD related interrupts 249 */ 250 void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl, 251 struct msm_dp_panel *panel) 252 { 253 struct msm_dp_ctrl_private *ctrl = 254 container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 255 u32 sw_reset; 256 257 sw_reset = msm_dp_read_ahb(ctrl, REG_DP_SW_RESET); 258 259 sw_reset |= DP_SW_RESET; 260 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); 261 usleep_range(1000, 1100); /* h/w recommended delay */ 262 263 sw_reset &= ~DP_SW_RESET; 264 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); 265 266 if (!ctrl->hw_revision) 267 ctrl->hw_revision = msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); 268 panel->hw_revision = ctrl->hw_revision; 269 } 270 271 static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) 272 { 273 u32 intr, intr_ack; 274 275 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS); 276 intr &= ~DP_INTERRUPT_STATUS1_MASK; 277 intr_ack = (intr & DP_INTERRUPT_STATUS1) 278 << DP_INTERRUPT_STATUS_ACK_SHIFT; 279 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 280 intr_ack | DP_INTERRUPT_STATUS1_MASK); 281 282 return intr; 283 284 } 285 286 static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) 287 { 288 u32 intr, intr_ack; 289 290 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS2); 291 intr &= ~DP_INTERRUPT_STATUS2_MASK; 292 intr_ack = (intr & DP_INTERRUPT_STATUS2) 293 << DP_INTERRUPT_STATUS_ACK_SHIFT; 294 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 295 intr_ack | DP_INTERRUPT_STATUS2_MASK); 296 297 return intr; 298 } 299 300 void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl) 301 { 302 struct msm_dp_ctrl_private *ctrl = 303 container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 304 305 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 306 DP_INTERRUPT_STATUS1_MASK); 307 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 308 DP_INTERRUPT_STATUS2_MASK); 309 } 310 311 void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) 312 { 313 struct msm_dp_ctrl_private *ctrl = 314 container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 315 316 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); 317 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); 318 } 319 320 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) 321 { 322 u32 intr, intr_ack; 323 324 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS4); 325 intr_ack = (intr & DP_INTERRUPT_STATUS4) 326 << DP_INTERRUPT_STATUS_ACK_SHIFT; 327 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack); 328 329 return intr; 330 } 331 332 static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *ctrl) 333 { 334 msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); 335 } 336 337 static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) 338 { 339 u32 val; 340 341 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 342 val |= DP_MAINLINK_CTRL_ENABLE; 343 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); 344 } 345 346 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) 347 { 348 u32 val; 349 350 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 351 val &= ~DP_MAINLINK_CTRL_ENABLE; 352 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); 353 } 354 355 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) 356 { 357 u32 mainlink_ctrl; 358 359 drm_dbg_dp(ctrl->drm_dev, "enable\n"); 360 361 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 362 363 mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | 364 DP_MAINLINK_CTRL_ENABLE); 365 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 366 367 mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; 368 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 369 370 mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; 371 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 372 373 mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | 374 DP_MAINLINK_FB_BOUNDARY_SEL); 375 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 376 } 377 378 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) 379 { 380 u32 mainlink_ctrl; 381 382 drm_dbg_dp(ctrl->drm_dev, "disable\n"); 383 384 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 385 mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; 386 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 387 } 388 389 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) 390 { 391 u32 mainlink_ctrl; 392 393 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 394 395 if (ctrl->hw_revision >= DP_HW_VERSION_1_2) 396 mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; 397 else 398 mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; 399 400 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 401 } 402 403 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) 404 { 405 u32 data; 406 int ret; 407 408 /* Poll for mainlink ready status */ 409 ret = readl_poll_timeout(ctrl->link_base + REG_DP_MAINLINK_READY, 410 data, data & DP_MAINLINK_READY_FOR_VIDEO, 411 POLLING_SLEEP_US, POLLING_TIMEOUT_US); 412 if (ret < 0) { 413 DRM_ERROR("mainlink not ready\n"); 414 return false; 415 } 416 417 return true; 418 } 419 420 void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) 421 { 422 struct msm_dp_ctrl_private *ctrl; 423 424 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 425 426 reinit_completion(&ctrl->idle_comp); 427 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); 428 429 if (!wait_for_completion_timeout(&ctrl->idle_comp, 430 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 431 pr_warn("PUSH_IDLE pattern timedout\n"); 432 433 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); 434 } 435 436 static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, 437 struct msm_dp_panel *msm_dp_panel) 438 { 439 u32 config = 0, tbd; 440 441 /* 442 * RMW: called from atomic_enable(), serialized by the DRM atomic framework. 443 * Clear stream-specific fields before OR-ing to avoid bit accumulation. 444 */ 445 config = msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, 446 REG_DP_CONFIGURATION_CTRL); 447 config &= ~(DP_CONFIGURATION_CTRL_RGB_YUV_MASK | 448 DP_CONFIGURATION_CTRL_BPC_MASK | 449 DP_CONFIGURATION_CTRL_SEND_VSC); 450 451 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) 452 config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ 453 454 tbd = msm_dp_link_get_test_bits_depth(ctrl->link, 455 msm_dp_panel->msm_dp_mode.bpp); 456 457 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 458 459 if (msm_dp_panel->psr_cap.version) 460 config |= DP_CONFIGURATION_CTRL_SEND_VSC; 461 462 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); 463 464 msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_CONFIGURATION_CTRL, config); 465 } 466 467 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, 468 struct msm_dp_panel *panel) 469 { 470 u32 config = 0; 471 const u8 *dpcd = panel->dpcd; 472 473 /* Default-> LSCLK DIV: 1/4 LCLK */ 474 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 475 476 /* Scrambler reset enable */ 477 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 478 config |= DP_CONFIGURATION_CTRL_ASSR; 479 480 /* Num of Lanes */ 481 config |= ((ctrl->link->link_params.num_lanes - 1) 482 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 483 484 if (drm_dp_enhanced_frame_cap(dpcd)) 485 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 486 487 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 488 489 /* sync clock & static Mvid */ 490 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 491 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 492 493 drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); 494 495 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); 496 } 497 498 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) 499 { 500 u32 *lane_map = ctrl->link->lane_map; 501 u32 ln_mapping; 502 503 ln_mapping = lane_map[0] << LANE0_MAPPING_SHIFT; 504 ln_mapping |= lane_map[1] << LANE1_MAPPING_SHIFT; 505 ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT; 506 ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT; 507 508 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, 509 ln_mapping); 510 } 511 512 static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, 513 struct msm_dp_panel *msm_dp_panel) 514 { 515 u32 colorimetry_cfg, test_bits_depth, misc_val; 516 517 test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, 518 msm_dp_panel->msm_dp_mode.bpp); 519 colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); 520 521 misc_val = msm_dp_read_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0); 522 523 /* clear bpp bits */ 524 misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); 525 misc_val |= colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT; 526 misc_val |= test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT; 527 /* Configure clock to synchronous mode */ 528 misc_val |= DP_MISC0_SYNCHRONOUS_CLK; 529 530 drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); 531 msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, REG_DP_MISC1_MISC0, misc_val); 532 } 533 534 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, 535 struct msm_dp_panel *panel) 536 { 537 msm_dp_ctrl_config_ctrl_streams(ctrl, panel); 538 539 msm_dp_ctrl_config_misc1_misc0(ctrl, panel); 540 541 msm_dp_panel_timing_cfg(panel, ctrl->msm_dp_ctrl.wide_bus_en); 542 } 543 544 /* 545 * The structure and few functions present below are IP/Hardware 546 * specific implementation. Most of the implementation will not 547 * have coding comments 548 */ 549 struct tu_algo_data { 550 s64 lclk_fp; 551 s64 pclk_fp; 552 s64 lwidth; 553 s64 lwidth_fp; 554 s64 hbp_relative_to_pclk; 555 s64 hbp_relative_to_pclk_fp; 556 int nlanes; 557 int bpp; 558 int pixelEnc; 559 int dsc_en; 560 int async_en; 561 int bpc; 562 563 uint delay_start_link_extra_pixclk; 564 int extra_buffer_margin; 565 s64 ratio_fp; 566 s64 original_ratio_fp; 567 568 s64 err_fp; 569 s64 n_err_fp; 570 s64 n_n_err_fp; 571 int tu_size; 572 int tu_size_desired; 573 int tu_size_minus1; 574 575 int valid_boundary_link; 576 s64 resulting_valid_fp; 577 s64 total_valid_fp; 578 s64 effective_valid_fp; 579 s64 effective_valid_recorded_fp; 580 int n_tus; 581 int n_tus_per_lane; 582 int paired_tus; 583 int remainder_tus; 584 int remainder_tus_upper; 585 int remainder_tus_lower; 586 int extra_bytes; 587 int filler_size; 588 int delay_start_link; 589 590 int extra_pclk_cycles; 591 int extra_pclk_cycles_in_link_clk; 592 s64 ratio_by_tu_fp; 593 s64 average_valid2_fp; 594 int new_valid_boundary_link; 595 int remainder_symbols_exist; 596 int n_symbols; 597 s64 n_remainder_symbols_per_lane_fp; 598 s64 last_partial_tu_fp; 599 s64 TU_ratio_err_fp; 600 601 int n_tus_incl_last_incomplete_tu; 602 int extra_pclk_cycles_tmp; 603 int extra_pclk_cycles_in_link_clk_tmp; 604 int extra_required_bytes_new_tmp; 605 int filler_size_tmp; 606 int lower_filler_size_tmp; 607 int delay_start_link_tmp; 608 609 bool boundary_moderation_en; 610 int boundary_mod_lower_err; 611 int upper_boundary_count; 612 int lower_boundary_count; 613 int i_upper_boundary_count; 614 int i_lower_boundary_count; 615 int valid_lower_boundary_link; 616 int even_distribution_BF; 617 int even_distribution_legacy; 618 int even_distribution; 619 int min_hblank_violated; 620 s64 delay_start_time_fp; 621 s64 hbp_time_fp; 622 s64 hactive_time_fp; 623 s64 diff_abs_fp; 624 625 s64 ratio; 626 }; 627 628 static int _tu_param_compare(s64 a, s64 b) 629 { 630 u32 a_sign; 631 u32 b_sign; 632 s64 a_temp, b_temp, minus_1; 633 634 if (a == b) 635 return 0; 636 637 minus_1 = drm_fixp_from_fraction(-1, 1); 638 639 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 640 641 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 642 643 if (a_sign > b_sign) 644 return 2; 645 else if (b_sign > a_sign) 646 return 1; 647 648 if (!a_sign && !b_sign) { /* positive */ 649 if (a > b) 650 return 1; 651 else 652 return 2; 653 } else { /* negative */ 654 a_temp = drm_fixp_mul(a, minus_1); 655 b_temp = drm_fixp_mul(b, minus_1); 656 657 if (a_temp > b_temp) 658 return 2; 659 else 660 return 1; 661 } 662 } 663 664 static void msm_dp_panel_update_tu_timings(struct msm_dp_tu_calc_input *in, 665 struct tu_algo_data *tu) 666 { 667 int nlanes = in->nlanes; 668 int dsc_num_slices = in->num_of_dsc_slices; 669 int dsc_num_bytes = 0; 670 int numerator; 671 s64 pclk_dsc_fp; 672 s64 dwidth_dsc_fp; 673 s64 hbp_dsc_fp; 674 675 int tot_num_eoc_symbols = 0; 676 int tot_num_hor_bytes = 0; 677 int tot_num_dummy_bytes = 0; 678 int dwidth_dsc_bytes = 0; 679 int eoc_bytes = 0; 680 681 s64 temp1_fp, temp2_fp, temp3_fp; 682 683 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 684 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 685 tu->lwidth = in->hactive; 686 tu->hbp_relative_to_pclk = in->hporch; 687 tu->nlanes = in->nlanes; 688 tu->bpp = in->bpp; 689 tu->pixelEnc = in->pixel_enc; 690 tu->dsc_en = in->dsc_en; 691 tu->async_en = in->async_en; 692 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 693 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 694 695 if (tu->pixelEnc == 420) { 696 temp1_fp = drm_fixp_from_fraction(2, 1); 697 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 698 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 699 tu->hbp_relative_to_pclk_fp = 700 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 701 } 702 703 if (tu->pixelEnc == 422) { 704 switch (tu->bpp) { 705 case 24: 706 tu->bpp = 16; 707 tu->bpc = 8; 708 break; 709 case 30: 710 tu->bpp = 20; 711 tu->bpc = 10; 712 break; 713 default: 714 tu->bpp = 16; 715 tu->bpc = 8; 716 break; 717 } 718 } else { 719 tu->bpc = tu->bpp/3; 720 } 721 722 if (!in->dsc_en) 723 goto fec_check; 724 725 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 726 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 727 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 728 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 729 730 temp1_fp = drm_fixp_from_fraction(8, 1); 731 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 732 733 numerator = drm_fixp2int(temp3_fp); 734 735 dsc_num_bytes = numerator / dsc_num_slices; 736 eoc_bytes = dsc_num_bytes % nlanes; 737 tot_num_eoc_symbols = nlanes * dsc_num_slices; 738 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 739 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 740 741 if (dsc_num_bytes == 0) 742 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 743 744 dwidth_dsc_bytes = (tot_num_hor_bytes + 745 tot_num_eoc_symbols + 746 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 747 748 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 749 750 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 751 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 752 pclk_dsc_fp = temp1_fp; 753 754 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 755 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 756 hbp_dsc_fp = temp2_fp; 757 758 /* output */ 759 tu->pclk_fp = pclk_dsc_fp; 760 tu->lwidth_fp = dwidth_dsc_fp; 761 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 762 763 fec_check: 764 if (in->fec_en) { 765 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 766 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 767 } 768 } 769 770 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 771 { 772 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 773 int compare_result_1, compare_result_2, compare_result_3; 774 775 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 776 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 777 778 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 779 780 temp = (tu->i_upper_boundary_count * 781 tu->new_valid_boundary_link + 782 tu->i_lower_boundary_count * 783 (tu->new_valid_boundary_link-1)); 784 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 785 (tu->i_upper_boundary_count + 786 tu->i_lower_boundary_count)); 787 788 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 789 temp2_fp = tu->lwidth_fp; 790 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 791 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 792 tu->n_tus = drm_fixp2int(temp2_fp); 793 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 794 tu->n_tus += 1; 795 796 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 797 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 798 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 799 temp2_fp = temp1_fp - temp2_fp; 800 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 801 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 802 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 803 804 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 805 tu->last_partial_tu_fp = 806 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 807 temp1_fp); 808 809 if (tu->n_remainder_symbols_per_lane_fp != 0) 810 tu->remainder_symbols_exist = 1; 811 else 812 tu->remainder_symbols_exist = 0; 813 814 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 815 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 816 817 tu->paired_tus = (int)((tu->n_tus_per_lane) / 818 (tu->i_upper_boundary_count + 819 tu->i_lower_boundary_count)); 820 821 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 822 (tu->i_upper_boundary_count + 823 tu->i_lower_boundary_count); 824 825 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 826 tu->remainder_tus_upper = tu->i_upper_boundary_count; 827 tu->remainder_tus_lower = tu->remainder_tus - 828 tu->i_upper_boundary_count; 829 } else { 830 tu->remainder_tus_upper = tu->remainder_tus; 831 tu->remainder_tus_lower = 0; 832 } 833 834 temp = tu->paired_tus * (tu->i_upper_boundary_count * 835 tu->new_valid_boundary_link + 836 tu->i_lower_boundary_count * 837 (tu->new_valid_boundary_link - 1)) + 838 (tu->remainder_tus_upper * 839 tu->new_valid_boundary_link) + 840 (tu->remainder_tus_lower * 841 (tu->new_valid_boundary_link - 1)); 842 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 843 844 if (tu->remainder_symbols_exist) { 845 temp1_fp = tu->total_valid_fp + 846 tu->n_remainder_symbols_per_lane_fp; 847 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 848 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 849 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 850 } else { 851 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 852 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 853 } 854 tu->effective_valid_fp = temp1_fp; 855 856 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 857 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 858 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 859 860 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 861 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 862 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 863 864 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 865 866 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 867 temp2_fp = tu->lwidth_fp; 868 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 869 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 870 871 if (temp2_fp) 872 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 873 else 874 tu->n_tus_incl_last_incomplete_tu = 0; 875 876 temp1 = 0; 877 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 878 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 879 temp1_fp = tu->average_valid2_fp - temp2_fp; 880 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 881 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 882 883 if (temp1_fp) 884 temp1 = drm_fixp2int_ceil(temp1_fp); 885 886 temp = tu->i_upper_boundary_count * tu->nlanes; 887 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 888 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 889 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 890 temp2_fp = temp1_fp - temp2_fp; 891 temp1_fp = drm_fixp_from_fraction(temp, 1); 892 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 893 894 if (temp2_fp) 895 temp2 = drm_fixp2int_ceil(temp2_fp); 896 else 897 temp2 = 0; 898 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 899 900 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 901 temp2_fp = drm_fixp_from_fraction( 902 tu->extra_required_bytes_new_tmp, 1); 903 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 904 905 if (temp1_fp) 906 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 907 else 908 tu->extra_pclk_cycles_tmp = 0; 909 910 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 911 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 912 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 913 914 if (temp1_fp) 915 tu->extra_pclk_cycles_in_link_clk_tmp = 916 drm_fixp2int_ceil(temp1_fp); 917 else 918 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 919 920 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 921 922 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 923 924 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 925 tu->lower_filler_size_tmp + 926 tu->extra_buffer_margin; 927 928 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 929 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 930 931 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 932 if (compare_result_1 == 2) 933 compare_result_1 = 1; 934 else 935 compare_result_1 = 0; 936 937 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 938 if (compare_result_2 == 2) 939 compare_result_2 = 1; 940 else 941 compare_result_2 = 0; 942 943 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 944 tu->delay_start_time_fp); 945 if (compare_result_3 == 2) 946 compare_result_3 = 0; 947 else 948 compare_result_3 = 1; 949 950 if (((tu->even_distribution == 1) || 951 ((tu->even_distribution_BF == 0) && 952 (tu->even_distribution_legacy == 0))) && 953 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 954 compare_result_2 && 955 (compare_result_1 || (tu->min_hblank_violated == 1)) && 956 (tu->new_valid_boundary_link - 1) > 0 && 957 compare_result_3 && 958 (tu->delay_start_link_tmp <= 1023)) { 959 tu->upper_boundary_count = tu->i_upper_boundary_count; 960 tu->lower_boundary_count = tu->i_lower_boundary_count; 961 tu->err_fp = tu->n_n_err_fp; 962 tu->boundary_moderation_en = true; 963 tu->tu_size_desired = tu->tu_size; 964 tu->valid_boundary_link = tu->new_valid_boundary_link; 965 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 966 tu->even_distribution_BF = 1; 967 tu->delay_start_link = tu->delay_start_link_tmp; 968 } else if (tu->boundary_mod_lower_err == 0) { 969 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 970 tu->diff_abs_fp); 971 if (compare_result_1 == 2) 972 tu->boundary_mod_lower_err = 1; 973 } 974 } 975 976 static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl, 977 struct msm_dp_tu_calc_input *in, 978 struct msm_dp_vc_tu_mapping_table *tu_table) 979 { 980 struct tu_algo_data *tu; 981 int compare_result_1, compare_result_2; 982 u64 temp = 0; 983 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 984 985 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 986 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 987 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 988 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 989 990 u8 DP_BRUTE_FORCE = 1; 991 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 992 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 993 uint HBLANK_MARGIN = 4; 994 995 tu = kzalloc_obj(*tu); 996 if (!tu) 997 return; 998 999 msm_dp_panel_update_tu_timings(in, tu); 1000 1001 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 1002 1003 temp1_fp = drm_fixp_from_fraction(4, 1); 1004 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 1005 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 1006 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 1007 1008 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 1009 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 1010 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 1011 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 1012 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 1013 1014 tu->original_ratio_fp = tu->ratio_fp; 1015 tu->boundary_moderation_en = false; 1016 tu->upper_boundary_count = 0; 1017 tu->lower_boundary_count = 0; 1018 tu->i_upper_boundary_count = 0; 1019 tu->i_lower_boundary_count = 0; 1020 tu->valid_lower_boundary_link = 0; 1021 tu->even_distribution_BF = 0; 1022 tu->even_distribution_legacy = 0; 1023 tu->even_distribution = 0; 1024 tu->delay_start_time_fp = 0; 1025 1026 tu->err_fp = drm_fixp_from_fraction(1000, 1); 1027 tu->n_err_fp = 0; 1028 tu->n_n_err_fp = 0; 1029 1030 tu->ratio = drm_fixp2int(tu->ratio_fp); 1031 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 1032 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 1033 if (temp2_fp != 0 && 1034 !tu->ratio && tu->dsc_en == 0) { 1035 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 1036 tu->ratio = drm_fixp2int(tu->ratio_fp); 1037 if (tu->ratio) 1038 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 1039 } 1040 1041 if (tu->ratio > 1) 1042 tu->ratio = 1; 1043 1044 if (tu->ratio == 1) 1045 goto tu_size_calc; 1046 1047 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 1048 if (!compare_result_1 || compare_result_1 == 1) 1049 compare_result_1 = 1; 1050 else 1051 compare_result_1 = 0; 1052 1053 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 1054 if (!compare_result_2 || compare_result_2 == 2) 1055 compare_result_2 = 1; 1056 else 1057 compare_result_2 = 0; 1058 1059 if (tu->dsc_en && compare_result_1 && compare_result_2) { 1060 HBLANK_MARGIN += 4; 1061 drm_dbg_dp(ctrl->drm_dev, 1062 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN); 1063 } 1064 1065 tu_size_calc: 1066 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 1067 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 1068 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 1069 temp = drm_fixp2int_ceil(temp2_fp); 1070 temp1_fp = drm_fixp_from_fraction(temp, 1); 1071 tu->n_err_fp = temp1_fp - temp2_fp; 1072 1073 if (tu->n_err_fp < tu->err_fp) { 1074 tu->err_fp = tu->n_err_fp; 1075 tu->tu_size_desired = tu->tu_size; 1076 } 1077 } 1078 1079 tu->tu_size_minus1 = tu->tu_size_desired - 1; 1080 1081 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 1082 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 1083 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 1084 1085 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 1086 temp2_fp = tu->lwidth_fp; 1087 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 1088 1089 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 1090 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 1091 tu->n_tus = drm_fixp2int(temp2_fp); 1092 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 1093 tu->n_tus += 1; 1094 1095 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 1096 1097 drm_dbg_dp(ctrl->drm_dev, 1098 "n_sym = %d, num_of_tus = %d\n", 1099 tu->valid_boundary_link, tu->n_tus); 1100 1101 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 1102 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 1103 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 1104 temp2_fp = temp1_fp - temp2_fp; 1105 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 1106 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 1107 1108 temp = drm_fixp2int(temp2_fp); 1109 if (temp && temp2_fp) 1110 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 1111 else 1112 tu->extra_bytes = 0; 1113 1114 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 1115 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 1116 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 1117 1118 if (temp && temp1_fp) 1119 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 1120 else 1121 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 1122 1123 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 1124 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 1125 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 1126 1127 if (temp1_fp) 1128 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 1129 else 1130 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 1131 1132 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 1133 1134 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 1135 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 1136 1137 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 1138 tu->filler_size + tu->extra_buffer_margin; 1139 1140 tu->resulting_valid_fp = 1141 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 1142 1143 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 1144 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 1145 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 1146 1147 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 1148 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 1149 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 1150 1151 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 1152 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 1153 1154 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 1155 tu->delay_start_time_fp); 1156 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 1157 tu->min_hblank_violated = 1; 1158 1159 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 1160 1161 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 1162 tu->delay_start_time_fp); 1163 if (compare_result_2 == 2) 1164 tu->min_hblank_violated = 1; 1165 1166 tu->delay_start_time_fp = 0; 1167 1168 /* brute force */ 1169 1170 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 1171 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 1172 1173 temp = drm_fixp2int(tu->diff_abs_fp); 1174 if (!temp && tu->diff_abs_fp <= 0xffff) 1175 tu->diff_abs_fp = 0; 1176 1177 /* if(diff_abs < 0) diff_abs *= -1 */ 1178 if (tu->diff_abs_fp < 0) 1179 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 1180 1181 tu->boundary_mod_lower_err = 0; 1182 if ((tu->diff_abs_fp != 0 && 1183 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 1184 (tu->even_distribution_legacy == 0) || 1185 (DP_BRUTE_FORCE == 1))) || 1186 (tu->min_hblank_violated == 1)) { 1187 do { 1188 tu->err_fp = drm_fixp_from_fraction(1000, 1); 1189 1190 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 1191 temp2_fp = drm_fixp_from_fraction( 1192 tu->delay_start_link_extra_pixclk, 1); 1193 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 1194 1195 if (temp1_fp) 1196 tu->extra_buffer_margin = 1197 drm_fixp2int_ceil(temp1_fp); 1198 else 1199 tu->extra_buffer_margin = 0; 1200 1201 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 1202 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 1203 1204 if (temp1_fp) 1205 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 1206 else 1207 tu->n_symbols = 0; 1208 1209 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 1210 for (tu->i_upper_boundary_count = 1; 1211 tu->i_upper_boundary_count <= 15; 1212 tu->i_upper_boundary_count++) { 1213 for (tu->i_lower_boundary_count = 1; 1214 tu->i_lower_boundary_count <= 15; 1215 tu->i_lower_boundary_count++) { 1216 _tu_valid_boundary_calc(tu); 1217 } 1218 } 1219 } 1220 tu->delay_start_link_extra_pixclk--; 1221 } while (tu->boundary_moderation_en != true && 1222 tu->boundary_mod_lower_err == 1 && 1223 tu->delay_start_link_extra_pixclk != 0); 1224 1225 if (tu->boundary_moderation_en == true) { 1226 temp1_fp = drm_fixp_from_fraction( 1227 (tu->upper_boundary_count * 1228 tu->valid_boundary_link + 1229 tu->lower_boundary_count * 1230 (tu->valid_boundary_link - 1)), 1); 1231 temp2_fp = drm_fixp_from_fraction( 1232 (tu->upper_boundary_count + 1233 tu->lower_boundary_count), 1); 1234 tu->resulting_valid_fp = 1235 drm_fixp_div(temp1_fp, temp2_fp); 1236 1237 temp1_fp = drm_fixp_from_fraction( 1238 tu->tu_size_desired, 1); 1239 tu->ratio_by_tu_fp = 1240 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 1241 1242 tu->valid_lower_boundary_link = 1243 tu->valid_boundary_link - 1; 1244 1245 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 1246 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 1247 temp2_fp = drm_fixp_div(temp1_fp, 1248 tu->resulting_valid_fp); 1249 tu->n_tus = drm_fixp2int(temp2_fp); 1250 1251 tu->tu_size_minus1 = tu->tu_size_desired - 1; 1252 tu->even_distribution_BF = 1; 1253 1254 temp1_fp = 1255 drm_fixp_from_fraction(tu->tu_size_desired, 1); 1256 temp2_fp = 1257 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 1258 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 1259 } 1260 } 1261 1262 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 1263 1264 if (temp2_fp) 1265 temp = drm_fixp2int_ceil(temp2_fp); 1266 else 1267 temp = 0; 1268 1269 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 1270 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 1271 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 1272 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 1273 temp1_fp = drm_fixp_from_fraction(temp, 1); 1274 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 1275 temp = drm_fixp2int(temp2_fp); 1276 1277 if (tu->async_en) 1278 tu->delay_start_link += (int)temp; 1279 1280 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 1281 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 1282 1283 /* OUTPUTS */ 1284 tu_table->valid_boundary_link = tu->valid_boundary_link; 1285 tu_table->delay_start_link = tu->delay_start_link; 1286 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 1287 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 1288 tu_table->upper_boundary_count = tu->upper_boundary_count; 1289 tu_table->lower_boundary_count = tu->lower_boundary_count; 1290 tu_table->tu_size_minus1 = tu->tu_size_minus1; 1291 1292 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", 1293 tu_table->valid_boundary_link); 1294 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", 1295 tu_table->delay_start_link); 1296 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", 1297 tu_table->boundary_moderation_en); 1298 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", 1299 tu_table->valid_lower_boundary_link); 1300 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", 1301 tu_table->upper_boundary_count); 1302 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", 1303 tu_table->lower_boundary_count); 1304 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", 1305 tu_table->tu_size_minus1); 1306 1307 kfree(tu); 1308 } 1309 1310 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl, 1311 struct msm_dp_panel *panel, 1312 struct msm_dp_vc_tu_mapping_table *tu_table) 1313 { 1314 struct msm_dp_tu_calc_input in; 1315 const struct drm_display_mode *drm_mode; 1316 1317 drm_mode = &panel->msm_dp_mode.drm_mode; 1318 1319 in.lclk = ctrl->link->link_params.rate / 1000; 1320 in.pclk_khz = drm_mode->clock; 1321 in.hactive = drm_mode->hdisplay; 1322 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 1323 in.nlanes = ctrl->link->link_params.num_lanes; 1324 in.bpp = panel->msm_dp_mode.bpp; 1325 in.pixel_enc = panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; 1326 in.dsc_en = 0; 1327 in.async_en = 0; 1328 in.fec_en = 0; 1329 in.num_of_dsc_slices = 0; 1330 in.compress_ratio = 100; 1331 1332 _dp_ctrl_calc_tu(ctrl, &in, tu_table); 1333 } 1334 1335 static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl, 1336 struct msm_dp_panel *panel) 1337 { 1338 u32 msm_dp_tu = 0x0; 1339 u32 valid_boundary = 0x0; 1340 u32 valid_boundary2 = 0x0; 1341 struct msm_dp_vc_tu_mapping_table tu_calc_table; 1342 1343 msm_dp_ctrl_calc_tu_parameters(ctrl, panel, &tu_calc_table); 1344 1345 msm_dp_tu |= tu_calc_table.tu_size_minus1; 1346 valid_boundary |= tu_calc_table.valid_boundary_link; 1347 valid_boundary |= (tu_calc_table.delay_start_link << 16); 1348 1349 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 1350 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 1351 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 1352 1353 if (tu_calc_table.boundary_moderation_en) 1354 valid_boundary2 |= BIT(0); 1355 1356 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 1357 msm_dp_tu, valid_boundary, valid_boundary2); 1358 1359 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); 1360 msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); 1361 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); 1362 } 1363 1364 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) 1365 { 1366 int ret = 0; 1367 1368 if (!wait_for_completion_timeout(&ctrl->video_comp, 1369 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 1370 DRM_ERROR("wait4video timedout\n"); 1371 ret = -ETIMEDOUT; 1372 } 1373 return ret; 1374 } 1375 1376 static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl, 1377 u8 v_level, u8 p_level) 1378 { 1379 union phy_configure_opts *phy_opts = &ctrl->phy_opts; 1380 1381 /* TODO: Update for all lanes instead of just first one */ 1382 phy_opts->dp.voltage[0] = v_level; 1383 phy_opts->dp.pre[0] = p_level; 1384 phy_opts->dp.set_voltages = 1; 1385 phy_configure(ctrl->phy, phy_opts); 1386 phy_opts->dp.set_voltages = 0; 1387 1388 return 0; 1389 } 1390 1391 static int msm_dp_ctrl_update_phy_vx_px(struct msm_dp_ctrl_private *ctrl, 1392 enum drm_dp_phy dp_phy) 1393 { 1394 struct msm_dp_link *link = ctrl->link; 1395 int lane, lane_cnt, reg; 1396 int ret = 0; 1397 u8 buf[4]; 1398 u32 max_level_reached = 0; 1399 u32 voltage_swing_level = link->phy_params.v_level; 1400 u32 pre_emphasis_level = link->phy_params.p_level; 1401 1402 drm_dbg_dp(ctrl->drm_dev, 1403 "voltage level: %d emphasis level: %d\n", 1404 voltage_swing_level, pre_emphasis_level); 1405 ret = msm_dp_ctrl_set_vx_px(ctrl, 1406 voltage_swing_level, pre_emphasis_level); 1407 1408 if (ret) 1409 return ret; 1410 1411 if (voltage_swing_level >= DP_TRAIN_LEVEL_MAX) { 1412 drm_dbg_dp(ctrl->drm_dev, 1413 "max. voltage swing level reached %d\n", 1414 voltage_swing_level); 1415 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1416 } 1417 1418 if (pre_emphasis_level >= DP_TRAIN_LEVEL_MAX) { 1419 drm_dbg_dp(ctrl->drm_dev, 1420 "max. pre-emphasis level reached %d\n", 1421 pre_emphasis_level); 1422 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1423 } 1424 1425 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1426 1427 lane_cnt = ctrl->link->link_params.num_lanes; 1428 for (lane = 0; lane < lane_cnt; lane++) 1429 buf[lane] = voltage_swing_level | pre_emphasis_level 1430 | max_level_reached; 1431 1432 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", 1433 voltage_swing_level | pre_emphasis_level); 1434 1435 if (dp_phy == DP_PHY_DPRX) 1436 reg = DP_TRAINING_LANE0_SET; 1437 else 1438 reg = DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 1439 1440 ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt); 1441 if (ret == lane_cnt) 1442 ret = 0; 1443 1444 return ret; 1445 } 1446 1447 static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl, 1448 u8 pattern, enum drm_dp_phy dp_phy) 1449 { 1450 u8 buf; 1451 int reg; 1452 int ret = 0; 1453 1454 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); 1455 1456 buf = pattern; 1457 1458 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1459 buf |= DP_LINK_SCRAMBLING_DISABLE; 1460 1461 if (dp_phy == DP_PHY_DPRX) 1462 reg = DP_TRAINING_PATTERN_SET; 1463 else 1464 reg = DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 1465 1466 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf); 1467 return ret == 1; 1468 } 1469 1470 static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, 1471 u32 state_bit) 1472 { 1473 int bit, ret; 1474 u32 data; 1475 1476 bit = BIT(state_bit - 1); 1477 drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); 1478 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); 1479 1480 bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; 1481 1482 /* Poll for mainlink ready status */ 1483 ret = readx_poll_timeout(readl, ctrl->link_base + REG_DP_MAINLINK_READY, 1484 data, data & bit, 1485 POLLING_SLEEP_US, POLLING_TIMEOUT_US); 1486 if (ret < 0) { 1487 DRM_ERROR("set state_bit for link_train=%d failed\n", state_bit); 1488 return ret; 1489 } 1490 1491 return 0; 1492 } 1493 1494 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, 1495 struct msm_dp_panel *panel, 1496 int *training_step, enum drm_dp_phy dp_phy) 1497 { 1498 int delay_us; 1499 int tries, old_v_level, ret = 0; 1500 u8 link_status[DP_LINK_STATUS_SIZE]; 1501 int const maximum_retries = 4; 1502 1503 delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, 1504 panel->dpcd, dp_phy, false); 1505 1506 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); 1507 1508 *training_step = DP_TRAINING_1; 1509 1510 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, 1); 1511 if (ret) 1512 return ret; 1513 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1514 DP_LINK_SCRAMBLING_DISABLE, dp_phy); 1515 1516 msm_dp_link_reset_phy_params_vx_px(ctrl->link); 1517 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1518 if (ret) 1519 return ret; 1520 1521 tries = 0; 1522 old_v_level = ctrl->link->phy_params.v_level; 1523 for (tries = 0; tries < maximum_retries; tries++) { 1524 fsleep(delay_us); 1525 1526 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); 1527 if (ret) 1528 return ret; 1529 1530 if (drm_dp_clock_recovery_ok(link_status, 1531 ctrl->link->link_params.num_lanes)) { 1532 return 0; 1533 } 1534 1535 if (ctrl->link->phy_params.v_level >= 1536 DP_TRAIN_LEVEL_MAX) { 1537 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1538 return -EAGAIN; 1539 } 1540 1541 if (old_v_level != ctrl->link->phy_params.v_level) { 1542 tries = 0; 1543 old_v_level = ctrl->link->phy_params.v_level; 1544 } 1545 1546 msm_dp_link_adjust_levels(ctrl->link, link_status); 1547 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1548 if (ret) 1549 return ret; 1550 } 1551 1552 DRM_ERROR("max tries reached\n"); 1553 return -ETIMEDOUT; 1554 } 1555 1556 static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl) 1557 { 1558 int ret = 0; 1559 struct msm_dp_link_info *link_params = &ctrl->link->link_params; 1560 1561 if (link_params->rate_set) { 1562 --link_params->rate_set; 1563 link_params->rate = link_params->supported_rates[link_params->rate_set]; 1564 } else { 1565 switch (link_params->rate) { 1566 case 810000: 1567 link_params->rate = 540000; 1568 break; 1569 case 540000: 1570 link_params->rate = 270000; 1571 break; 1572 case 270000: 1573 link_params->rate = 162000; 1574 break; 1575 case 162000: 1576 default: 1577 ret = -EINVAL; 1578 break; 1579 } 1580 } 1581 1582 if (!ret) { 1583 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", 1584 link_params->rate); 1585 } 1586 1587 return ret; 1588 } 1589 1590 static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl, 1591 struct msm_dp_panel *panel) 1592 { 1593 1594 if (ctrl->link->link_params.num_lanes == 1) 1595 return -1; 1596 1597 ctrl->link->link_params.num_lanes /= 2; 1598 ctrl->link->link_params.rate = panel->link_info.rate; 1599 1600 ctrl->link->phy_params.p_level = 0; 1601 ctrl->link->phy_params.v_level = 0; 1602 1603 return 0; 1604 } 1605 1606 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl, 1607 struct msm_dp_panel *panel, 1608 enum drm_dp_phy dp_phy) 1609 { 1610 int delay_us; 1611 1612 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); 1613 1614 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, 1615 panel->dpcd, dp_phy, false); 1616 fsleep(delay_us); 1617 } 1618 1619 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, 1620 struct msm_dp_panel *panel, 1621 int *training_step, enum drm_dp_phy dp_phy) 1622 { 1623 int delay_us; 1624 int tries = 0, ret = 0; 1625 u8 pattern; 1626 u32 state_ctrl_bit; 1627 int const maximum_retries = 5; 1628 u8 link_status[DP_LINK_STATUS_SIZE]; 1629 1630 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, 1631 panel->dpcd, dp_phy, false); 1632 1633 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); 1634 1635 *training_step = DP_TRAINING_2; 1636 1637 if (drm_dp_tps4_supported(panel->dpcd)) { 1638 pattern = DP_TRAINING_PATTERN_4; 1639 state_ctrl_bit = 4; 1640 } else if (drm_dp_tps3_supported(panel->dpcd)) { 1641 pattern = DP_TRAINING_PATTERN_3; 1642 state_ctrl_bit = 3; 1643 } else { 1644 pattern = DP_TRAINING_PATTERN_2; 1645 state_ctrl_bit = 2; 1646 } 1647 1648 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit); 1649 if (ret) 1650 return ret; 1651 1652 msm_dp_ctrl_train_pattern_set(ctrl, pattern, dp_phy); 1653 1654 for (tries = 0; tries <= maximum_retries; tries++) { 1655 fsleep(delay_us); 1656 1657 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); 1658 if (ret) 1659 return ret; 1660 1661 if (drm_dp_channel_eq_ok(link_status, 1662 ctrl->link->link_params.num_lanes)) { 1663 return 0; 1664 } 1665 1666 msm_dp_link_adjust_levels(ctrl->link, link_status); 1667 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); 1668 if (ret) 1669 return ret; 1670 1671 } 1672 1673 return -ETIMEDOUT; 1674 } 1675 1676 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, 1677 struct msm_dp_panel *panel, 1678 int *training_step, enum drm_dp_phy dp_phy) 1679 { 1680 int ret; 1681 1682 ret = msm_dp_ctrl_link_train_1(ctrl, panel, training_step, dp_phy); 1683 if (ret) { 1684 DRM_ERROR("link training #1 on phy %d failed. ret=%d\n", dp_phy, ret); 1685 return ret; 1686 } 1687 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy); 1688 1689 ret = msm_dp_ctrl_link_train_2(ctrl, panel, training_step, dp_phy); 1690 if (ret) { 1691 DRM_ERROR("link training #2 on phy %d failed. ret=%d\n", dp_phy, ret); 1692 return ret; 1693 } 1694 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy); 1695 1696 return 0; 1697 } 1698 1699 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, 1700 struct msm_dp_panel *panel, 1701 int *training_step) 1702 { 1703 int i; 1704 int ret = 0; 1705 const u8 *dpcd = panel->dpcd; 1706 u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; 1707 u8 assr; 1708 struct msm_dp_link_info link_info = {0}; 1709 1710 msm_dp_ctrl_config_ctrl_link(ctrl, panel); 1711 msm_dp_ctrl_config_ctrl_streams(ctrl, panel); 1712 1713 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1714 link_info.rate = ctrl->link->link_params.rate; 1715 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1716 1717 msm_dp_aux_link_configure(ctrl->aux, &link_info); 1718 1719 if (drm_dp_max_downspread(dpcd)) 1720 encoding[0] |= DP_SPREAD_AMP_0_5; 1721 1722 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ 1723 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); 1724 1725 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { 1726 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 1727 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, 1728 &assr, 1); 1729 } 1730 1731 for (i = ctrl->link->lttpr_count - 1; i >= 0; i--) { 1732 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1733 1734 ret = msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, dp_phy); 1735 msm_dp_ctrl_clear_training_pattern(ctrl, panel, dp_phy); 1736 1737 if (ret) 1738 break; 1739 } 1740 1741 if (ret) { 1742 DRM_ERROR("link training of LTTPR(s) failed. ret=%d\n", ret); 1743 goto end; 1744 } 1745 1746 ret = msm_dp_ctrl_link_train_1_2(ctrl, panel, training_step, DP_PHY_DPRX); 1747 if (ret) { 1748 DRM_ERROR("link training on sink failed. ret=%d\n", ret); 1749 goto end; 1750 } 1751 1752 end: 1753 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); 1754 1755 return ret; 1756 } 1757 1758 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, 1759 struct msm_dp_panel *panel, 1760 int *training_step) 1761 { 1762 int ret = 0; 1763 1764 msm_dp_ctrl_mainlink_enable(ctrl); 1765 1766 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1767 return ret; 1768 1769 /* 1770 * As part of previous calls, DP controller state might have 1771 * transitioned to PUSH_IDLE. In order to start transmitting 1772 * a link training pattern, we have to first do soft reset. 1773 */ 1774 1775 ret = msm_dp_ctrl_link_train(ctrl, panel, training_step); 1776 1777 return ret; 1778 } 1779 1780 int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1781 { 1782 struct msm_dp_ctrl_private *ctrl; 1783 int ret = 0; 1784 1785 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1786 1787 if (ctrl->core_clks_on) { 1788 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); 1789 return 0; 1790 } 1791 1792 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); 1793 if (ret) 1794 return ret; 1795 1796 ctrl->core_clks_on = true; 1797 1798 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); 1799 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1800 str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), 1801 str_on_off(ctrl->link_clks_on), 1802 str_on_off(ctrl->core_clks_on)); 1803 1804 return 0; 1805 } 1806 1807 void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1808 { 1809 struct msm_dp_ctrl_private *ctrl; 1810 1811 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1812 1813 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); 1814 1815 ctrl->core_clks_on = false; 1816 1817 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); 1818 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1819 str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), 1820 str_on_off(ctrl->link_clks_on), 1821 str_on_off(ctrl->core_clks_on)); 1822 } 1823 1824 static int msm_dp_ctrl_link_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1825 { 1826 struct msm_dp_ctrl_private *ctrl; 1827 int ret = 0; 1828 1829 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1830 1831 if (ctrl->link_clks_on) { 1832 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); 1833 return 0; 1834 } 1835 1836 if (!ctrl->core_clks_on) { 1837 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); 1838 1839 msm_dp_ctrl_core_clk_enable(msm_dp_ctrl); 1840 } 1841 1842 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); 1843 if (ret) 1844 return ret; 1845 1846 ctrl->link_clks_on = true; 1847 1848 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); 1849 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1850 str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), 1851 str_on_off(ctrl->link_clks_on), 1852 str_on_off(ctrl->core_clks_on)); 1853 1854 return 0; 1855 } 1856 1857 static void msm_dp_ctrl_link_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1858 { 1859 struct msm_dp_ctrl_private *ctrl; 1860 1861 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1862 1863 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); 1864 1865 ctrl->link_clks_on = false; 1866 1867 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); 1868 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", 1869 str_on_off(ctrl->stream_clks_on[DP_STREAM_0]), 1870 str_on_off(ctrl->link_clks_on), 1871 str_on_off(ctrl->core_clks_on)); 1872 } 1873 1874 static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl, 1875 struct msm_dp_panel *panel) 1876 { 1877 int ret = 0; 1878 struct phy *phy = ctrl->phy; 1879 const u8 *dpcd = panel->dpcd; 1880 1881 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1882 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; 1883 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); 1884 1885 phy_configure(phy, &ctrl->phy_opts); 1886 phy_power_on(phy); 1887 1888 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); 1889 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); 1890 if (ret) 1891 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1892 1893 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); 1894 1895 return ret; 1896 } 1897 1898 static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) 1899 { 1900 /* trigger sdp */ 1901 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); 1902 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); 1903 } 1904 1905 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) 1906 { 1907 u32 cmd; 1908 1909 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); 1910 1911 cmd &= ~(PSR_ENTER | PSR_EXIT); 1912 cmd |= PSR_ENTER; 1913 1914 msm_dp_ctrl_enable_sdp(ctrl); 1915 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); 1916 } 1917 1918 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) 1919 { 1920 u32 cmd; 1921 1922 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); 1923 1924 cmd &= ~(PSR_ENTER | PSR_EXIT); 1925 cmd |= PSR_EXIT; 1926 1927 msm_dp_ctrl_enable_sdp(ctrl); 1928 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); 1929 } 1930 1931 void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl, 1932 struct msm_dp_panel *panel) 1933 { 1934 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1935 struct msm_dp_ctrl_private, msm_dp_ctrl); 1936 u32 cfg; 1937 1938 if (!panel->psr_cap.version) 1939 return; 1940 1941 /* enable PSR1 function */ 1942 cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); 1943 cfg |= PSR1_SUPPORTED; 1944 msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); 1945 1946 msm_dp_ctrl_config_psr_interrupt(ctrl); 1947 msm_dp_ctrl_enable_sdp(ctrl); 1948 1949 cfg = DP_PSR_ENABLE; 1950 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); 1951 } 1952 1953 void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, 1954 struct msm_dp_panel *panel, bool enter) 1955 { 1956 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1957 struct msm_dp_ctrl_private, msm_dp_ctrl); 1958 1959 if (!panel->psr_cap.version) 1960 return; 1961 1962 /* 1963 * When entering PSR, 1964 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT 1965 * 2. Turn off video 1966 * 3. Disable the mainlink 1967 * 1968 * When exiting PSR, 1969 * 1. Enable the mainlink 1970 * 2. Send the PSR exit SDP 1971 */ 1972 if (enter) { 1973 reinit_completion(&ctrl->psr_op_comp); 1974 msm_dp_ctrl_psr_enter(ctrl); 1975 1976 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, 1977 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { 1978 DRM_ERROR("PSR_ENTRY timedout\n"); 1979 msm_dp_ctrl_psr_exit(ctrl); 1980 return; 1981 } 1982 1983 msm_dp_ctrl_push_idle(msm_dp_ctrl); 1984 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); 1985 1986 msm_dp_ctrl_psr_mainlink_disable(ctrl); 1987 } else { 1988 msm_dp_ctrl_psr_mainlink_enable(ctrl); 1989 1990 msm_dp_ctrl_psr_exit(ctrl); 1991 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); 1992 msm_dp_ctrl_wait4video_ready(ctrl); 1993 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); 1994 } 1995 } 1996 1997 static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) 1998 { 1999 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 2000 DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); 2001 usleep_range(1000, 1100); /* h/w recommended delay */ 2002 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0); 2003 } 2004 2005 void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) 2006 { 2007 struct msm_dp_ctrl_private *ctrl; 2008 struct phy *phy; 2009 2010 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2011 phy = ctrl->phy; 2012 2013 msm_dp_ctrl_phy_reset(ctrl); 2014 phy_init(phy); 2015 } 2016 2017 void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl) 2018 { 2019 struct msm_dp_ctrl_private *ctrl; 2020 struct phy *phy; 2021 2022 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2023 phy = ctrl->phy; 2024 2025 msm_dp_ctrl_phy_reset(ctrl); 2026 phy_exit(phy); 2027 } 2028 2029 static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl, 2030 struct msm_dp_panel *panel) 2031 { 2032 struct phy *phy = ctrl->phy; 2033 int ret = 0; 2034 2035 msm_dp_ctrl_mainlink_disable(ctrl); 2036 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 2037 phy_configure(phy, &ctrl->phy_opts); 2038 2039 /* 2040 * Disable and re-enable the mainlink clock since the 2041 * link clock might have been adjusted as part of the 2042 * link maintenance. 2043 */ 2044 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2045 2046 phy_power_off(phy); 2047 /* hw recommended delay before re-enabling clocks */ 2048 msleep(20); 2049 2050 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); 2051 if (ret) { 2052 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 2053 return ret; 2054 } 2055 2056 return ret; 2057 } 2058 2059 static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl, 2060 struct msm_dp_panel *panel) 2061 { 2062 struct phy *phy; 2063 2064 phy = ctrl->phy; 2065 2066 msm_dp_ctrl_mainlink_disable(ctrl); 2067 2068 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); 2069 2070 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2071 2072 phy_power_off(phy); 2073 2074 /* aux channel down, reinit phy */ 2075 phy_exit(phy); 2076 phy_init(phy); 2077 2078 return 0; 2079 } 2080 2081 static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl, 2082 struct msm_dp_panel *panel) 2083 { 2084 int ret = 0; 2085 int training_step = DP_TRAINING_NONE; 2086 2087 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); 2088 2089 ctrl->link->phy_params.p_level = 0; 2090 ctrl->link->phy_params.v_level = 0; 2091 2092 ret = msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); 2093 if (ret) 2094 goto end; 2095 2096 msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); 2097 2098 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); 2099 2100 ret = msm_dp_ctrl_wait4video_ready(ctrl); 2101 end: 2102 return ret; 2103 } 2104 2105 #define SCRAMBLER_RESET_COUNT_VALUE 0xFC 2106 2107 static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, 2108 u32 pattern) 2109 { 2110 u32 value = 0x0; 2111 2112 /* Make sure to clear the current pattern before starting a new one */ 2113 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); 2114 2115 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); 2116 switch (pattern) { 2117 case DP_PHY_TEST_PATTERN_D10_2: 2118 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2119 DP_STATE_CTRL_LINK_TRAINING_PATTERN1); 2120 break; 2121 2122 case DP_PHY_TEST_PATTERN_ERROR_COUNT: 2123 value &= ~(1 << 16); 2124 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 2125 value); 2126 value |= SCRAMBLER_RESET_COUNT_VALUE; 2127 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 2128 value); 2129 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, 2130 DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); 2131 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2132 DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); 2133 break; 2134 2135 case DP_PHY_TEST_PATTERN_PRBS7: 2136 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2137 DP_STATE_CTRL_LINK_PRBS7); 2138 break; 2139 2140 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2141 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2142 DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); 2143 /* 00111110000011111000001111100000 */ 2144 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 2145 0x3E0F83E0); 2146 /* 00001111100000111110000011111000 */ 2147 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 2148 0x0F83E0F8); 2149 /* 1111100000111110 */ 2150 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 2151 0x0000F83E); 2152 break; 2153 2154 case DP_PHY_TEST_PATTERN_CP2520: 2155 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 2156 value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; 2157 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); 2158 2159 value = DP_HBR2_ERM_PATTERN; 2160 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 2161 value); 2162 value |= SCRAMBLER_RESET_COUNT_VALUE; 2163 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 2164 value); 2165 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, 2166 DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); 2167 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2168 DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); 2169 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); 2170 value |= DP_MAINLINK_CTRL_ENABLE; 2171 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); 2172 break; 2173 2174 case DP_PHY_TEST_PATTERN_SEL_MASK: 2175 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, 2176 DP_MAINLINK_CTRL_ENABLE); 2177 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 2178 DP_STATE_CTRL_LINK_TRAINING_PATTERN4); 2179 break; 2180 2181 default: 2182 drm_dbg_dp(ctrl->drm_dev, 2183 "No valid test pattern requested: %#x\n", pattern); 2184 break; 2185 } 2186 } 2187 2188 static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) 2189 { 2190 bool success = false; 2191 u32 pattern_sent = 0x0; 2192 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 2193 2194 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); 2195 2196 if (msm_dp_ctrl_set_vx_px(ctrl, 2197 ctrl->link->phy_params.v_level, 2198 ctrl->link->phy_params.p_level)) { 2199 DRM_ERROR("Failed to set v/p levels\n"); 2200 return false; 2201 } 2202 msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested); 2203 msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); 2204 msm_dp_link_send_test_response(ctrl->link); 2205 2206 pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); 2207 2208 switch (pattern_sent) { 2209 case MR_LINK_TRAINING1: 2210 success = (pattern_requested == 2211 DP_PHY_TEST_PATTERN_D10_2); 2212 break; 2213 case MR_LINK_SYMBOL_ERM: 2214 success = ((pattern_requested == 2215 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 2216 (pattern_requested == 2217 DP_PHY_TEST_PATTERN_CP2520)); 2218 break; 2219 case MR_LINK_PRBS7: 2220 success = (pattern_requested == 2221 DP_PHY_TEST_PATTERN_PRBS7); 2222 break; 2223 case MR_LINK_CUSTOM80: 2224 success = (pattern_requested == 2225 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 2226 break; 2227 case MR_LINK_TRAINING4: 2228 success = (pattern_requested == 2229 DP_PHY_TEST_PATTERN_SEL_MASK); 2230 break; 2231 default: 2232 success = false; 2233 } 2234 2235 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", 2236 success ? "success" : "failed", pattern_requested); 2237 return success; 2238 } 2239 2240 static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate, 2241 enum msm_dp_stream_id stream_id) 2242 { 2243 int ret; 2244 2245 ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); 2246 if (ret) { 2247 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 2248 return ret; 2249 } 2250 2251 if (WARN_ON_ONCE(ctrl->stream_clks_on[stream_id])) 2252 return -EINVAL; 2253 2254 ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]); 2255 if (ret) { 2256 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 2257 return ret; 2258 } 2259 ctrl->stream_clks_on[stream_id] = true; 2260 2261 return ret; 2262 } 2263 2264 void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id) 2265 { 2266 struct msm_dp_ctrl_private *ctrl; 2267 2268 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2269 2270 if (ctrl->stream_clks_on[stream_id]) { 2271 clk_disable_unprepare(ctrl->pixel_clk[stream_id]); 2272 ctrl->stream_clks_on[stream_id] = false; 2273 } 2274 } 2275 2276 static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl, 2277 struct msm_dp_panel *panel) 2278 { 2279 int ret; 2280 unsigned long pixel_rate; 2281 2282 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 2283 drm_dbg_dp(ctrl->drm_dev, 2284 "no test pattern selected by sink\n"); 2285 return 0; 2286 } 2287 2288 /* 2289 * The global reset will need DP link related clocks to be 2290 * running. Add the global reset just before disabling the 2291 * link clocks and core clocks. 2292 */ 2293 msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, panel->stream_id); 2294 msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl, panel); 2295 2296 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, panel); 2297 if (ret) { 2298 DRM_ERROR("failed to enable DP link controller\n"); 2299 return ret; 2300 } 2301 2302 pixel_rate = panel->msm_dp_mode.drm_mode.clock; 2303 ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); 2304 if (ret) 2305 return ret; 2306 2307 msm_dp_ctrl_send_phy_test_pattern(ctrl); 2308 2309 return 0; 2310 } 2311 2312 void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl, 2313 struct msm_dp_panel *panel) 2314 { 2315 struct msm_dp_ctrl_private *ctrl; 2316 u32 sink_request = 0x0; 2317 2318 if (!msm_dp_ctrl) { 2319 DRM_ERROR("invalid input\n"); 2320 return; 2321 } 2322 2323 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2324 sink_request = ctrl->link->sink_request; 2325 2326 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 2327 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); 2328 if (msm_dp_ctrl_process_phy_test_request(ctrl, panel)) { 2329 DRM_ERROR("process phy_test_req failed\n"); 2330 return; 2331 } 2332 } 2333 2334 if (sink_request & DP_LINK_STATUS_UPDATED) { 2335 if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { 2336 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 2337 return; 2338 } 2339 } 2340 2341 if (sink_request & DP_TEST_LINK_TRAINING) { 2342 msm_dp_link_send_test_response(ctrl->link); 2343 if (msm_dp_ctrl_link_maintenance(ctrl, panel)) { 2344 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 2345 return; 2346 } 2347 } 2348 } 2349 2350 static bool msm_dp_ctrl_clock_recovery_any_ok( 2351 const u8 link_status[DP_LINK_STATUS_SIZE], 2352 int lane_count) 2353 { 2354 int reduced_cnt; 2355 2356 if (lane_count <= 1) 2357 return false; 2358 2359 /* 2360 * only interested in the lane number after reduced 2361 * lane_count = 4, then only interested in 2 lanes 2362 * lane_count = 2, then only interested in 1 lane 2363 */ 2364 reduced_cnt = lane_count >> 1; 2365 2366 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 2367 } 2368 2369 static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) 2370 { 2371 u8 link_status[DP_LINK_STATUS_SIZE]; 2372 int num_lanes = ctrl->link->link_params.num_lanes; 2373 2374 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 2375 2376 return drm_dp_channel_eq_ok(link_status, num_lanes); 2377 } 2378 2379 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, 2380 struct msm_dp_panel *panel) 2381 { 2382 int rc = 0; 2383 struct msm_dp_ctrl_private *ctrl; 2384 u32 rate; 2385 int link_train_max_retries = 5; 2386 u32 const phy_cts_pixel_clk_khz = 148500; 2387 u8 link_status[DP_LINK_STATUS_SIZE]; 2388 unsigned int training_step; 2389 unsigned long pixel_rate; 2390 2391 if (!msm_dp_ctrl) 2392 return -EINVAL; 2393 2394 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2395 2396 rate = panel->link_info.rate; 2397 pixel_rate = panel->msm_dp_mode.drm_mode.clock; 2398 2399 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); 2400 2401 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 2402 drm_dbg_dp(ctrl->drm_dev, 2403 "using phy test link parameters\n"); 2404 if (!pixel_rate) 2405 pixel_rate = phy_cts_pixel_clk_khz; 2406 } else { 2407 ctrl->link->link_params.rate = rate; 2408 ctrl->link->link_params.num_lanes = 2409 panel->link_info.num_lanes; 2410 if (panel->msm_dp_mode.out_fmt_is_yuv_420) 2411 pixel_rate >>= 1; 2412 } 2413 2414 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 2415 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, 2416 pixel_rate); 2417 2418 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); 2419 if (rc) 2420 return rc; 2421 2422 while (--link_train_max_retries) { 2423 training_step = DP_TRAINING_NONE; 2424 rc = msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); 2425 if (rc == 0) { 2426 /* training completed successfully */ 2427 break; 2428 } else if (training_step == DP_TRAINING_1) { 2429 /* link train_1 failed */ 2430 if (!msm_dp_aux_is_link_connected(ctrl->aux)) 2431 break; 2432 2433 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 2434 2435 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 2436 if (rc < 0) { /* already in RBR = 1.6G */ 2437 if (msm_dp_ctrl_clock_recovery_any_ok(link_status, 2438 ctrl->link->link_params.num_lanes)) { 2439 /* 2440 * some lanes are ready, 2441 * reduce lane number 2442 */ 2443 rc = msm_dp_ctrl_link_lane_down_shift(ctrl, panel); 2444 if (rc < 0) { /* lane == 1 already */ 2445 /* end with failure */ 2446 break; 2447 } 2448 } else { 2449 /* end with failure */ 2450 break; /* lane == 1 already */ 2451 } 2452 } 2453 } else if (training_step == DP_TRAINING_2) { 2454 /* link train_2 failed */ 2455 if (!msm_dp_aux_is_link_connected(ctrl->aux)) 2456 break; 2457 2458 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 2459 2460 if (!drm_dp_clock_recovery_ok(link_status, 2461 ctrl->link->link_params.num_lanes)) 2462 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 2463 else 2464 rc = msm_dp_ctrl_link_lane_down_shift(ctrl, panel); 2465 2466 if (rc < 0) { 2467 /* end with failure */ 2468 break; /* lane == 1 already */ 2469 } 2470 2471 /* stop link training before start re training */ 2472 msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); 2473 } 2474 2475 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl, panel); 2476 if (rc) { 2477 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); 2478 break; 2479 } 2480 } 2481 2482 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 2483 return rc; 2484 2485 if (!link_train_max_retries) 2486 rc = -ETIMEDOUT; 2487 2488 if (rc == 0) { /* link train successfully */ 2489 /* 2490 * do not stop train pattern here 2491 * stop link training at on_stream 2492 * to pass compliance test 2493 */ 2494 } else { 2495 /* 2496 * link training failed 2497 * end txing train pattern here 2498 */ 2499 msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); 2500 2501 msm_dp_ctrl_deinitialize_mainlink(ctrl, panel); 2502 rc = -ECONNRESET; 2503 } 2504 2505 return rc; 2506 } 2507 2508 static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl, 2509 struct msm_dp_panel *panel) 2510 { 2511 int training_step = DP_TRAINING_NONE; 2512 2513 return msm_dp_ctrl_setup_main_link(ctrl, panel, &training_step); 2514 } 2515 2516 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, 2517 struct msm_dp_panel *panel, u32 rate) 2518 { 2519 u32 pixel_m, pixel_n; 2520 u32 mvid, nvid, pixel_div, dispcc_input_rate; 2521 u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; 2522 u32 const link_rate_hbr2 = 540000; 2523 u32 const link_rate_hbr3 = 810000; 2524 u32 stream_rate_khz = panel->msm_dp_mode.drm_mode.clock; 2525 unsigned long den, num; 2526 2527 switch (rate) { 2528 case link_rate_hbr3: 2529 pixel_div = 6; 2530 break; 2531 case link_rate_hbr2: 2532 pixel_div = 4; 2533 break; 2534 case 162000: 2535 case 270000: 2536 pixel_div = 2; 2537 break; 2538 default: 2539 /* 2540 * This cannot be reached but the compiler is not able to know 2541 * that statically so return early to avoid a possibly invalid 2542 * division. 2543 */ 2544 DRM_ERROR("Invalid pixel mux divider\n"); 2545 return; 2546 } 2547 2548 dispcc_input_rate = (rate * 10) / pixel_div; 2549 2550 rational_best_approximation(dispcc_input_rate, stream_rate_khz, 2551 (unsigned long)(1 << 16) - 1, 2552 (unsigned long)(1 << 16) - 1, &den, &num); 2553 2554 den = ~(den - num); 2555 den = den & 0xFFFF; 2556 pixel_m = num; 2557 pixel_n = den; 2558 2559 mvid = (pixel_m & 0xFFFF) * 5; 2560 nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); 2561 2562 if (nvid < nvid_fixed) { 2563 u32 temp; 2564 2565 temp = (nvid_fixed / nvid) * nvid; 2566 mvid = (nvid_fixed / nvid) * mvid; 2567 nvid = temp; 2568 } 2569 2570 if (panel->msm_dp_mode.out_fmt_is_yuv_420) 2571 mvid /= 2; 2572 2573 if (link_rate_hbr2 == rate) 2574 nvid *= 2; 2575 2576 if (link_rate_hbr3 == rate) 2577 nvid *= 3; 2578 2579 drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); 2580 msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_MVID, mvid); 2581 msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, nvid); 2582 } 2583 2584 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, 2585 struct msm_dp_panel *panel, 2586 bool force_link_train) 2587 { 2588 int ret = 0; 2589 struct msm_dp_ctrl_private *ctrl; 2590 2591 if (!msm_dp_ctrl) 2592 return -EINVAL; 2593 2594 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2595 2596 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d\n", 2597 ctrl->link->link_params.rate, 2598 ctrl->link->link_params.num_lanes); 2599 2600 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=%d link_clk_on=%d\n", 2601 ctrl->core_clks_on, ctrl->link_clks_on); 2602 2603 if (!ctrl->link_clks_on) { /* link clk is off */ 2604 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl, panel); 2605 if (ret) { 2606 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 2607 return ret; 2608 } 2609 } 2610 2611 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) 2612 msm_dp_ctrl_link_retrain(ctrl, panel); 2613 2614 /* stop txing train pattern to end link training */ 2615 msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX); 2616 2617 return ret; 2618 } 2619 2620 int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *panel) 2621 { 2622 int ret = 0; 2623 bool mainlink_ready = false; 2624 struct msm_dp_ctrl_private *ctrl; 2625 unsigned long pixel_rate; 2626 2627 if (!msm_dp_ctrl) 2628 return -EINVAL; 2629 2630 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2631 2632 pixel_rate = panel->msm_dp_mode.drm_mode.clock; 2633 2634 if (msm_dp_ctrl->wide_bus_en || panel->msm_dp_mode.out_fmt_is_yuv_420) 2635 pixel_rate >>= 1; 2636 2637 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate); 2638 2639 ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, panel->stream_id); 2640 if (ret) 2641 return ret; 2642 2643 /* 2644 * Set up transfer unit values and set controller state to send 2645 * video. 2646 */ 2647 reinit_completion(&ctrl->video_comp); 2648 2649 msm_dp_ctrl_lane_mapping(ctrl); 2650 msm_dp_setup_peripheral_flush(ctrl); 2651 2652 msm_dp_ctrl_configure_source_params(ctrl, panel); 2653 2654 msm_dp_ctrl_config_msa(ctrl, panel, 2655 ctrl->link->link_params.rate); 2656 2657 msm_dp_panel_clear_dsc_dto(panel); 2658 2659 msm_dp_ctrl_setup_tr_unit(ctrl, panel); 2660 2661 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); 2662 2663 ret = msm_dp_ctrl_wait4video_ready(ctrl); 2664 if (ret) 2665 return ret; 2666 2667 mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl); 2668 drm_dbg_dp(ctrl->drm_dev, 2669 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 2670 2671 return ret; 2672 } 2673 2674 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) 2675 { 2676 struct msm_dp_ctrl_private *ctrl; 2677 struct phy *phy; 2678 2679 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2680 phy = ctrl->phy; 2681 2682 /* aux channel down, reinit phy */ 2683 phy_exit(phy); 2684 phy_init(phy); 2685 } 2686 2687 void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl, 2688 struct msm_dp_panel *panel) 2689 { 2690 struct msm_dp_ctrl_private *ctrl; 2691 struct phy *phy; 2692 2693 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2694 phy = ctrl->phy; 2695 2696 msm_dp_ctrl_mainlink_disable(ctrl); 2697 2698 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl, panel); 2699 2700 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2701 2702 phy_power_off(phy); 2703 } 2704 2705 irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl, 2706 struct msm_dp_panel *panel) 2707 { 2708 struct msm_dp_ctrl_private *ctrl; 2709 u32 isr; 2710 irqreturn_t ret = IRQ_NONE; 2711 2712 if (!msm_dp_ctrl) 2713 return IRQ_NONE; 2714 2715 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2716 2717 if (panel->psr_cap.version) { 2718 isr = msm_dp_ctrl_get_psr_interrupt(ctrl); 2719 2720 if (isr) 2721 complete(&ctrl->psr_op_comp); 2722 2723 if (isr & PSR_EXIT_INT) 2724 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); 2725 2726 if (isr & PSR_UPDATE_INT) 2727 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); 2728 2729 if (isr & PSR_CAPTURE_INT) 2730 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); 2731 } 2732 2733 isr = msm_dp_ctrl_get_interrupt(ctrl); 2734 2735 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 2736 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); 2737 complete(&ctrl->video_comp); 2738 ret = IRQ_HANDLED; 2739 } 2740 2741 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 2742 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); 2743 complete(&ctrl->idle_comp); 2744 ret = IRQ_HANDLED; 2745 } 2746 2747 /* DP aux isr */ 2748 isr = msm_dp_ctrl_get_aux_interrupt(ctrl); 2749 if (isr) 2750 ret |= msm_dp_aux_isr(ctrl->aux, isr); 2751 2752 return ret; 2753 } 2754 2755 static const char *core_clks[] = { 2756 "core_iface", 2757 "core_aux", 2758 }; 2759 2760 static const char *ctrl_clks[] = { 2761 "ctrl_link", 2762 "ctrl_link_iface", 2763 }; 2764 2765 static const char * const pixel_clks[] = { 2766 "stream_pixel", 2767 "stream_1_pixel", 2768 "stream_2_pixel", 2769 "stream_3_pixel", 2770 }; 2771 2772 static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) 2773 { 2774 struct msm_dp_ctrl_private *ctrl; 2775 struct device *dev; 2776 int i, rc; 2777 2778 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2779 dev = ctrl->dev; 2780 2781 ctrl->num_core_clks = ARRAY_SIZE(core_clks); 2782 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); 2783 if (!ctrl->core_clks) 2784 return -ENOMEM; 2785 2786 for (i = 0; i < ctrl->num_core_clks; i++) 2787 ctrl->core_clks[i].id = core_clks[i]; 2788 2789 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); 2790 if (rc) 2791 return rc; 2792 2793 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); 2794 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); 2795 if (!ctrl->link_clks) 2796 return -ENOMEM; 2797 2798 for (i = 0; i < ctrl->num_link_clks; i++) 2799 ctrl->link_clks[i].id = ctrl_clks[i]; 2800 2801 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); 2802 if (rc) 2803 return rc; 2804 2805 ctrl->pixel_clk[0] = devm_clk_get(dev, pixel_clks[0]); 2806 if (IS_ERR(ctrl->pixel_clk[0])) 2807 return PTR_ERR(ctrl->pixel_clk[0]); 2808 ctrl->num_pixel_clks = 1; 2809 2810 for (i = DP_STREAM_1; i < DP_STREAM_MAX; i++) { 2811 ctrl->pixel_clk[i] = devm_clk_get_optional(dev, pixel_clks[i]); 2812 if (IS_ERR(ctrl->pixel_clk[i])) 2813 return PTR_ERR(ctrl->pixel_clk[i]); 2814 if (!ctrl->pixel_clk[i]) 2815 break; 2816 ctrl->num_pixel_clks++; 2817 } 2818 2819 return 0; 2820 } 2821 2822 bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *msm_dp_ctrl, 2823 enum msm_dp_stream_id stream_id) 2824 { 2825 struct msm_dp_ctrl_private *ctrl; 2826 2827 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2828 2829 return ctrl->stream_clks_on[stream_id]; 2830 } 2831 2832 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, 2833 struct drm_dp_aux *aux, 2834 struct phy *phy, 2835 void __iomem *ahb_base, 2836 void __iomem *link_base, 2837 void __iomem *mst2link_base, 2838 void __iomem *mst3link_base) 2839 { 2840 struct msm_dp_ctrl_private *ctrl; 2841 int ret; 2842 2843 if (!dev || !aux || !link) { 2844 DRM_ERROR("invalid input\n"); 2845 return ERR_PTR(-EINVAL); 2846 } 2847 2848 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 2849 if (!ctrl) { 2850 DRM_ERROR("Mem allocation failure\n"); 2851 return ERR_PTR(-ENOMEM); 2852 } 2853 2854 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 2855 if (ret) { 2856 dev_err(dev, "invalid DP OPP table in device tree\n"); 2857 /* caller do PTR_ERR(opp_table) */ 2858 return (struct msm_dp_ctrl *)ERR_PTR(ret); 2859 } 2860 2861 /* OPP table is optional */ 2862 ret = devm_pm_opp_of_add_table(dev); 2863 if (ret) 2864 dev_err(dev, "failed to add DP OPP table\n"); 2865 2866 init_completion(&ctrl->idle_comp); 2867 init_completion(&ctrl->psr_op_comp); 2868 init_completion(&ctrl->video_comp); 2869 2870 /* in parameters */ 2871 ctrl->aux = aux; 2872 ctrl->link = link; 2873 ctrl->dev = dev; 2874 ctrl->phy = phy; 2875 ctrl->ahb_base = ahb_base; 2876 ctrl->link_base = link_base; 2877 ctrl->mst2link_base = mst2link_base; 2878 ctrl->mst3link_base = mst3link_base; 2879 2880 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); 2881 if (ret) { 2882 dev_err(dev, "failed to init clocks\n"); 2883 return ERR_PTR(ret); 2884 } 2885 2886 return &ctrl->msm_dp_ctrl; 2887 } 2888