xref: /linux/drivers/gpu/drm/msm/dp/dp_catalog.h (revision 4ae68b26c3ab5a82aa271e6e9fc9b1a06e1d6b40) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _DP_CATALOG_H_
7 #define _DP_CATALOG_H_
8 
9 #include <drm/drm_modes.h>
10 
11 #include "dp_parser.h"
12 #include "disp/msm_disp_snapshot.h"
13 
14 /* interrupts */
15 #define DP_INTR_HPD		BIT(0)
16 #define DP_INTR_AUX_XFER_DONE	BIT(3)
17 #define DP_INTR_WRONG_ADDR	BIT(6)
18 #define DP_INTR_TIMEOUT		BIT(9)
19 #define DP_INTR_NACK_DEFER	BIT(12)
20 #define DP_INTR_WRONG_DATA_CNT	BIT(15)
21 #define DP_INTR_I2C_NACK	BIT(18)
22 #define DP_INTR_I2C_DEFER	BIT(21)
23 #define DP_INTR_PLL_UNLOCKED	BIT(24)
24 #define DP_INTR_AUX_ERROR	BIT(27)
25 
26 #define DP_INTR_READY_FOR_VIDEO		BIT(0)
27 #define DP_INTR_IDLE_PATTERN_SENT	BIT(3)
28 #define DP_INTR_FRAME_END		BIT(6)
29 #define DP_INTR_CRC_UPDATED		BIT(9)
30 
31 #define DP_AUX_CFG_MAX_VALUE_CNT 3
32 
33 /* PHY AUX config registers */
34 enum dp_phy_aux_config_type {
35 	PHY_AUX_CFG0,
36 	PHY_AUX_CFG1,
37 	PHY_AUX_CFG2,
38 	PHY_AUX_CFG3,
39 	PHY_AUX_CFG4,
40 	PHY_AUX_CFG5,
41 	PHY_AUX_CFG6,
42 	PHY_AUX_CFG7,
43 	PHY_AUX_CFG8,
44 	PHY_AUX_CFG9,
45 	PHY_AUX_CFG_MAX,
46 };
47 
48 enum dp_catalog_audio_sdp_type {
49 	DP_AUDIO_SDP_STREAM,
50 	DP_AUDIO_SDP_TIMESTAMP,
51 	DP_AUDIO_SDP_INFOFRAME,
52 	DP_AUDIO_SDP_COPYMANAGEMENT,
53 	DP_AUDIO_SDP_ISRC,
54 	DP_AUDIO_SDP_MAX,
55 };
56 
57 enum dp_catalog_audio_header_type {
58 	DP_AUDIO_SDP_HEADER_1,
59 	DP_AUDIO_SDP_HEADER_2,
60 	DP_AUDIO_SDP_HEADER_3,
61 	DP_AUDIO_SDP_HEADER_MAX,
62 };
63 
64 struct dp_catalog {
65 	u32 aux_data;
66 	u32 total;
67 	u32 sync_start;
68 	u32 width_blanking;
69 	u32 dp_active;
70 	enum dp_catalog_audio_sdp_type sdp_type;
71 	enum dp_catalog_audio_header_type sdp_header;
72 	u32 audio_data;
73 	bool wide_bus_en;
74 };
75 
76 /* Debug module */
77 void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state);
78 
79 /* AUX APIs */
80 u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
81 int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
82 int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog);
83 int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read);
84 int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog);
85 void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
86 void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
87 void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
88 int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog);
89 u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
90 
91 /* DP Controller APIs */
92 void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
93 void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
94 void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
95 void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
96 void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
97 void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
98 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
99 				u32 stream_rate_khz, bool fixed_nvid);
100 int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);
101 u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog);
102 void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);
103 bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog);
104 void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
105 void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
106 			u32 intr_mask, bool en);
107 void dp_catalog_ctrl_hpd_enable(struct dp_catalog *dp_catalog);
108 void dp_catalog_ctrl_hpd_disable(struct dp_catalog *dp_catalog);
109 void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
110 void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
111 u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
112 u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
113 void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
114 int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
115 				u8 p_level);
116 int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
117 u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog);
118 void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
119 				u32 dp_tu, u32 valid_boundary,
120 				u32 valid_boundary2);
121 void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
122 				u32 pattern);
123 u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog);
124 
125 /* DP Panel APIs */
126 int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog);
127 void dp_catalog_dump_regs(struct dp_catalog *dp_catalog);
128 void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog,
129 				struct drm_display_mode *drm_mode);
130 void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog);
131 
132 struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io);
133 
134 /* DP Audio APIs */
135 void dp_catalog_audio_get_header(struct dp_catalog *catalog);
136 void dp_catalog_audio_set_header(struct dp_catalog *catalog);
137 void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
138 void dp_catalog_audio_enable(struct dp_catalog *catalog);
139 void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
140 void dp_catalog_audio_init(struct dp_catalog *catalog);
141 void dp_catalog_audio_sfe_level(struct dp_catalog *catalog);
142 
143 #endif /* _DP_CATALOG_H_ */
144