1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, 194 struct drm_encoder *encoder) 195 { 196 return rate; 197 } 198 199 static int mdp5_set_split_display(struct msm_kms *kms, 200 struct drm_encoder *encoder, 201 struct drm_encoder *slave_encoder, 202 bool is_cmd_mode) 203 { 204 if (is_cmd_mode) 205 return mdp5_cmd_encoder_set_split_display(encoder, 206 slave_encoder); 207 else 208 return mdp5_vid_encoder_set_split_display(encoder, 209 slave_encoder); 210 } 211 212 static void mdp5_kms_destroy(struct msm_kms *kms) 213 { 214 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 215 struct msm_gem_address_space *aspace = kms->aspace; 216 int i; 217 218 for (i = 0; i < mdp5_kms->num_hwmixers; i++) 219 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); 220 221 for (i = 0; i < mdp5_kms->num_hwpipes; i++) 222 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); 223 224 if (aspace) { 225 aspace->mmu->funcs->detach(aspace->mmu); 226 msm_gem_address_space_put(aspace); 227 } 228 229 mdp_kms_destroy(&mdp5_kms->base); 230 } 231 232 #ifdef CONFIG_DEBUG_FS 233 static int smp_show(struct seq_file *m, void *arg) 234 { 235 struct drm_info_node *node = (struct drm_info_node *) m->private; 236 struct drm_device *dev = node->minor->dev; 237 struct msm_drm_private *priv = dev->dev_private; 238 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 239 struct drm_printer p = drm_seq_file_printer(m); 240 241 if (!mdp5_kms->smp) { 242 drm_printf(&p, "no SMP pool\n"); 243 return 0; 244 } 245 246 mdp5_smp_dump(mdp5_kms->smp, &p); 247 248 return 0; 249 } 250 251 static struct drm_info_list mdp5_debugfs_list[] = { 252 {"smp", smp_show }, 253 }; 254 255 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 256 { 257 drm_debugfs_create_files(mdp5_debugfs_list, 258 ARRAY_SIZE(mdp5_debugfs_list), 259 minor->debugfs_root, minor); 260 261 return 0; 262 } 263 #endif 264 265 static const struct mdp_kms_funcs kms_funcs = { 266 .base = { 267 .hw_init = mdp5_hw_init, 268 .irq_preinstall = mdp5_irq_preinstall, 269 .irq_postinstall = mdp5_irq_postinstall, 270 .irq_uninstall = mdp5_irq_uninstall, 271 .irq = mdp5_irq, 272 .enable_vblank = mdp5_enable_vblank, 273 .disable_vblank = mdp5_disable_vblank, 274 .flush_commit = mdp5_flush_commit, 275 .enable_commit = mdp5_enable_commit, 276 .disable_commit = mdp5_disable_commit, 277 .prepare_commit = mdp5_prepare_commit, 278 .wait_flush = mdp5_wait_flush, 279 .complete_commit = mdp5_complete_commit, 280 .get_format = mdp_get_format, 281 .round_pixclk = mdp5_round_pixclk, 282 .set_split_display = mdp5_set_split_display, 283 .destroy = mdp5_kms_destroy, 284 #ifdef CONFIG_DEBUG_FS 285 .debugfs_init = mdp5_kms_debugfs_init, 286 #endif 287 }, 288 .set_irqmask = mdp5_set_irqmask, 289 }; 290 291 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 292 { 293 DBG(""); 294 295 mdp5_kms->enable_count--; 296 WARN_ON(mdp5_kms->enable_count < 0); 297 298 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 299 clk_disable_unprepare(mdp5_kms->tbu_clk); 300 clk_disable_unprepare(mdp5_kms->ahb_clk); 301 clk_disable_unprepare(mdp5_kms->axi_clk); 302 clk_disable_unprepare(mdp5_kms->core_clk); 303 clk_disable_unprepare(mdp5_kms->lut_clk); 304 305 return 0; 306 } 307 308 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 309 { 310 DBG(""); 311 312 mdp5_kms->enable_count++; 313 314 clk_prepare_enable(mdp5_kms->ahb_clk); 315 clk_prepare_enable(mdp5_kms->axi_clk); 316 clk_prepare_enable(mdp5_kms->core_clk); 317 clk_prepare_enable(mdp5_kms->lut_clk); 318 clk_prepare_enable(mdp5_kms->tbu_clk); 319 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 320 321 return 0; 322 } 323 324 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 325 struct mdp5_interface *intf, 326 struct mdp5_ctl *ctl) 327 { 328 struct drm_device *dev = mdp5_kms->dev; 329 struct msm_drm_private *priv = dev->dev_private; 330 struct drm_encoder *encoder; 331 332 encoder = mdp5_encoder_init(dev, intf, ctl); 333 if (IS_ERR(encoder)) { 334 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 335 return encoder; 336 } 337 338 priv->encoders[priv->num_encoders++] = encoder; 339 340 return encoder; 341 } 342 343 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 344 { 345 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 346 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 347 int id = 0, i; 348 349 for (i = 0; i < intf_cnt; i++) { 350 if (intfs[i] == INTF_DSI) { 351 if (intf_num == i) 352 return id; 353 354 id++; 355 } 356 } 357 358 return -EINVAL; 359 } 360 361 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 362 struct mdp5_interface *intf) 363 { 364 struct drm_device *dev = mdp5_kms->dev; 365 struct msm_drm_private *priv = dev->dev_private; 366 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 367 struct mdp5_ctl *ctl; 368 struct drm_encoder *encoder; 369 int ret = 0; 370 371 switch (intf->type) { 372 case INTF_eDP: 373 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); 374 break; 375 case INTF_HDMI: 376 if (!priv->hdmi) 377 break; 378 379 ctl = mdp5_ctlm_request(ctlm, intf->num); 380 if (!ctl) { 381 ret = -EINVAL; 382 break; 383 } 384 385 encoder = construct_encoder(mdp5_kms, intf, ctl); 386 if (IS_ERR(encoder)) { 387 ret = PTR_ERR(encoder); 388 break; 389 } 390 391 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 392 break; 393 case INTF_DSI: 394 { 395 const struct mdp5_cfg_hw *hw_cfg = 396 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 397 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 398 399 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 400 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 401 intf->num); 402 ret = -EINVAL; 403 break; 404 } 405 406 if (!priv->dsi[dsi_id]) 407 break; 408 409 ctl = mdp5_ctlm_request(ctlm, intf->num); 410 if (!ctl) { 411 ret = -EINVAL; 412 break; 413 } 414 415 encoder = construct_encoder(mdp5_kms, intf, ctl); 416 if (IS_ERR(encoder)) { 417 ret = PTR_ERR(encoder); 418 break; 419 } 420 421 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 422 if (!ret) 423 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id])); 424 425 break; 426 } 427 default: 428 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 429 ret = -EINVAL; 430 break; 431 } 432 433 return ret; 434 } 435 436 static int modeset_init(struct mdp5_kms *mdp5_kms) 437 { 438 struct drm_device *dev = mdp5_kms->dev; 439 struct msm_drm_private *priv = dev->dev_private; 440 unsigned int num_crtcs; 441 int i, ret, pi = 0, ci = 0; 442 struct drm_plane *primary[MAX_BASES] = { NULL }; 443 struct drm_plane *cursor[MAX_BASES] = { NULL }; 444 445 /* 446 * Construct encoders and modeset initialize connector devices 447 * for each external display interface. 448 */ 449 for (i = 0; i < mdp5_kms->num_intfs; i++) { 450 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 451 if (ret) 452 goto fail; 453 } 454 455 /* 456 * We should ideally have less number of encoders (set up by parsing 457 * the MDP5 interfaces) than the number of layer mixers present in HW, 458 * but let's be safe here anyway 459 */ 460 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); 461 462 /* 463 * Construct planes equaling the number of hw pipes, and CRTCs for the 464 * N encoders set up by the driver. The first N planes become primary 465 * planes for the CRTCs, with the remainder as overlay planes: 466 */ 467 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 468 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 469 struct drm_plane *plane; 470 enum drm_plane_type type; 471 472 if (i < num_crtcs) 473 type = DRM_PLANE_TYPE_PRIMARY; 474 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 475 type = DRM_PLANE_TYPE_CURSOR; 476 else 477 type = DRM_PLANE_TYPE_OVERLAY; 478 479 plane = mdp5_plane_init(dev, type); 480 if (IS_ERR(plane)) { 481 ret = PTR_ERR(plane); 482 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 483 goto fail; 484 } 485 priv->planes[priv->num_planes++] = plane; 486 487 if (type == DRM_PLANE_TYPE_PRIMARY) 488 primary[pi++] = plane; 489 if (type == DRM_PLANE_TYPE_CURSOR) 490 cursor[ci++] = plane; 491 } 492 493 for (i = 0; i < num_crtcs; i++) { 494 struct drm_crtc *crtc; 495 496 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 497 if (IS_ERR(crtc)) { 498 ret = PTR_ERR(crtc); 499 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 500 goto fail; 501 } 502 priv->crtcs[priv->num_crtcs++] = crtc; 503 } 504 505 /* 506 * Now that we know the number of crtcs we've created, set the possible 507 * crtcs for the encoders 508 */ 509 for (i = 0; i < priv->num_encoders; i++) { 510 struct drm_encoder *encoder = priv->encoders[i]; 511 512 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 513 } 514 515 return 0; 516 517 fail: 518 return ret; 519 } 520 521 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 522 u32 *major, u32 *minor) 523 { 524 struct device *dev = &mdp5_kms->pdev->dev; 525 u32 version; 526 527 pm_runtime_get_sync(dev); 528 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 529 pm_runtime_put_sync(dev); 530 531 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 532 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 533 534 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 535 } 536 537 static int get_clk(struct platform_device *pdev, struct clk **clkp, 538 const char *name, bool mandatory) 539 { 540 struct device *dev = &pdev->dev; 541 struct clk *clk = msm_clk_get(pdev, name); 542 if (IS_ERR(clk) && mandatory) { 543 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 544 return PTR_ERR(clk); 545 } 546 if (IS_ERR(clk)) 547 DBG("skipping %s", name); 548 else 549 *clkp = clk; 550 551 return 0; 552 } 553 554 struct msm_kms *mdp5_kms_init(struct drm_device *dev) 555 { 556 struct msm_drm_private *priv = dev->dev_private; 557 struct platform_device *pdev; 558 struct mdp5_kms *mdp5_kms; 559 struct mdp5_cfg *config; 560 struct msm_kms *kms; 561 struct msm_gem_address_space *aspace; 562 int irq, i, ret; 563 struct device *iommu_dev; 564 565 /* priv->kms would have been populated by the MDP5 driver */ 566 kms = priv->kms; 567 if (!kms) 568 return NULL; 569 570 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 571 pdev = mdp5_kms->pdev; 572 573 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 574 if (ret) { 575 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 576 goto fail; 577 } 578 579 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 580 if (irq < 0) { 581 ret = irq; 582 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret); 583 goto fail; 584 } 585 586 kms->irq = irq; 587 588 config = mdp5_cfg_get_config(mdp5_kms->cfg); 589 590 /* make sure things are off before attaching iommu (bootloader could 591 * have left things on, in which case we'll start getting faults if 592 * we don't disable): 593 */ 594 pm_runtime_get_sync(&pdev->dev); 595 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 596 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 597 !config->hw->intf.base[i]) 598 continue; 599 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 600 601 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 602 } 603 mdelay(16); 604 605 if (config->platform.iommu) { 606 struct msm_mmu *mmu; 607 608 iommu_dev = &pdev->dev; 609 if (!dev_iommu_fwspec_get(iommu_dev)) 610 iommu_dev = iommu_dev->parent; 611 612 mmu = msm_iommu_new(iommu_dev, config->platform.iommu); 613 614 aspace = msm_gem_address_space_create(mmu, "mdp5", 615 0x1000, 0x100000000 - 0x1000); 616 617 if (IS_ERR(aspace)) { 618 if (!IS_ERR(mmu)) 619 mmu->funcs->destroy(mmu); 620 ret = PTR_ERR(aspace); 621 goto fail; 622 } 623 624 kms->aspace = aspace; 625 } else { 626 DRM_DEV_INFO(&pdev->dev, 627 "no iommu, fallback to phys contig buffers for scanout\n"); 628 aspace = NULL; 629 } 630 631 pm_runtime_put_sync(&pdev->dev); 632 633 ret = modeset_init(mdp5_kms); 634 if (ret) { 635 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 636 goto fail; 637 } 638 639 dev->mode_config.min_width = 0; 640 dev->mode_config.min_height = 0; 641 dev->mode_config.max_width = 0xffff; 642 dev->mode_config.max_height = 0xffff; 643 644 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 645 dev->vblank_disable_immediate = true; 646 647 return kms; 648 fail: 649 if (kms) 650 mdp5_kms_destroy(kms); 651 return ERR_PTR(ret); 652 } 653 654 static void mdp5_destroy(struct platform_device *pdev) 655 { 656 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 657 int i; 658 659 if (mdp5_kms->ctlm) 660 mdp5_ctlm_destroy(mdp5_kms->ctlm); 661 if (mdp5_kms->smp) 662 mdp5_smp_destroy(mdp5_kms->smp); 663 if (mdp5_kms->cfg) 664 mdp5_cfg_destroy(mdp5_kms->cfg); 665 666 for (i = 0; i < mdp5_kms->num_intfs; i++) 667 kfree(mdp5_kms->intfs[i]); 668 669 if (mdp5_kms->rpm_enabled) 670 pm_runtime_disable(&pdev->dev); 671 672 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 673 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 674 } 675 676 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 677 const enum mdp5_pipe *pipes, const uint32_t *offsets, 678 uint32_t caps) 679 { 680 struct drm_device *dev = mdp5_kms->dev; 681 int i, ret; 682 683 for (i = 0; i < cnt; i++) { 684 struct mdp5_hw_pipe *hwpipe; 685 686 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); 687 if (IS_ERR(hwpipe)) { 688 ret = PTR_ERR(hwpipe); 689 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 690 pipe2name(pipes[i]), ret); 691 return ret; 692 } 693 hwpipe->idx = mdp5_kms->num_hwpipes; 694 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 695 } 696 697 return 0; 698 } 699 700 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 701 { 702 static const enum mdp5_pipe rgb_planes[] = { 703 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 704 }; 705 static const enum mdp5_pipe vig_planes[] = { 706 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 707 }; 708 static const enum mdp5_pipe dma_planes[] = { 709 SSPP_DMA0, SSPP_DMA1, 710 }; 711 static const enum mdp5_pipe cursor_planes[] = { 712 SSPP_CURSOR0, SSPP_CURSOR1, 713 }; 714 const struct mdp5_cfg_hw *hw_cfg; 715 int ret; 716 717 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 718 719 /* Construct RGB pipes: */ 720 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 721 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 722 if (ret) 723 return ret; 724 725 /* Construct video (VIG) pipes: */ 726 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 727 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 728 if (ret) 729 return ret; 730 731 /* Construct DMA pipes: */ 732 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 733 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 734 if (ret) 735 return ret; 736 737 /* Construct cursor pipes: */ 738 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 739 cursor_planes, hw_cfg->pipe_cursor.base, 740 hw_cfg->pipe_cursor.caps); 741 if (ret) 742 return ret; 743 744 return 0; 745 } 746 747 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 748 { 749 struct drm_device *dev = mdp5_kms->dev; 750 const struct mdp5_cfg_hw *hw_cfg; 751 int i, ret; 752 753 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 754 755 for (i = 0; i < hw_cfg->lm.count; i++) { 756 struct mdp5_hw_mixer *mixer; 757 758 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); 759 if (IS_ERR(mixer)) { 760 ret = PTR_ERR(mixer); 761 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 762 i, ret); 763 return ret; 764 } 765 766 mixer->idx = mdp5_kms->num_hwmixers; 767 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 768 } 769 770 return 0; 771 } 772 773 static int interface_init(struct mdp5_kms *mdp5_kms) 774 { 775 struct drm_device *dev = mdp5_kms->dev; 776 const struct mdp5_cfg_hw *hw_cfg; 777 const enum mdp5_intf_type *intf_types; 778 int i; 779 780 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 781 intf_types = hw_cfg->intf.connect; 782 783 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 784 struct mdp5_interface *intf; 785 786 if (intf_types[i] == INTF_DISABLED) 787 continue; 788 789 intf = kzalloc(sizeof(*intf), GFP_KERNEL); 790 if (!intf) { 791 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 792 return -ENOMEM; 793 } 794 795 intf->num = i; 796 intf->type = intf_types[i]; 797 intf->mode = MDP5_INTF_MODE_NONE; 798 intf->idx = mdp5_kms->num_intfs; 799 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 800 } 801 802 return 0; 803 } 804 805 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 806 { 807 struct msm_drm_private *priv = dev->dev_private; 808 struct mdp5_kms *mdp5_kms; 809 struct mdp5_cfg *config; 810 u32 major, minor; 811 int ret; 812 813 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 814 if (!mdp5_kms) { 815 ret = -ENOMEM; 816 goto fail; 817 } 818 819 platform_set_drvdata(pdev, mdp5_kms); 820 821 spin_lock_init(&mdp5_kms->resource_lock); 822 823 mdp5_kms->dev = dev; 824 mdp5_kms->pdev = pdev; 825 826 ret = mdp5_global_obj_init(mdp5_kms); 827 if (ret) 828 goto fail; 829 830 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); 831 if (IS_ERR(mdp5_kms->mmio)) { 832 ret = PTR_ERR(mdp5_kms->mmio); 833 goto fail; 834 } 835 836 /* mandatory clocks: */ 837 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 838 if (ret) 839 goto fail; 840 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 841 if (ret) 842 goto fail; 843 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 844 if (ret) 845 goto fail; 846 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 847 if (ret) 848 goto fail; 849 850 /* optional clocks: */ 851 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 852 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 853 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 854 855 /* we need to set a default rate before enabling. Set a safe 856 * rate first, then figure out hw revision, and then set a 857 * more optimal rate: 858 */ 859 clk_set_rate(mdp5_kms->core_clk, 200000000); 860 861 pm_runtime_enable(&pdev->dev); 862 mdp5_kms->rpm_enabled = true; 863 864 read_mdp_hw_revision(mdp5_kms, &major, &minor); 865 866 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 867 if (IS_ERR(mdp5_kms->cfg)) { 868 ret = PTR_ERR(mdp5_kms->cfg); 869 mdp5_kms->cfg = NULL; 870 goto fail; 871 } 872 873 config = mdp5_cfg_get_config(mdp5_kms->cfg); 874 mdp5_kms->caps = config->hw->mdp.caps; 875 876 /* TODO: compute core clock rate at runtime */ 877 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 878 879 /* 880 * Some chipsets have a Shared Memory Pool (SMP), while others 881 * have dedicated latency buffering per source pipe instead; 882 * this section initializes the SMP: 883 */ 884 if (mdp5_kms->caps & MDP_CAP_SMP) { 885 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 886 if (IS_ERR(mdp5_kms->smp)) { 887 ret = PTR_ERR(mdp5_kms->smp); 888 mdp5_kms->smp = NULL; 889 goto fail; 890 } 891 } 892 893 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 894 if (IS_ERR(mdp5_kms->ctlm)) { 895 ret = PTR_ERR(mdp5_kms->ctlm); 896 mdp5_kms->ctlm = NULL; 897 goto fail; 898 } 899 900 ret = hwpipe_init(mdp5_kms); 901 if (ret) 902 goto fail; 903 904 ret = hwmixer_init(mdp5_kms); 905 if (ret) 906 goto fail; 907 908 ret = interface_init(mdp5_kms); 909 if (ret) 910 goto fail; 911 912 /* set uninit-ed kms */ 913 priv->kms = &mdp5_kms->base.base; 914 915 return 0; 916 fail: 917 if (mdp5_kms) 918 mdp5_destroy(pdev); 919 return ret; 920 } 921 922 static int mdp5_bind(struct device *dev, struct device *master, void *data) 923 { 924 struct msm_drm_private *priv = dev_get_drvdata(master); 925 struct drm_device *ddev = priv->dev; 926 struct platform_device *pdev = to_platform_device(dev); 927 928 DBG(""); 929 930 return mdp5_init(pdev, ddev); 931 } 932 933 static void mdp5_unbind(struct device *dev, struct device *master, 934 void *data) 935 { 936 struct platform_device *pdev = to_platform_device(dev); 937 938 mdp5_destroy(pdev); 939 } 940 941 static const struct component_ops mdp5_ops = { 942 .bind = mdp5_bind, 943 .unbind = mdp5_unbind, 944 }; 945 946 static int mdp5_setup_interconnect(struct platform_device *pdev) 947 { 948 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem"); 949 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem"); 950 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem"); 951 952 if (IS_ERR(path0)) 953 return PTR_ERR(path0); 954 955 if (!path0) { 956 /* no interconnect support is not necessarily a fatal 957 * condition, the platform may simply not have an 958 * interconnect driver yet. But warn about it in case 959 * bootloader didn't setup bus clocks high enough for 960 * scanout. 961 */ 962 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 963 return 0; 964 } 965 966 icc_set_bw(path0, 0, MBps_to_icc(6400)); 967 968 if (!IS_ERR_OR_NULL(path1)) 969 icc_set_bw(path1, 0, MBps_to_icc(6400)); 970 if (!IS_ERR_OR_NULL(path_rot)) 971 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 972 973 return 0; 974 } 975 976 static int mdp5_dev_probe(struct platform_device *pdev) 977 { 978 int ret; 979 980 DBG(""); 981 982 ret = mdp5_setup_interconnect(pdev); 983 if (ret) 984 return ret; 985 986 return component_add(&pdev->dev, &mdp5_ops); 987 } 988 989 static int mdp5_dev_remove(struct platform_device *pdev) 990 { 991 DBG(""); 992 component_del(&pdev->dev, &mdp5_ops); 993 return 0; 994 } 995 996 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 997 { 998 struct platform_device *pdev = to_platform_device(dev); 999 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1000 1001 DBG(""); 1002 1003 return mdp5_disable(mdp5_kms); 1004 } 1005 1006 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 1007 { 1008 struct platform_device *pdev = to_platform_device(dev); 1009 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1010 1011 DBG(""); 1012 1013 return mdp5_enable(mdp5_kms); 1014 } 1015 1016 static const struct dev_pm_ops mdp5_pm_ops = { 1017 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 1018 }; 1019 1020 const struct of_device_id mdp5_dt_match[] = { 1021 { .compatible = "qcom,mdp5", }, 1022 /* to support downstream DT files */ 1023 { .compatible = "qcom,mdss_mdp", }, 1024 {} 1025 }; 1026 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 1027 1028 static struct platform_driver mdp5_driver = { 1029 .probe = mdp5_dev_probe, 1030 .remove = mdp5_dev_remove, 1031 .driver = { 1032 .name = "msm_mdp", 1033 .of_match_table = mdp5_dt_match, 1034 .pm = &mdp5_pm_ops, 1035 }, 1036 }; 1037 1038 void __init msm_mdp_register(void) 1039 { 1040 DBG(""); 1041 platform_driver_register(&mdp5_driver); 1042 } 1043 1044 void __exit msm_mdp_unregister(void) 1045 { 1046 DBG(""); 1047 platform_driver_unregister(&mdp5_driver); 1048 } 1049