1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static int mdp5_set_split_display(struct msm_kms *kms, 194 struct drm_encoder *encoder, 195 struct drm_encoder *slave_encoder, 196 bool is_cmd_mode) 197 { 198 if (is_cmd_mode) 199 return mdp5_cmd_encoder_set_split_display(encoder, 200 slave_encoder); 201 else 202 return mdp5_vid_encoder_set_split_display(encoder, 203 slave_encoder); 204 } 205 206 static void mdp5_destroy(struct mdp5_kms *mdp5_kms); 207 208 static void mdp5_kms_destroy(struct msm_kms *kms) 209 { 210 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 211 struct msm_gem_address_space *aspace = kms->aspace; 212 213 if (aspace) { 214 aspace->mmu->funcs->detach(aspace->mmu); 215 msm_gem_address_space_put(aspace); 216 } 217 218 mdp_kms_destroy(&mdp5_kms->base); 219 mdp5_destroy(mdp5_kms); 220 } 221 222 #ifdef CONFIG_DEBUG_FS 223 static int smp_show(struct seq_file *m, void *arg) 224 { 225 struct drm_info_node *node = m->private; 226 struct drm_device *dev = node->minor->dev; 227 struct msm_drm_private *priv = dev->dev_private; 228 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 229 struct drm_printer p = drm_seq_file_printer(m); 230 231 if (!mdp5_kms->smp) { 232 drm_printf(&p, "no SMP pool\n"); 233 return 0; 234 } 235 236 mdp5_smp_dump(mdp5_kms->smp, &p); 237 238 return 0; 239 } 240 241 static struct drm_info_list mdp5_debugfs_list[] = { 242 {"smp", smp_show }, 243 }; 244 245 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 246 { 247 drm_debugfs_create_files(mdp5_debugfs_list, 248 ARRAY_SIZE(mdp5_debugfs_list), 249 minor->debugfs_root, minor); 250 251 return 0; 252 } 253 #endif 254 255 static const struct mdp_kms_funcs kms_funcs = { 256 .base = { 257 .hw_init = mdp5_hw_init, 258 .irq_preinstall = mdp5_irq_preinstall, 259 .irq_postinstall = mdp5_irq_postinstall, 260 .irq_uninstall = mdp5_irq_uninstall, 261 .irq = mdp5_irq, 262 .enable_vblank = mdp5_enable_vblank, 263 .disable_vblank = mdp5_disable_vblank, 264 .flush_commit = mdp5_flush_commit, 265 .enable_commit = mdp5_enable_commit, 266 .disable_commit = mdp5_disable_commit, 267 .prepare_commit = mdp5_prepare_commit, 268 .wait_flush = mdp5_wait_flush, 269 .complete_commit = mdp5_complete_commit, 270 .get_format = mdp_get_format, 271 .set_split_display = mdp5_set_split_display, 272 .destroy = mdp5_kms_destroy, 273 #ifdef CONFIG_DEBUG_FS 274 .debugfs_init = mdp5_kms_debugfs_init, 275 #endif 276 }, 277 .set_irqmask = mdp5_set_irqmask, 278 }; 279 280 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 281 { 282 DBG(""); 283 284 mdp5_kms->enable_count--; 285 WARN_ON(mdp5_kms->enable_count < 0); 286 287 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 288 clk_disable_unprepare(mdp5_kms->tbu_clk); 289 clk_disable_unprepare(mdp5_kms->ahb_clk); 290 clk_disable_unprepare(mdp5_kms->axi_clk); 291 clk_disable_unprepare(mdp5_kms->core_clk); 292 clk_disable_unprepare(mdp5_kms->lut_clk); 293 294 return 0; 295 } 296 297 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 298 { 299 DBG(""); 300 301 mdp5_kms->enable_count++; 302 303 clk_prepare_enable(mdp5_kms->ahb_clk); 304 clk_prepare_enable(mdp5_kms->axi_clk); 305 clk_prepare_enable(mdp5_kms->core_clk); 306 clk_prepare_enable(mdp5_kms->lut_clk); 307 clk_prepare_enable(mdp5_kms->tbu_clk); 308 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 309 310 return 0; 311 } 312 313 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 314 struct mdp5_interface *intf, 315 struct mdp5_ctl *ctl) 316 { 317 struct drm_device *dev = mdp5_kms->dev; 318 struct drm_encoder *encoder; 319 320 encoder = mdp5_encoder_init(dev, intf, ctl); 321 if (IS_ERR(encoder)) { 322 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 323 return encoder; 324 } 325 326 return encoder; 327 } 328 329 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 330 { 331 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 332 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 333 int id = 0, i; 334 335 for (i = 0; i < intf_cnt; i++) { 336 if (intfs[i] == INTF_DSI) { 337 if (intf_num == i) 338 return id; 339 340 id++; 341 } 342 } 343 344 return -EINVAL; 345 } 346 347 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 348 struct mdp5_interface *intf) 349 { 350 struct drm_device *dev = mdp5_kms->dev; 351 struct msm_drm_private *priv = dev->dev_private; 352 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 353 struct mdp5_ctl *ctl; 354 struct drm_encoder *encoder; 355 int ret = 0; 356 357 switch (intf->type) { 358 case INTF_eDP: 359 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); 360 break; 361 case INTF_HDMI: 362 if (!priv->hdmi) 363 break; 364 365 ctl = mdp5_ctlm_request(ctlm, intf->num); 366 if (!ctl) { 367 ret = -EINVAL; 368 break; 369 } 370 371 encoder = construct_encoder(mdp5_kms, intf, ctl); 372 if (IS_ERR(encoder)) { 373 ret = PTR_ERR(encoder); 374 break; 375 } 376 377 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 378 break; 379 case INTF_DSI: 380 { 381 const struct mdp5_cfg_hw *hw_cfg = 382 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 383 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 384 385 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 386 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 387 intf->num); 388 ret = -EINVAL; 389 break; 390 } 391 392 if (!priv->dsi[dsi_id]) 393 break; 394 395 ctl = mdp5_ctlm_request(ctlm, intf->num); 396 if (!ctl) { 397 ret = -EINVAL; 398 break; 399 } 400 401 encoder = construct_encoder(mdp5_kms, intf, ctl); 402 if (IS_ERR(encoder)) { 403 ret = PTR_ERR(encoder); 404 break; 405 } 406 407 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 408 if (!ret) 409 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id])); 410 411 break; 412 } 413 default: 414 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 415 ret = -EINVAL; 416 break; 417 } 418 419 return ret; 420 } 421 422 static int modeset_init(struct mdp5_kms *mdp5_kms) 423 { 424 struct drm_device *dev = mdp5_kms->dev; 425 struct msm_drm_private *priv = dev->dev_private; 426 unsigned int num_crtcs; 427 int i, ret, pi = 0, ci = 0; 428 struct drm_plane *primary[MAX_BASES] = { NULL }; 429 struct drm_plane *cursor[MAX_BASES] = { NULL }; 430 struct drm_encoder *encoder; 431 unsigned int num_encoders; 432 433 /* 434 * Construct encoders and modeset initialize connector devices 435 * for each external display interface. 436 */ 437 for (i = 0; i < mdp5_kms->num_intfs; i++) { 438 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 439 if (ret) 440 goto fail; 441 } 442 443 num_encoders = 0; 444 drm_for_each_encoder(encoder, dev) 445 num_encoders++; 446 447 /* 448 * We should ideally have less number of encoders (set up by parsing 449 * the MDP5 interfaces) than the number of layer mixers present in HW, 450 * but let's be safe here anyway 451 */ 452 num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers); 453 454 /* 455 * Construct planes equaling the number of hw pipes, and CRTCs for the 456 * N encoders set up by the driver. The first N planes become primary 457 * planes for the CRTCs, with the remainder as overlay planes: 458 */ 459 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 460 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 461 struct drm_plane *plane; 462 enum drm_plane_type type; 463 464 if (i < num_crtcs) 465 type = DRM_PLANE_TYPE_PRIMARY; 466 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 467 type = DRM_PLANE_TYPE_CURSOR; 468 else 469 type = DRM_PLANE_TYPE_OVERLAY; 470 471 plane = mdp5_plane_init(dev, type); 472 if (IS_ERR(plane)) { 473 ret = PTR_ERR(plane); 474 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 475 goto fail; 476 } 477 478 if (type == DRM_PLANE_TYPE_PRIMARY) 479 primary[pi++] = plane; 480 if (type == DRM_PLANE_TYPE_CURSOR) 481 cursor[ci++] = plane; 482 } 483 484 for (i = 0; i < num_crtcs; i++) { 485 struct drm_crtc *crtc; 486 487 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 488 if (IS_ERR(crtc)) { 489 ret = PTR_ERR(crtc); 490 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 491 goto fail; 492 } 493 priv->num_crtcs++; 494 } 495 496 /* 497 * Now that we know the number of crtcs we've created, set the possible 498 * crtcs for the encoders 499 */ 500 drm_for_each_encoder(encoder, dev) 501 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 502 503 return 0; 504 505 fail: 506 return ret; 507 } 508 509 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 510 u32 *major, u32 *minor) 511 { 512 struct device *dev = &mdp5_kms->pdev->dev; 513 u32 version; 514 515 pm_runtime_get_sync(dev); 516 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 517 pm_runtime_put_sync(dev); 518 519 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 520 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 521 522 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 523 } 524 525 static int get_clk(struct platform_device *pdev, struct clk **clkp, 526 const char *name, bool mandatory) 527 { 528 struct device *dev = &pdev->dev; 529 struct clk *clk = msm_clk_get(pdev, name); 530 if (IS_ERR(clk) && mandatory) { 531 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 532 return PTR_ERR(clk); 533 } 534 if (IS_ERR(clk)) 535 DBG("skipping %s", name); 536 else 537 *clkp = clk; 538 539 return 0; 540 } 541 542 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev); 543 544 static int mdp5_kms_init(struct drm_device *dev) 545 { 546 struct msm_drm_private *priv = dev->dev_private; 547 struct platform_device *pdev; 548 struct mdp5_kms *mdp5_kms; 549 struct mdp5_cfg *config; 550 struct msm_kms *kms = priv->kms; 551 struct msm_gem_address_space *aspace; 552 int i, ret; 553 554 ret = mdp5_init(to_platform_device(dev->dev), dev); 555 if (ret) 556 return ret; 557 558 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 559 560 pdev = mdp5_kms->pdev; 561 562 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 563 if (ret) { 564 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 565 goto fail; 566 } 567 568 config = mdp5_cfg_get_config(mdp5_kms->cfg); 569 570 /* make sure things are off before attaching iommu (bootloader could 571 * have left things on, in which case we'll start getting faults if 572 * we don't disable): 573 */ 574 pm_runtime_get_sync(&pdev->dev); 575 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 576 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 577 !config->hw->intf.base[i]) 578 continue; 579 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 580 581 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 582 } 583 mdelay(16); 584 585 aspace = msm_kms_init_aspace(mdp5_kms->dev); 586 if (IS_ERR(aspace)) { 587 ret = PTR_ERR(aspace); 588 goto fail; 589 } 590 591 kms->aspace = aspace; 592 593 pm_runtime_put_sync(&pdev->dev); 594 595 ret = modeset_init(mdp5_kms); 596 if (ret) { 597 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 598 goto fail; 599 } 600 601 dev->mode_config.min_width = 0; 602 dev->mode_config.min_height = 0; 603 dev->mode_config.max_width = 0xffff; 604 dev->mode_config.max_height = 0xffff; 605 606 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 607 dev->vblank_disable_immediate = true; 608 609 return 0; 610 fail: 611 if (kms) 612 mdp5_kms_destroy(kms); 613 614 return ret; 615 } 616 617 static void mdp5_destroy(struct mdp5_kms *mdp5_kms) 618 { 619 if (mdp5_kms->rpm_enabled) 620 pm_runtime_disable(&mdp5_kms->pdev->dev); 621 622 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 623 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 624 } 625 626 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 627 const enum mdp5_pipe *pipes, const uint32_t *offsets, 628 uint32_t caps) 629 { 630 struct drm_device *dev = mdp5_kms->dev; 631 int i, ret; 632 633 for (i = 0; i < cnt; i++) { 634 struct mdp5_hw_pipe *hwpipe; 635 636 hwpipe = mdp5_pipe_init(dev, pipes[i], offsets[i], caps); 637 if (IS_ERR(hwpipe)) { 638 ret = PTR_ERR(hwpipe); 639 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 640 pipe2name(pipes[i]), ret); 641 return ret; 642 } 643 hwpipe->idx = mdp5_kms->num_hwpipes; 644 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 645 } 646 647 return 0; 648 } 649 650 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 651 { 652 static const enum mdp5_pipe rgb_planes[] = { 653 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 654 }; 655 static const enum mdp5_pipe vig_planes[] = { 656 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 657 }; 658 static const enum mdp5_pipe dma_planes[] = { 659 SSPP_DMA0, SSPP_DMA1, 660 }; 661 static const enum mdp5_pipe cursor_planes[] = { 662 SSPP_CURSOR0, SSPP_CURSOR1, 663 }; 664 const struct mdp5_cfg_hw *hw_cfg; 665 int ret; 666 667 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 668 669 /* Construct RGB pipes: */ 670 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 671 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 672 if (ret) 673 return ret; 674 675 /* Construct video (VIG) pipes: */ 676 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 677 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 678 if (ret) 679 return ret; 680 681 /* Construct DMA pipes: */ 682 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 683 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 684 if (ret) 685 return ret; 686 687 /* Construct cursor pipes: */ 688 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 689 cursor_planes, hw_cfg->pipe_cursor.base, 690 hw_cfg->pipe_cursor.caps); 691 if (ret) 692 return ret; 693 694 return 0; 695 } 696 697 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 698 { 699 struct drm_device *dev = mdp5_kms->dev; 700 const struct mdp5_cfg_hw *hw_cfg; 701 int i, ret; 702 703 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 704 705 for (i = 0; i < hw_cfg->lm.count; i++) { 706 struct mdp5_hw_mixer *mixer; 707 708 mixer = mdp5_mixer_init(dev, &hw_cfg->lm.instances[i]); 709 if (IS_ERR(mixer)) { 710 ret = PTR_ERR(mixer); 711 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 712 i, ret); 713 return ret; 714 } 715 716 mixer->idx = mdp5_kms->num_hwmixers; 717 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 718 } 719 720 return 0; 721 } 722 723 static int interface_init(struct mdp5_kms *mdp5_kms) 724 { 725 struct drm_device *dev = mdp5_kms->dev; 726 const struct mdp5_cfg_hw *hw_cfg; 727 const enum mdp5_intf_type *intf_types; 728 int i; 729 730 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 731 intf_types = hw_cfg->intf.connect; 732 733 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 734 struct mdp5_interface *intf; 735 736 if (intf_types[i] == INTF_DISABLED) 737 continue; 738 739 intf = devm_kzalloc(dev->dev, sizeof(*intf), GFP_KERNEL); 740 if (!intf) { 741 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 742 return -ENOMEM; 743 } 744 745 intf->num = i; 746 intf->type = intf_types[i]; 747 intf->mode = MDP5_INTF_MODE_NONE; 748 intf->idx = mdp5_kms->num_intfs; 749 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 750 } 751 752 return 0; 753 } 754 755 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 756 { 757 struct msm_drm_private *priv = dev->dev_private; 758 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 759 struct mdp5_cfg *config; 760 u32 major, minor; 761 int ret; 762 763 mdp5_kms->dev = dev; 764 765 ret = mdp5_global_obj_init(mdp5_kms); 766 if (ret) 767 goto fail; 768 769 /* we need to set a default rate before enabling. Set a safe 770 * rate first, then figure out hw revision, and then set a 771 * more optimal rate: 772 */ 773 clk_set_rate(mdp5_kms->core_clk, 200000000); 774 775 pm_runtime_enable(&pdev->dev); 776 mdp5_kms->rpm_enabled = true; 777 778 read_mdp_hw_revision(mdp5_kms, &major, &minor); 779 780 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 781 if (IS_ERR(mdp5_kms->cfg)) { 782 ret = PTR_ERR(mdp5_kms->cfg); 783 mdp5_kms->cfg = NULL; 784 goto fail; 785 } 786 787 config = mdp5_cfg_get_config(mdp5_kms->cfg); 788 mdp5_kms->caps = config->hw->mdp.caps; 789 790 /* TODO: compute core clock rate at runtime */ 791 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 792 793 /* 794 * Some chipsets have a Shared Memory Pool (SMP), while others 795 * have dedicated latency buffering per source pipe instead; 796 * this section initializes the SMP: 797 */ 798 if (mdp5_kms->caps & MDP_CAP_SMP) { 799 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 800 if (IS_ERR(mdp5_kms->smp)) { 801 ret = PTR_ERR(mdp5_kms->smp); 802 mdp5_kms->smp = NULL; 803 goto fail; 804 } 805 } 806 807 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 808 if (IS_ERR(mdp5_kms->ctlm)) { 809 ret = PTR_ERR(mdp5_kms->ctlm); 810 mdp5_kms->ctlm = NULL; 811 goto fail; 812 } 813 814 ret = hwpipe_init(mdp5_kms); 815 if (ret) 816 goto fail; 817 818 ret = hwmixer_init(mdp5_kms); 819 if (ret) 820 goto fail; 821 822 ret = interface_init(mdp5_kms); 823 if (ret) 824 goto fail; 825 826 return 0; 827 fail: 828 mdp5_destroy(mdp5_kms); 829 return ret; 830 } 831 832 static int mdp5_setup_interconnect(struct platform_device *pdev) 833 { 834 struct icc_path *path0 = msm_icc_get(&pdev->dev, "mdp0-mem"); 835 struct icc_path *path1 = msm_icc_get(&pdev->dev, "mdp1-mem"); 836 struct icc_path *path_rot = msm_icc_get(&pdev->dev, "rotator-mem"); 837 838 if (IS_ERR(path0)) 839 return PTR_ERR(path0); 840 841 if (!path0) { 842 /* no interconnect support is not necessarily a fatal 843 * condition, the platform may simply not have an 844 * interconnect driver yet. But warn about it in case 845 * bootloader didn't setup bus clocks high enough for 846 * scanout. 847 */ 848 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 849 return 0; 850 } 851 852 icc_set_bw(path0, 0, MBps_to_icc(6400)); 853 854 if (!IS_ERR_OR_NULL(path1)) 855 icc_set_bw(path1, 0, MBps_to_icc(6400)); 856 if (!IS_ERR_OR_NULL(path_rot)) 857 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 858 859 return 0; 860 } 861 862 static int mdp5_dev_probe(struct platform_device *pdev) 863 { 864 struct mdp5_kms *mdp5_kms; 865 int ret, irq; 866 867 DBG(""); 868 869 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 870 if (!mdp5_kms) 871 return -ENOMEM; 872 873 ret = mdp5_setup_interconnect(pdev); 874 if (ret) 875 return ret; 876 877 mdp5_kms->pdev = pdev; 878 879 spin_lock_init(&mdp5_kms->resource_lock); 880 881 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys"); 882 if (IS_ERR(mdp5_kms->mmio)) 883 return PTR_ERR(mdp5_kms->mmio); 884 885 /* mandatory clocks: */ 886 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 887 if (ret) 888 return ret; 889 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 890 if (ret) 891 return ret; 892 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 893 if (ret) 894 return ret; 895 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 896 if (ret) 897 return ret; 898 899 /* optional clocks: */ 900 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 901 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 902 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 903 904 irq = platform_get_irq(pdev, 0); 905 if (irq < 0) 906 return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); 907 908 mdp5_kms->base.base.irq = irq; 909 910 return msm_drv_probe(&pdev->dev, mdp5_kms_init, &mdp5_kms->base.base); 911 } 912 913 static void mdp5_dev_remove(struct platform_device *pdev) 914 { 915 DBG(""); 916 component_master_del(&pdev->dev, &msm_drm_ops); 917 } 918 919 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 920 { 921 struct platform_device *pdev = to_platform_device(dev); 922 struct msm_drm_private *priv = platform_get_drvdata(pdev); 923 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 924 925 DBG(""); 926 927 return mdp5_disable(mdp5_kms); 928 } 929 930 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 931 { 932 struct platform_device *pdev = to_platform_device(dev); 933 struct msm_drm_private *priv = platform_get_drvdata(pdev); 934 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 935 936 DBG(""); 937 938 return mdp5_enable(mdp5_kms); 939 } 940 941 static const struct dev_pm_ops mdp5_pm_ops = { 942 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 943 .prepare = msm_kms_pm_prepare, 944 .complete = msm_kms_pm_complete, 945 }; 946 947 static const struct of_device_id mdp5_dt_match[] = { 948 { .compatible = "qcom,mdp5", }, 949 /* to support downstream DT files */ 950 { .compatible = "qcom,mdss_mdp", }, 951 {} 952 }; 953 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 954 955 static struct platform_driver mdp5_driver = { 956 .probe = mdp5_dev_probe, 957 .remove_new = mdp5_dev_remove, 958 .shutdown = msm_kms_shutdown, 959 .driver = { 960 .name = "msm_mdp", 961 .of_match_table = mdp5_dt_match, 962 .pm = &mdp5_pm_ops, 963 }, 964 }; 965 966 void __init msm_mdp_register(void) 967 { 968 DBG(""); 969 platform_driver_register(&mdp5_driver); 970 } 971 972 void __exit msm_mdp_unregister(void) 973 { 974 DBG(""); 975 platform_driver_unregister(&mdp5_driver); 976 } 977