xref: /linux/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include <linux/irq.h>
8 
9 #include <drm/drm_print.h>
10 #include <drm/drm_vblank.h>
11 
12 #include "msm_drv.h"
13 #include "mdp5_kms.h"
14 
15 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
16 		uint32_t old_irqmask)
17 {
18 	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR,
19 		   irqmask ^ (irqmask & old_irqmask));
20 	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
21 }
22 
23 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
24 {
25 	struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler);
26 	static DEFINE_RATELIMIT_STATE(rs, 5*HZ, 1);
27 	extern bool dumpstate;
28 
29 	DRM_ERROR_RATELIMITED("errors: %08x\n", irqstatus);
30 
31 	if (dumpstate && __ratelimit(&rs)) {
32 		struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);
33 		drm_state_dump(mdp5_kms->dev, &p);
34 		if (mdp5_kms->smp)
35 			mdp5_smp_dump(mdp5_kms->smp, &p);
36 	}
37 }
38 
39 void mdp5_irq_preinstall(struct msm_kms *kms)
40 {
41 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
42 	struct device *dev = &mdp5_kms->pdev->dev;
43 
44 	pm_runtime_get_sync(dev);
45 	mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
46 	mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
47 	pm_runtime_put_sync(dev);
48 }
49 
50 int mdp5_irq_postinstall(struct msm_kms *kms)
51 {
52 	struct mdp_kms *mdp_kms = to_mdp_kms(kms);
53 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
54 	struct device *dev = &mdp5_kms->pdev->dev;
55 	struct mdp_irq *error_handler = &mdp5_kms->error_handler;
56 
57 	error_handler->irq = mdp5_irq_error_handler;
58 	error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
59 			MDP5_IRQ_INTF1_UNDER_RUN |
60 			MDP5_IRQ_INTF2_UNDER_RUN |
61 			MDP5_IRQ_INTF3_UNDER_RUN;
62 
63 	pm_runtime_get_sync(dev);
64 	mdp_irq_register(mdp_kms, error_handler);
65 	pm_runtime_put_sync(dev);
66 
67 	return 0;
68 }
69 
70 void mdp5_irq_uninstall(struct msm_kms *kms)
71 {
72 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
73 	struct device *dev = &mdp5_kms->pdev->dev;
74 
75 	pm_runtime_get_sync(dev);
76 	mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
77 	pm_runtime_put_sync(dev);
78 }
79 
80 irqreturn_t mdp5_irq(struct msm_kms *kms)
81 {
82 	struct mdp_kms *mdp_kms = to_mdp_kms(kms);
83 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
84 	struct drm_device *dev = mdp5_kms->dev;
85 	struct drm_crtc *crtc;
86 	uint32_t status, enable;
87 
88 	enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN);
89 	status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable;
90 	mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
91 
92 	VERB("status=%08x", status);
93 
94 	mdp_dispatch_irqs(mdp_kms, status);
95 
96 	drm_for_each_crtc(crtc, dev)
97 		if (status & mdp5_crtc_vblank(crtc))
98 			drm_crtc_handle_vblank(crtc);
99 
100 	return IRQ_HANDLED;
101 }
102 
103 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
104 {
105 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
106 	struct device *dev = &mdp5_kms->pdev->dev;
107 
108 	pm_runtime_get_sync(dev);
109 	mdp_update_vblank_mask(to_mdp_kms(kms),
110 			mdp5_crtc_vblank(crtc), true);
111 	pm_runtime_put_sync(dev);
112 
113 	return 0;
114 }
115 
116 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
117 {
118 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
119 	struct device *dev = &mdp5_kms->pdev->dev;
120 
121 	pm_runtime_get_sync(dev);
122 	mdp_update_vblank_mask(to_mdp_kms(kms),
123 			mdp5_crtc_vblank(crtc), false);
124 	pm_runtime_put_sync(dev);
125 }
126