xref: /linux/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c (revision eed4edda910fe34dfae8c6bfbcf57f4593a54295)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include <linux/irq.h>
8 
9 #include <drm/drm_print.h>
10 #include <drm/drm_vblank.h>
11 
12 #include "msm_drv.h"
13 #include "mdp5_kms.h"
14 
15 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
16 		uint32_t old_irqmask)
17 {
18 	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR,
19 		   irqmask ^ (irqmask & old_irqmask));
20 	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
21 }
22 
23 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
24 {
25 	struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler);
26 	static DEFINE_RATELIMIT_STATE(rs, 5*HZ, 1);
27 	extern bool dumpstate;
28 
29 	DRM_ERROR_RATELIMITED("errors: %08x\n", irqstatus);
30 
31 	if (dumpstate && __ratelimit(&rs)) {
32 		struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);
33 		drm_state_dump(mdp5_kms->dev, &p);
34 	}
35 }
36 
37 void mdp5_irq_preinstall(struct msm_kms *kms)
38 {
39 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
40 	struct device *dev = &mdp5_kms->pdev->dev;
41 
42 	pm_runtime_get_sync(dev);
43 	mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
44 	mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
45 	pm_runtime_put_sync(dev);
46 }
47 
48 int mdp5_irq_postinstall(struct msm_kms *kms)
49 {
50 	struct mdp_kms *mdp_kms = to_mdp_kms(kms);
51 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
52 	struct device *dev = &mdp5_kms->pdev->dev;
53 	struct mdp_irq *error_handler = &mdp5_kms->error_handler;
54 
55 	error_handler->irq = mdp5_irq_error_handler;
56 	error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
57 			MDP5_IRQ_INTF1_UNDER_RUN |
58 			MDP5_IRQ_INTF2_UNDER_RUN |
59 			MDP5_IRQ_INTF3_UNDER_RUN;
60 
61 	pm_runtime_get_sync(dev);
62 	mdp_irq_register(mdp_kms, error_handler);
63 	pm_runtime_put_sync(dev);
64 
65 	return 0;
66 }
67 
68 void mdp5_irq_uninstall(struct msm_kms *kms)
69 {
70 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
71 	struct device *dev = &mdp5_kms->pdev->dev;
72 
73 	pm_runtime_get_sync(dev);
74 	mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
75 	pm_runtime_put_sync(dev);
76 }
77 
78 irqreturn_t mdp5_irq(struct msm_kms *kms)
79 {
80 	struct mdp_kms *mdp_kms = to_mdp_kms(kms);
81 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
82 	struct drm_device *dev = mdp5_kms->dev;
83 	struct drm_crtc *crtc;
84 	uint32_t status, enable;
85 
86 	enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN);
87 	status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable;
88 	mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
89 
90 	VERB("status=%08x", status);
91 
92 	mdp_dispatch_irqs(mdp_kms, status);
93 
94 	drm_for_each_crtc(crtc, dev)
95 		if (status & mdp5_crtc_vblank(crtc))
96 			drm_crtc_handle_vblank(crtc);
97 
98 	return IRQ_HANDLED;
99 }
100 
101 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
102 {
103 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
104 	struct device *dev = &mdp5_kms->pdev->dev;
105 
106 	pm_runtime_get_sync(dev);
107 	mdp_update_vblank_mask(to_mdp_kms(kms),
108 			mdp5_crtc_vblank(crtc), true);
109 	pm_runtime_put_sync(dev);
110 
111 	return 0;
112 }
113 
114 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
115 {
116 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
117 	struct device *dev = &mdp5_kms->pdev->dev;
118 
119 	pm_runtime_get_sync(dev);
120 	mdp_update_vblank_mask(to_mdp_kms(kms),
121 			mdp5_crtc_vblank(crtc), false);
122 	pm_runtime_put_sync(dev);
123 }
124