xref: /linux/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __MDP5_CTL_H__
7 #define __MDP5_CTL_H__
8 
9 #include "msm_drv.h"
10 
11 /*
12  * CTL Manager prototypes:
13  * mdp5_ctlm_init() returns a ctlm (CTL Manager) handler,
14  * which is then used to call the other mdp5_ctlm_*(ctlm, ...) functions.
15  */
16 struct mdp5_ctl_manager;
17 struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
18 		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
19 void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
20 
21 /*
22  * CTL prototypes:
23  * mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
24  * which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
25  */
26 struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
27 
28 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
29 
30 struct mdp5_interface;
31 struct mdp5_pipeline;
32 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
33 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
34 			       bool enabled);
35 
36 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
37 			int cursor_id, bool enable);
38 
39 #define MAX_PIPE_STAGE		2
40 
41 /*
42  * mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
43  *
44  * @stage: array to contain the pipe num for each stage
45  * @stage_cnt: valid stage number in stage array
46  * @ctl_blend_op_flags: blender operation mode flags
47  *
48  * Note:
49  * CTL registers need to be flushed after calling this function
50  * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
51  */
52 #define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT	BIT(0)
53 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
54 		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
55 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
56 		   u32 stage_cnt, u32 ctl_blend_op_flags);
57 
58 /**
59  * mdp_ctl_flush_mask...() - Register FLUSH masks
60  *
61  * These masks are used to specify which block(s) need to be flushed
62  * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
63  */
64 u32 mdp_ctl_flush_mask_lm(int lm);
65 u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
66 u32 mdp_ctl_flush_mask_cursor(int cursor_id);
67 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
68 
69 /* @flush_mask: see CTL flush masks definitions below */
70 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
71 		    u32 flush_mask, bool start);
72 u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
73 
74 
75 
76 #endif /* __MDP5_CTL_H__ */
77