xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h (revision 576d7fed09c7edbae7600f29a8a3ed6c1ead904f)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
6 #define _DPU_TRACE_H_
7 
8 #include <linux/stringify.h>
9 #include <linux/types.h>
10 #include <linux/tracepoint.h>
11 
12 #include <drm/drm_rect.h>
13 #include "dpu_crtc.h"
14 #include "dpu_encoder_phys.h"
15 #include "dpu_hw_mdss.h"
16 #include "dpu_hw_vbif.h"
17 #include "dpu_plane.h"
18 
19 #undef TRACE_SYSTEM
20 #define TRACE_SYSTEM dpu
21 #undef TRACE_INCLUDE_FILE
22 #define TRACE_INCLUDE_FILE dpu_trace
23 
24 TRACE_EVENT(dpu_perf_set_qos_luts,
25 	TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
26 		u32 lut, u32 lut_usage),
27 	TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
28 	TP_STRUCT__entry(
29 			__field(u32, pnum)
30 			__field(u32, fmt)
31 			__field(bool, rt)
32 			__field(u32, fl)
33 			__field(u64, lut)
34 			__field(u32, lut_usage)
35 	),
36 	TP_fast_assign(
37 			__entry->pnum = pnum;
38 			__entry->fmt = fmt;
39 			__entry->rt = rt;
40 			__entry->fl = fl;
41 			__entry->lut = lut;
42 			__entry->lut_usage = lut_usage;
43 	),
44 	TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
45 			__entry->pnum, __entry->fmt,
46 			__entry->rt, __entry->fl,
47 			__entry->lut, __entry->lut_usage)
48 );
49 
50 TRACE_EVENT(dpu_perf_set_danger_luts,
51 	TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
52 		u32 safe_lut),
53 	TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
54 	TP_STRUCT__entry(
55 			__field(u32, pnum)
56 			__field(u32, fmt)
57 			__field(u32, mode)
58 			__field(u32, danger_lut)
59 			__field(u32, safe_lut)
60 	),
61 	TP_fast_assign(
62 			__entry->pnum = pnum;
63 			__entry->fmt = fmt;
64 			__entry->mode = mode;
65 			__entry->danger_lut = danger_lut;
66 			__entry->safe_lut = safe_lut;
67 	),
68 	TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
69 			__entry->pnum, __entry->fmt,
70 			__entry->mode, __entry->danger_lut,
71 			__entry->safe_lut)
72 );
73 
74 TRACE_EVENT(dpu_perf_set_ot,
75 	TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
76 	TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
77 	TP_STRUCT__entry(
78 			__field(u32, pnum)
79 			__field(u32, xin_id)
80 			__field(u32, rd_lim)
81 			__field(u32, vbif_idx)
82 	),
83 	TP_fast_assign(
84 			__entry->pnum = pnum;
85 			__entry->xin_id = xin_id;
86 			__entry->rd_lim = rd_lim;
87 			__entry->vbif_idx = vbif_idx;
88 	),
89 	TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
90 			__entry->pnum, __entry->xin_id, __entry->rd_lim,
91 			__entry->vbif_idx)
92 )
93 
94 TRACE_EVENT(dpu_cmd_release_bw,
95 	TP_PROTO(u32 crtc_id),
96 	TP_ARGS(crtc_id),
97 	TP_STRUCT__entry(
98 			__field(u32, crtc_id)
99 	),
100 	TP_fast_assign(
101 			__entry->crtc_id = crtc_id;
102 	),
103 	TP_printk("crtc:%d", __entry->crtc_id)
104 );
105 
106 TRACE_EVENT(tracing_mark_write,
107 	TP_PROTO(int pid, const char *name, bool trace_begin),
108 	TP_ARGS(pid, name, trace_begin),
109 	TP_STRUCT__entry(
110 			__field(int, pid)
111 			__string(trace_name, name)
112 			__field(bool, trace_begin)
113 	),
114 	TP_fast_assign(
115 			__entry->pid = pid;
116 			__assign_str(trace_name, name);
117 			__entry->trace_begin = trace_begin;
118 	),
119 	TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
120 		__entry->pid, __get_str(trace_name))
121 )
122 
123 TRACE_EVENT(dpu_trace_counter,
124 	TP_PROTO(int pid, char *name, int value),
125 	TP_ARGS(pid, name, value),
126 	TP_STRUCT__entry(
127 			__field(int, pid)
128 			__string(counter_name, name)
129 			__field(int, value)
130 	),
131 	TP_fast_assign(
132 			__entry->pid = current->tgid;
133 			__assign_str(counter_name, name);
134 			__entry->value = value;
135 	),
136 	TP_printk("%d|%s|%d", __entry->pid,
137 			__get_str(counter_name), __entry->value)
138 )
139 
140 TRACE_EVENT(dpu_perf_crtc_update,
141 	TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate,
142 			bool stop_req, bool update_bus, bool update_clk),
143 	TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk),
144 	TP_STRUCT__entry(
145 			__field(u32, crtc)
146 			__field(u64, bw_ctl)
147 			__field(u32, core_clk_rate)
148 			__field(bool, stop_req)
149 			__field(u32, update_bus)
150 			__field(u32, update_clk)
151 	),
152 	TP_fast_assign(
153 			__entry->crtc = crtc;
154 			__entry->bw_ctl = bw_ctl;
155 			__entry->core_clk_rate = core_clk_rate;
156 			__entry->stop_req = stop_req;
157 			__entry->update_bus = update_bus;
158 			__entry->update_clk = update_clk;
159 	),
160 	 TP_printk(
161 		"crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
162 			__entry->crtc,
163 			__entry->bw_ctl,
164 			__entry->core_clk_rate,
165 			__entry->stop_req,
166 			__entry->update_bus,
167 			__entry->update_clk)
168 );
169 
170 DECLARE_EVENT_CLASS(dpu_irq_template,
171 	TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
172 	TP_ARGS(irq_reg, irq_bit),
173 	TP_STRUCT__entry(
174 		__field(	unsigned int,		irq_reg		)
175 		__field(	unsigned int,		irq_bit		)
176 	),
177 	TP_fast_assign(
178 		__entry->irq_reg = irq_reg;
179 		__entry->irq_bit = irq_bit;
180 	),
181 	TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
182 );
183 DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success,
184 	TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
185 	TP_ARGS(irq_reg, irq_bit)
186 );
187 DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success,
188 	TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
189 	TP_ARGS(irq_reg, irq_bit)
190 );
191 
192 TRACE_EVENT(dpu_enc_irq_wait_success,
193 	TP_PROTO(uint32_t drm_id, void *func,
194 		 unsigned int irq_reg, unsigned int irq_bit, enum dpu_pingpong pp_idx, int atomic_cnt),
195 	TP_ARGS(drm_id, func, irq_reg, irq_bit, pp_idx, atomic_cnt),
196 	TP_STRUCT__entry(
197 		__field(	uint32_t,		drm_id		)
198 		__field(	void *,			func		)
199 		__field(	unsigned int,		irq_reg		)
200 		__field(	unsigned int,		irq_bit		)
201 		__field(	enum dpu_pingpong,	pp_idx		)
202 		__field(	int,			atomic_cnt	)
203 	),
204 	TP_fast_assign(
205 		__entry->drm_id = drm_id;
206 		__entry->func = func;
207 		__entry->irq_reg = irq_reg;
208 		__entry->irq_bit = irq_bit;
209 		__entry->pp_idx = pp_idx;
210 		__entry->atomic_cnt = atomic_cnt;
211 	),
212 	TP_printk("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d",
213 		  __entry->drm_id, __entry->func,
214 		  __entry->irq_reg, __entry->irq_bit, __entry->pp_idx, __entry->atomic_cnt)
215 );
216 
217 DECLARE_EVENT_CLASS(dpu_drm_obj_template,
218 	TP_PROTO(uint32_t drm_id),
219 	TP_ARGS(drm_id),
220 	TP_STRUCT__entry(
221 		__field(	uint32_t,		drm_id		)
222 	),
223 	TP_fast_assign(
224 		__entry->drm_id = drm_id;
225 	),
226 	TP_printk("id=%u", __entry->drm_id)
227 );
228 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
229 	TP_PROTO(uint32_t drm_id),
230 	TP_ARGS(drm_id)
231 );
232 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
233 	TP_PROTO(uint32_t drm_id),
234 	TP_ARGS(drm_id)
235 );
236 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
237 	TP_PROTO(uint32_t drm_id),
238 	TP_ARGS(drm_id)
239 );
240 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
241 	TP_PROTO(uint32_t drm_id),
242 	TP_ARGS(drm_id)
243 );
244 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
245 	TP_PROTO(uint32_t drm_id),
246 	TP_ARGS(drm_id)
247 );
248 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
249 	TP_PROTO(uint32_t drm_id),
250 	TP_ARGS(drm_id)
251 );
252 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
253 	TP_PROTO(uint32_t drm_id),
254 	TP_ARGS(drm_id)
255 );
256 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
257 	TP_PROTO(uint32_t drm_id),
258 	TP_ARGS(drm_id)
259 );
260 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
261 	TP_PROTO(uint32_t drm_id),
262 	TP_ARGS(drm_id)
263 );
264 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
265 	TP_PROTO(uint32_t drm_id),
266 	TP_ARGS(drm_id)
267 );
268 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
269 	TP_PROTO(uint32_t drm_id),
270 	TP_ARGS(drm_id)
271 );
272 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
273 	TP_PROTO(uint32_t drm_id),
274 	TP_ARGS(drm_id)
275 );
276 
277 TRACE_EVENT(dpu_enc_enable,
278 	TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
279 	TP_ARGS(drm_id, hdisplay, vdisplay),
280 	TP_STRUCT__entry(
281 		__field(	uint32_t,		drm_id		)
282 		__field(	int,			hdisplay	)
283 		__field(	int,			vdisplay	)
284 	),
285 	TP_fast_assign(
286 		__entry->drm_id = drm_id;
287 		__entry->hdisplay = hdisplay;
288 		__entry->vdisplay = vdisplay;
289 	),
290 	TP_printk("id=%u, mode=%dx%d",
291 		  __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
292 );
293 
294 DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
295 	TP_PROTO(uint32_t drm_id, int val),
296 	TP_ARGS(drm_id, val),
297 	TP_STRUCT__entry(
298 		__field(	uint32_t,	drm_id	)
299 		__field(	int,		val	)
300 	),
301 	TP_fast_assign(
302 		__entry->drm_id = drm_id;
303 		__entry->val = val;
304 	),
305 	TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
306 );
307 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
308 	TP_PROTO(uint32_t drm_id, int count),
309 	TP_ARGS(drm_id, count)
310 );
311 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
312 	TP_PROTO(uint32_t drm_id, int ctl_idx),
313 	TP_ARGS(drm_id, ctl_idx)
314 );
315 
316 TRACE_EVENT(dpu_enc_atomic_check_flags,
317 	TP_PROTO(uint32_t drm_id, unsigned int flags),
318 	TP_ARGS(drm_id, flags),
319 	TP_STRUCT__entry(
320 		__field(	uint32_t,		drm_id		)
321 		__field(	unsigned int,		flags		)
322 	),
323 	TP_fast_assign(
324 		__entry->drm_id = drm_id;
325 		__entry->flags = flags;
326 	),
327 	TP_printk("id=%u, flags=%u",
328 		  __entry->drm_id, __entry->flags)
329 );
330 
331 DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
332 	TP_PROTO(uint32_t drm_id, bool enable),
333 	TP_ARGS(drm_id, enable),
334 	TP_STRUCT__entry(
335 		__field(	uint32_t,		drm_id		)
336 		__field(	bool,			enable		)
337 	),
338 	TP_fast_assign(
339 		__entry->drm_id = drm_id;
340 		__entry->enable = enable;
341 	),
342 	TP_printk("id=%u, enable=%s",
343 		  __entry->drm_id, __entry->enable ? "true" : "false")
344 );
345 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
346 	TP_PROTO(uint32_t drm_id, bool enable),
347 	TP_ARGS(drm_id, enable)
348 );
349 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
350 	TP_PROTO(uint32_t drm_id, bool enable),
351 	TP_ARGS(drm_id, enable)
352 );
353 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
354 	TP_PROTO(uint32_t drm_id, bool enable),
355 	TP_ARGS(drm_id, enable)
356 );
357 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
358 	TP_PROTO(uint32_t drm_id, bool enable),
359 	TP_ARGS(drm_id, enable)
360 );
361 
362 TRACE_EVENT(dpu_enc_rc,
363 	TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
364 		 int rc_state, const char *stage),
365 	TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
366 	TP_STRUCT__entry(
367 		__field(	uint32_t,	drm_id			)
368 		__field(	u32,		sw_event		)
369 		__field(	bool,		idle_pc_supported	)
370 		__field(	int,		rc_state		)
371 		__string(	stage_str,	stage			)
372 	),
373 	TP_fast_assign(
374 		__entry->drm_id = drm_id;
375 		__entry->sw_event = sw_event;
376 		__entry->idle_pc_supported = idle_pc_supported;
377 		__entry->rc_state = rc_state;
378 		__assign_str(stage_str, stage);
379 	),
380 	TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d",
381 		  __get_str(stage_str), __entry->drm_id, __entry->sw_event,
382 		  __entry->idle_pc_supported ? "true" : "false",
383 		  __entry->rc_state)
384 );
385 
386 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
387 	TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf intf_idx,
388 			enum dpu_wb wb_idx),
389 	TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
390 	TP_STRUCT__entry(
391 		__field(	uint32_t,	drm_id		)
392 		__field(	u32,		event		)
393 		__string(	intf_mode_str,	intf_mode	)
394 		__field(	enum dpu_intf,	intf_idx	)
395 		__field(	enum dpu_wb,	wb_idx		)
396 	),
397 	TP_fast_assign(
398 		__entry->drm_id = drm_id;
399 		__entry->event = event;
400 		__assign_str(intf_mode_str, intf_mode);
401 		__entry->intf_idx = intf_idx;
402 		__entry->wb_idx = wb_idx;
403 	),
404 	TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", __entry->drm_id,
405 			__entry->event, __get_str(intf_mode_str),
406 			__entry->intf_idx, __entry->wb_idx)
407 );
408 
409 TRACE_EVENT(dpu_enc_frame_done_cb,
410 	TP_PROTO(uint32_t drm_id, unsigned int idx,
411 		 unsigned long frame_busy_mask),
412 	TP_ARGS(drm_id, idx, frame_busy_mask),
413 	TP_STRUCT__entry(
414 		__field(	uint32_t,		drm_id		)
415 		__field(	unsigned int,		idx		)
416 		__field(	unsigned long,		frame_busy_mask	)
417 	),
418 	TP_fast_assign(
419 		__entry->drm_id = drm_id;
420 		__entry->idx = idx;
421 		__entry->frame_busy_mask = frame_busy_mask;
422 	),
423 	TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
424 		  __entry->idx, __entry->frame_busy_mask)
425 );
426 
427 TRACE_EVENT(dpu_enc_trigger_flush,
428 	TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum dpu_wb wb_idx,
429 		 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
430 		 u32 pending_flush_ret),
431 	TP_ARGS(drm_id, intf_mode, intf_idx, wb_idx, pending_kickoff_cnt, ctl_idx,
432 		extra_flush_bits, pending_flush_ret),
433 	TP_STRUCT__entry(
434 		__field(	uint32_t,	drm_id			)
435 		__string(	intf_mode_str,	intf_mode		)
436 		__field(	enum dpu_intf,	intf_idx		)
437 		__field(	enum dpu_wb,	wb_idx			)
438 		__field(	int,		pending_kickoff_cnt	)
439 		__field(	int,		ctl_idx			)
440 		__field(	u32,		extra_flush_bits	)
441 		__field(	u32,		pending_flush_ret	)
442 	),
443 	TP_fast_assign(
444 		__entry->drm_id = drm_id;
445 		__assign_str(intf_mode_str, intf_mode);
446 		__entry->intf_idx = intf_idx;
447 		__entry->wb_idx = wb_idx;
448 		__entry->pending_kickoff_cnt = pending_kickoff_cnt;
449 		__entry->ctl_idx = ctl_idx;
450 		__entry->extra_flush_bits = extra_flush_bits;
451 		__entry->pending_flush_ret = pending_flush_ret;
452 	),
453 	TP_printk("id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
454 		  "extra_flush_bits=0x%x pending_flush_ret=0x%x",
455 		  __entry->drm_id, __get_str(intf_mode_str), __entry->intf_idx, __entry->wb_idx,
456 		  __entry->pending_kickoff_cnt, __entry->ctl_idx,
457 		  __entry->extra_flush_bits, __entry->pending_flush_ret)
458 );
459 
460 DECLARE_EVENT_CLASS(dpu_id_event_template,
461 	TP_PROTO(uint32_t drm_id, u32 event),
462 	TP_ARGS(drm_id, event),
463 	TP_STRUCT__entry(
464 		__field(	uint32_t,	drm_id	)
465 		__field(	u32,		event	)
466 	),
467 	TP_fast_assign(
468 		__entry->drm_id = drm_id;
469 		__entry->event = event;
470 	),
471 	TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
472 );
473 DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
474 	TP_PROTO(uint32_t drm_id, u32 event),
475 	TP_ARGS(drm_id, event)
476 );
477 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
478 	TP_PROTO(uint32_t drm_id, u32 event),
479 	TP_ARGS(drm_id, event)
480 );
481 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
482 	TP_PROTO(uint32_t drm_id, u32 event),
483 	TP_ARGS(drm_id, event)
484 );
485 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
486 	TP_PROTO(uint32_t drm_id, u32 event),
487 	TP_ARGS(drm_id, event)
488 );
489 
490 TRACE_EVENT(dpu_enc_wait_event_timeout,
491 	TP_PROTO(uint32_t drm_id, unsigned int irq_reg, unsigned int irq_bit, int rc, s64 time,
492 		 s64 expected_time, int atomic_cnt),
493 	TP_ARGS(drm_id, irq_reg, irq_bit, rc, time, expected_time, atomic_cnt),
494 	TP_STRUCT__entry(
495 		__field(	uint32_t,	drm_id		)
496 		__field(	unsigned int,	irq_reg		)
497 		__field(	unsigned int,	irq_bit		)
498 		__field(	int,		rc		)
499 		__field(	s64,		time		)
500 		__field(	s64,		expected_time	)
501 		__field(	int,		atomic_cnt	)
502 	),
503 	TP_fast_assign(
504 		__entry->drm_id = drm_id;
505 		__entry->irq_reg = irq_reg;
506 		__entry->irq_bit = irq_bit;
507 		__entry->rc = rc;
508 		__entry->time = time;
509 		__entry->expected_time = expected_time;
510 		__entry->atomic_cnt = atomic_cnt;
511 	),
512 	TP_printk("id=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d",
513 		  __entry->drm_id, __entry->irq_reg, __entry->irq_bit, __entry->rc, __entry->time,
514 		  __entry->expected_time, __entry->atomic_cnt)
515 );
516 
517 TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
518 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
519 		 int refcnt),
520 	TP_ARGS(drm_id, pp, enable, refcnt),
521 	TP_STRUCT__entry(
522 		__field(	uint32_t,		drm_id	)
523 		__field(	enum dpu_pingpong,	pp	)
524 		__field(	bool,			enable	)
525 		__field(	int,			refcnt	)
526 	),
527 	TP_fast_assign(
528 		__entry->drm_id = drm_id;
529 		__entry->pp = pp;
530 		__entry->enable = enable;
531 		__entry->refcnt = refcnt;
532 	),
533 	TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
534 		  __entry->pp, __entry->enable ? "true" : "false",
535 		  __entry->refcnt)
536 );
537 
538 TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
539 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
540 		 u32 event),
541 	TP_ARGS(drm_id, pp, new_count, event),
542 	TP_STRUCT__entry(
543 		__field(	uint32_t,		drm_id		)
544 		__field(	enum dpu_pingpong,	pp		)
545 		__field(	int,			new_count	)
546 		__field(	u32,			event		)
547 	),
548 	TP_fast_assign(
549 		__entry->drm_id = drm_id;
550 		__entry->pp = pp;
551 		__entry->new_count = new_count;
552 		__entry->event = event;
553 	),
554 	TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
555 		  __entry->pp, __entry->new_count, __entry->event)
556 );
557 
558 TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
559 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
560 		 int kickoff_count, u32 event),
561 	TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
562 	TP_STRUCT__entry(
563 		__field(	uint32_t,		drm_id		)
564 		__field(	enum dpu_pingpong,	pp		)
565 		__field(	int,			timeout_count	)
566 		__field(	int,			kickoff_count	)
567 		__field(	u32,			event		)
568 	),
569 	TP_fast_assign(
570 		__entry->drm_id = drm_id;
571 		__entry->pp = pp;
572 		__entry->timeout_count = timeout_count;
573 		__entry->kickoff_count = kickoff_count;
574 		__entry->event = event;
575 	),
576 	TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
577 		  __entry->drm_id, __entry->pp, __entry->timeout_count,
578 		  __entry->kickoff_count, __entry->event)
579 );
580 
581 TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
582 	TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
583 	TP_ARGS(drm_id, intf_idx),
584 	TP_STRUCT__entry(
585 		__field(	uint32_t,	drm_id			)
586 		__field(	enum dpu_intf,	intf_idx		)
587 	),
588 	TP_fast_assign(
589 		__entry->drm_id = drm_id;
590 		__entry->intf_idx = intf_idx;
591 	),
592 	TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
593 );
594 
595 TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
596 	TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
597 		 int refcnt),
598 	TP_ARGS(drm_id, intf_idx, enable, refcnt),
599 	TP_STRUCT__entry(
600 		__field(	uint32_t,	drm_id		)
601 		__field(	enum dpu_intf,	intf_idx	)
602 		__field(	bool,		enable		)
603 		__field(	int,		refcnt		)
604 	),
605 	TP_fast_assign(
606 		__entry->drm_id = drm_id;
607 		__entry->intf_idx = intf_idx;
608 		__entry->enable = enable;
609 		__entry->refcnt = refcnt;
610 	),
611 	TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
612 		  __entry->intf_idx, __entry->enable ? "true" : "false",
613 		  __entry->drm_id)
614 );
615 
616 TRACE_EVENT(dpu_crtc_setup_mixer,
617 	TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
618 		 struct drm_plane_state *state, struct dpu_plane_state *pstate,
619 		 uint32_t stage_idx, uint32_t pixel_format,
620 		 uint64_t modifier),
621 	TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
622 		pixel_format, modifier),
623 	TP_STRUCT__entry(
624 		__field(	uint32_t,		crtc_id		)
625 		__field(	uint32_t,		plane_id	)
626 		__field(	uint32_t,		fb_id		)
627 		__field_struct(	struct drm_rect,	src_rect	)
628 		__field_struct(	struct drm_rect,	dst_rect	)
629 		__field(	uint32_t,		stage_idx	)
630 		__field(	enum dpu_stage,		stage		)
631 		__field(	enum dpu_sspp,		sspp		)
632 		__field(	uint32_t,		multirect_idx	)
633 		__field(	uint32_t,		multirect_mode	)
634 		__field(	uint32_t,		pixel_format	)
635 		__field(	uint64_t,		modifier	)
636 	),
637 	TP_fast_assign(
638 		__entry->crtc_id = crtc_id;
639 		__entry->plane_id = plane_id;
640 		__entry->fb_id = state ? state->fb->base.id : 0;
641 		__entry->src_rect = drm_plane_state_src(state);
642 		__entry->dst_rect = drm_plane_state_dest(state);
643 		__entry->stage_idx = stage_idx;
644 		__entry->stage = pstate->stage;
645 		__entry->sspp = pstate->pipe.sspp->idx;
646 		__entry->multirect_idx = pstate->pipe.multirect_index;
647 		__entry->multirect_mode = pstate->pipe.multirect_mode;
648 		__entry->pixel_format = pixel_format;
649 		__entry->modifier = modifier;
650 	),
651 	TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
652 		  " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
653 		  "multirect_index:%d multirect_mode:%u pix_format:%u "
654 		  "modifier:%llu",
655 		  __entry->crtc_id, __entry->plane_id, __entry->fb_id,
656 		  DRM_RECT_FP_ARG(&__entry->src_rect),
657 		  DRM_RECT_ARG(&__entry->dst_rect),
658 		  __entry->stage_idx, __entry->stage, __entry->sspp,
659 		  __entry->multirect_idx, __entry->multirect_mode,
660 		  __entry->pixel_format, __entry->modifier)
661 );
662 
663 TRACE_EVENT(dpu_crtc_setup_lm_bounds,
664 	TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
665 	TP_ARGS(drm_id, mixer, bounds),
666 	TP_STRUCT__entry(
667 		__field(	uint32_t,		drm_id	)
668 		__field(	int,			mixer	)
669 		__field_struct(	struct drm_rect,	bounds	)
670 	),
671 	TP_fast_assign(
672 		__entry->drm_id = drm_id;
673 		__entry->mixer = mixer;
674 		__entry->bounds = *bounds;
675 	),
676 	TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
677 		  __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
678 );
679 
680 TRACE_EVENT(dpu_crtc_vblank_enable,
681 	TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
682 		 struct dpu_crtc *crtc),
683 	TP_ARGS(drm_id, enc_id, enable, crtc),
684 	TP_STRUCT__entry(
685 		__field(	uint32_t,		drm_id	)
686 		__field(	uint32_t,		enc_id	)
687 		__field(	bool,			enable	)
688 		__field(	bool,			enabled )
689 	),
690 	TP_fast_assign(
691 		__entry->drm_id = drm_id;
692 		__entry->enc_id = enc_id;
693 		__entry->enable = enable;
694 		__entry->enabled = crtc->enabled;
695 	),
696 	TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
697 		  __entry->drm_id, __entry->enc_id,
698 		  __entry->enable ? "true" : "false",
699 		  __entry->enabled ? "true" : "false")
700 );
701 
702 DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
703 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
704 	TP_ARGS(drm_id, enable, crtc),
705 	TP_STRUCT__entry(
706 		__field(	uint32_t,		drm_id	)
707 		__field(	bool,			enable	)
708 		__field(	bool,			enabled )
709 	),
710 	TP_fast_assign(
711 		__entry->drm_id = drm_id;
712 		__entry->enable = enable;
713 		__entry->enabled = crtc->enabled;
714 	),
715 	TP_printk("id:%u enable:%s state{enabled:%s}",
716 		  __entry->drm_id, __entry->enable ? "true" : "false",
717 		  __entry->enabled ? "true" : "false")
718 );
719 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
720 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
721 	TP_ARGS(drm_id, enable, crtc)
722 );
723 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
724 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
725 	TP_ARGS(drm_id, enable, crtc)
726 );
727 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
728 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
729 	TP_ARGS(drm_id, enable, crtc)
730 );
731 
732 TRACE_EVENT(dpu_crtc_disable_frame_pending,
733 	TP_PROTO(uint32_t drm_id, int frame_pending),
734 	TP_ARGS(drm_id, frame_pending),
735 	TP_STRUCT__entry(
736 		__field(	uint32_t,		drm_id		)
737 		__field(	int,			frame_pending	)
738 	),
739 	TP_fast_assign(
740 		__entry->drm_id = drm_id;
741 		__entry->frame_pending = frame_pending;
742 	),
743 	TP_printk("id:%u frame_pending:%d", __entry->drm_id,
744 		  __entry->frame_pending)
745 );
746 
747 TRACE_EVENT(dpu_plane_set_scanout,
748 	TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout),
749 	TP_ARGS(pipe, layout),
750 	TP_STRUCT__entry(
751 		__field(	enum dpu_sspp,			index	)
752 		__field_struct(	struct dpu_hw_fmt_layout,	layout	)
753 		__field(	enum dpu_sspp_multirect_index,	multirect_index)
754 	),
755 	TP_fast_assign(
756 		__entry->index = pipe->sspp->idx;
757 		__entry->layout = *layout;
758 		__entry->multirect_index = pipe->multirect_index;
759 	),
760 	TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
761 		  "multirect_index:%d", __entry->index, __entry->layout.width,
762 		  __entry->layout.height, __entry->layout.plane_addr[0],
763 		  __entry->layout.plane_size[0],
764 		  __entry->layout.plane_addr[1],
765 		  __entry->layout.plane_size[1],
766 		  __entry->layout.plane_addr[2],
767 		  __entry->layout.plane_size[2],
768 		  __entry->layout.plane_addr[3],
769 		  __entry->layout.plane_size[3], __entry->multirect_index)
770 );
771 
772 TRACE_EVENT(dpu_plane_disable,
773 	TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
774 	TP_ARGS(drm_id, is_virtual, multirect_mode),
775 	TP_STRUCT__entry(
776 		__field(	uint32_t,		drm_id		)
777 		__field(	bool,			is_virtual	)
778 		__field(	uint32_t,		multirect_mode	)
779 	),
780 	TP_fast_assign(
781 		__entry->drm_id = drm_id;
782 		__entry->is_virtual = is_virtual;
783 		__entry->multirect_mode = multirect_mode;
784 	),
785 	TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
786 		  __entry->is_virtual ? "true" : "false",
787 		  __entry->multirect_mode)
788 );
789 
790 DECLARE_EVENT_CLASS(dpu_rm_iter_template,
791 	TP_PROTO(uint32_t id, uint32_t enc_id),
792 	TP_ARGS(id, enc_id),
793 	TP_STRUCT__entry(
794 		__field(	uint32_t,		id	)
795 		__field(	uint32_t,		enc_id	)
796 	),
797 	TP_fast_assign(
798 		__entry->id = id;
799 		__entry->enc_id = enc_id;
800 	),
801 	TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
802 );
803 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
804 	TP_PROTO(uint32_t id, uint32_t enc_id),
805 	TP_ARGS(id, enc_id)
806 );
807 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
808 	TP_PROTO(uint32_t id, uint32_t enc_id),
809 	TP_ARGS(id, enc_id)
810 );
811 
812 TRACE_EVENT(dpu_rm_reserve_lms,
813 	TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
814 	TP_ARGS(id, enc_id, pp_id),
815 	TP_STRUCT__entry(
816 		__field(	uint32_t,		id	)
817 		__field(	uint32_t,		enc_id	)
818 		__field(	uint32_t,		pp_id	)
819 	),
820 	TP_fast_assign(
821 		__entry->id = id;
822 		__entry->enc_id = enc_id;
823 		__entry->pp_id = pp_id;
824 	),
825 	TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
826 		  __entry->enc_id, __entry->pp_id)
827 );
828 
829 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
830 	TP_PROTO(enum dpu_vbif index, u32 xin_id),
831 	TP_ARGS(index, xin_id),
832 	TP_STRUCT__entry(
833 		__field(	enum dpu_vbif,	index	)
834 		__field(	u32,		xin_id	)
835 	),
836 	TP_fast_assign(
837 		__entry->index = index;
838 		__entry->xin_id = xin_id;
839 	),
840 	TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
841 );
842 
843 TRACE_EVENT(dpu_pp_connect_ext_te,
844 	TP_PROTO(enum dpu_pingpong pp, u32 cfg),
845 	TP_ARGS(pp, cfg),
846 	TP_STRUCT__entry(
847 		__field(	enum dpu_pingpong,	pp	)
848 		__field(	u32,			cfg	)
849 	),
850 	TP_fast_assign(
851 		__entry->pp = pp;
852 		__entry->cfg = cfg;
853 	),
854 	TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
855 );
856 
857 TRACE_EVENT(dpu_intf_connect_ext_te,
858 	TP_PROTO(enum dpu_intf intf, u32 cfg),
859 	TP_ARGS(intf, cfg),
860 	TP_STRUCT__entry(
861 		__field(	enum dpu_intf,	intf	)
862 		__field(	u32,			cfg	)
863 	),
864 	TP_fast_assign(
865 		__entry->intf = intf;
866 		__entry->cfg = cfg;
867 	),
868 	TP_printk("intf:%d cfg:%u", __entry->intf, __entry->cfg)
869 );
870 
871 TRACE_EVENT(dpu_core_irq_register_callback,
872 	TP_PROTO(unsigned int irq_reg, unsigned int irq_bit, void *callback),
873 	TP_ARGS(irq_reg, irq_bit, callback),
874 	TP_STRUCT__entry(
875 		__field(	unsigned int,			irq_reg	)
876 		__field(	unsigned int,			irq_bit	)
877 		__field(	void *,				callback)
878 	),
879 	TP_fast_assign(
880 		__entry->irq_reg = irq_reg;
881 		__entry->irq_bit = irq_bit;
882 		__entry->callback = callback;
883 	),
884 	TP_printk("IRQ=[%d, %d] callback:%ps", __entry->irq_reg, __entry->irq_bit,
885 		  __entry->callback)
886 );
887 
888 TRACE_EVENT(dpu_core_irq_unregister_callback,
889 	TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
890 	TP_ARGS(irq_reg, irq_bit),
891 	TP_STRUCT__entry(
892 		__field(	unsigned int,			irq_reg	)
893 		__field(	unsigned int,			irq_bit	)
894 	),
895 	TP_fast_assign(
896 		__entry->irq_reg = irq_reg;
897 		__entry->irq_bit = irq_bit;
898 	),
899 	TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
900 );
901 
902 TRACE_EVENT(dpu_core_perf_update_clk,
903 	TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
904 	TP_ARGS(dev, stop_req, clk_rate),
905 	TP_STRUCT__entry(
906 		__string(	dev_name,		dev->unique	)
907 		__field(	bool,			stop_req	)
908 		__field(	u64,			clk_rate	)
909 	),
910 	TP_fast_assign(
911 		__assign_str(dev_name, dev->unique);
912 		__entry->stop_req = stop_req;
913 		__entry->clk_rate = clk_rate;
914 	),
915 	TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
916 		  __entry->stop_req ? "true" : "false", __entry->clk_rate)
917 );
918 
919 TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
920 	TP_PROTO(u32 new_bits, u32 pending_mask),
921 	TP_ARGS(new_bits, pending_mask),
922 	TP_STRUCT__entry(
923 		__field(	u32,			new_bits	)
924 		__field(	u32,			pending_mask	)
925 	),
926 	TP_fast_assign(
927 		__entry->new_bits = new_bits;
928 		__entry->pending_mask = pending_mask;
929 	),
930 	TP_printk("new=%x existing=%x", __entry->new_bits,
931 		  __entry->pending_mask)
932 );
933 
934 DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
935 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
936 	TP_ARGS(pending_mask, ctl_flush),
937 	TP_STRUCT__entry(
938 		__field(	u32,			pending_mask	)
939 		__field(	u32,			ctl_flush	)
940 	),
941 	TP_fast_assign(
942 		__entry->pending_mask = pending_mask;
943 		__entry->ctl_flush = ctl_flush;
944 	),
945 	TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
946 		  __entry->ctl_flush)
947 );
948 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
949 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
950 	TP_ARGS(pending_mask, ctl_flush)
951 );
952 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
953 	     dpu_hw_ctl_trigger_pending_flush,
954 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
955 	TP_ARGS(pending_mask, ctl_flush)
956 );
957 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
958 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
959 	TP_ARGS(pending_mask, ctl_flush)
960 );
961 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
962 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
963 	TP_ARGS(pending_mask, ctl_flush)
964 );
965 
966 #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
967 #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
968 #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
969 
970 #define DPU_ATRACE_INT(name, value) \
971 	trace_dpu_trace_counter(current->tgid, name, value)
972 
973 #endif /* _DPU_TRACE_H_ */
974 
975 /* This part must be outside protection */
976 #undef TRACE_INCLUDE_PATH
977 #define TRACE_INCLUDE_PATH .
978 #include <trace/define_trace.h>
979