1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DPU_RM_H__ 7 #define __DPU_RM_H__ 8 9 #include <linux/list.h> 10 11 #include "msm_kms.h" 12 #include "dpu_hw_top.h" 13 14 struct dpu_global_state; 15 16 /** 17 * struct dpu_rm - DPU dynamic hardware resource manager 18 * @pingpong_blks: array of pingpong hardware resources 19 * @mixer_blks: array of layer mixer hardware resources 20 * @ctl_blks: array of ctl hardware resources 21 * @hw_intf: array of intf hardware resources 22 * @hw_wb: array of wb hardware resources 23 * @dspp_blks: array of dspp hardware resources 24 * @hw_sspp: array of sspp hardware resources 25 * @cdm_blk: cdm hardware resource 26 */ 27 struct dpu_rm { 28 struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; 29 struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; 30 struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; 31 struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; 32 struct dpu_hw_wb *hw_wb[WB_MAX - WB_0]; 33 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; 34 struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; 35 struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; 36 struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE]; 37 struct dpu_hw_blk *cdm_blk; 38 }; 39 40 /** 41 * struct msm_display_topology - defines a display topology pipeline 42 * @num_lm: number of layer mixers used 43 * @num_intf: number of interfaces the panel is mounted on 44 * @num_dspp: number of dspp blocks used 45 * @num_dsc: number of Display Stream Compression (DSC) blocks used 46 * @needs_cdm: indicates whether cdm block is needed for this display topology 47 */ 48 struct msm_display_topology { 49 u32 num_lm; 50 u32 num_intf; 51 u32 num_dspp; 52 u32 num_dsc; 53 bool needs_cdm; 54 }; 55 56 int dpu_rm_init(struct drm_device *dev, 57 struct dpu_rm *rm, 58 const struct dpu_mdss_cfg *cat, 59 const struct msm_mdss_data *mdss_data, 60 void __iomem *mmio); 61 62 int dpu_rm_reserve(struct dpu_rm *rm, 63 struct dpu_global_state *global_state, 64 struct drm_encoder *drm_enc, 65 struct drm_crtc_state *crtc_state, 66 struct msm_display_topology topology); 67 68 void dpu_rm_release(struct dpu_global_state *global_state, 69 struct drm_encoder *enc); 70 71 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 72 struct dpu_global_state *global_state, uint32_t enc_id, 73 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 74 75 void dpu_rm_print_state(struct drm_printer *p, 76 const struct dpu_global_state *global_state); 77 78 /** 79 * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index. 80 * @rm: DPU Resource Manager handle 81 * @intf_idx: INTF's index 82 */ 83 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx) 84 { 85 return rm->hw_intf[intf_idx - INTF_0]; 86 } 87 88 /** 89 * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index. 90 * @rm: DPU Resource Manager handle 91 * @wb_idx: WB index 92 */ 93 static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx) 94 { 95 return rm->hw_wb[wb_idx - WB_0]; 96 } 97 98 /** 99 * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index. 100 * @rm: DPU Resource Manager handle 101 * @sspp_idx: SSPP index 102 */ 103 static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx) 104 { 105 return rm->hw_sspp[sspp_idx - SSPP_NONE]; 106 } 107 108 #endif /* __DPU_RM_H__ */ 109 110