1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DPU_RM_H__ 7 #define __DPU_RM_H__ 8 9 #include <linux/list.h> 10 11 #include "msm_kms.h" 12 #include "dpu_hw_top.h" 13 14 struct dpu_global_state; 15 16 /** 17 * struct dpu_rm - DPU dynamic hardware resource manager 18 * @pingpong_blks: array of pingpong hardware resources 19 * @mixer_blks: array of layer mixer hardware resources 20 * @ctl_blks: array of ctl hardware resources 21 * @hw_intf: array of intf hardware resources 22 * @hw_wb: array of wb hardware resources 23 * @hw_cwb: array of cwb hardware resources 24 * @dspp_blks: array of dspp hardware resources 25 * @hw_sspp: array of sspp hardware resources 26 * @cdm_blk: cdm hardware resource 27 */ 28 struct dpu_rm { 29 struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; 30 struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; 31 struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; 32 struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; 33 struct dpu_hw_wb *hw_wb[WB_MAX - WB_0]; 34 struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0]; 35 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; 36 struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; 37 struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; 38 struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE]; 39 struct dpu_hw_blk *cdm_blk; 40 }; 41 42 struct dpu_rm_sspp_requirements { 43 bool yuv; 44 bool scale; 45 bool rot90; 46 }; 47 48 /** 49 * struct msm_display_topology - defines a display topology pipeline 50 * @num_lm: number of layer mixers used 51 * @num_intf: number of interfaces the panel is mounted on 52 * @num_dspp: number of dspp blocks used 53 * @num_dsc: number of Display Stream Compression (DSC) blocks used 54 * @num_cdm: indicates how many outputs are requesting cdm block for 55 * this display topology 56 * @cwb_enabled: indicates whether CWB is enabled for this display topology 57 */ 58 struct msm_display_topology { 59 u32 num_lm; 60 u32 num_intf; 61 u32 num_dspp; 62 u32 num_dsc; 63 int num_cdm; 64 bool cwb_enabled; 65 }; 66 67 int dpu_rm_init(struct drm_device *dev, 68 struct dpu_rm *rm, 69 const struct dpu_mdss_cfg *cat, 70 const struct msm_mdss_data *mdss_data, 71 void __iomem *mmio); 72 73 int dpu_rm_reserve(struct dpu_rm *rm, 74 struct dpu_global_state *global_state, 75 struct drm_crtc *crtc, 76 struct msm_display_topology *topology); 77 78 void dpu_rm_release(struct dpu_global_state *global_state, 79 struct drm_crtc *crtc); 80 81 struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, 82 struct dpu_global_state *global_state, 83 struct drm_crtc *crtc, 84 struct dpu_rm_sspp_requirements *reqs); 85 86 void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, 87 struct drm_crtc *crtc); 88 89 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 90 struct dpu_global_state *global_state, struct drm_crtc *crtc, 91 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 92 93 void dpu_rm_print_state(struct drm_printer *p, 94 const struct dpu_global_state *global_state); 95 96 /** 97 * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index. 98 * @rm: DPU Resource Manager handle 99 * @intf_idx: INTF's index 100 */ 101 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx) 102 { 103 return rm->hw_intf[intf_idx - INTF_0]; 104 } 105 106 /** 107 * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index. 108 * @rm: DPU Resource Manager handle 109 * @wb_idx: WB index 110 */ 111 static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx) 112 { 113 return rm->hw_wb[wb_idx - WB_0]; 114 } 115 116 /** 117 * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index. 118 * @rm: DPU Resource Manager handle 119 * @sspp_idx: SSPP index 120 */ 121 static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx) 122 { 123 return rm->hw_sspp[sspp_idx - SSPP_NONE]; 124 } 125 126 #endif /* __DPU_RM_H__ */ 127 128