xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h (revision 5a558f369ef89c6fd8170ee1137274fcc08517ae)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DPU_RM_H__
7 #define __DPU_RM_H__
8 
9 #include <linux/list.h>
10 
11 #include "msm_kms.h"
12 #include "dpu_hw_top.h"
13 
14 struct dpu_global_state;
15 
16 /**
17  * struct dpu_rm - DPU dynamic hardware resource manager
18  * @pingpong_blks: array of pingpong hardware resources
19  * @mixer_blks: array of layer mixer hardware resources
20  * @ctl_blks: array of ctl hardware resources
21  * @hw_intf: array of intf hardware resources
22  * @hw_wb: array of wb hardware resources
23  * @dspp_blks: array of dspp hardware resources
24  * @hw_sspp: array of sspp hardware resources
25  * @cdm_blk: cdm hardware resource
26  */
27 struct dpu_rm {
28 	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
29 	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
30 	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
31 	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
32 	struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
33 	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
34 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
35 	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
36 	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
37 	struct dpu_hw_blk *cdm_blk;
38 };
39 
40 /**
41  * dpu_rm_init - Read hardware catalog and create reservation tracking objects
42  *	for all HW blocks.
43  * @dev:  Corresponding device for devres management
44  * @rm: DPU Resource Manager handle
45  * @cat: Pointer to hardware catalog
46  * @mdss_data: Pointer to MDSS / UBWC configuration
47  * @mmio: mapped register io address of MDP
48  * @Return: 0 on Success otherwise -ERROR
49  */
50 int dpu_rm_init(struct drm_device *dev,
51 		struct dpu_rm *rm,
52 		const struct dpu_mdss_cfg *cat,
53 		const struct msm_mdss_data *mdss_data,
54 		void __iomem *mmio);
55 
56 /**
57  * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
58  *	the use connections and user requirements, specified through related
59  *	topology control properties, and reserve hardware blocks to that
60  *	display chain.
61  *	HW blocks can then be accessed through dpu_rm_get_* functions.
62  *	HW Reservations should be released via dpu_rm_release_hw.
63  * @rm: DPU Resource Manager handle
64  * @drm_enc: DRM Encoder handle
65  * @crtc_state: Proposed Atomic DRM CRTC State handle
66  * @topology: Pointer to topology info for the display
67  * @Return: 0 on Success otherwise -ERROR
68  */
69 int dpu_rm_reserve(struct dpu_rm *rm,
70 		struct dpu_global_state *global_state,
71 		struct drm_encoder *drm_enc,
72 		struct drm_crtc_state *crtc_state,
73 		struct msm_display_topology topology);
74 
75 /**
76  * dpu_rm_reserve - Given the encoder for the display chain, release any
77  *	HW blocks previously reserved for that use case.
78  * @rm: DPU Resource Manager handle
79  * @enc: DRM Encoder handle
80  * @Return: 0 on Success otherwise -ERROR
81  */
82 void dpu_rm_release(struct dpu_global_state *global_state,
83 		struct drm_encoder *enc);
84 
85 /**
86  * Get hw resources of the given type that are assigned to this encoder.
87  */
88 int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
89 	struct dpu_global_state *global_state, uint32_t enc_id,
90 	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
91 
92 /**
93  * dpu_rm_print_state - output the RM private state
94  * @p: DRM printer
95  * @global_state: global state
96  */
97 void dpu_rm_print_state(struct drm_printer *p,
98 			const struct dpu_global_state *global_state);
99 
100 /**
101  * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
102  * @rm: DPU Resource Manager handle
103  * @intf_idx: INTF's index
104  */
105 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
106 {
107 	return rm->hw_intf[intf_idx - INTF_0];
108 }
109 
110 /**
111  * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
112  * @rm: DPU Resource Manager handle
113  * @wb_idx: WB index
114  */
115 static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
116 {
117 	return rm->hw_wb[wb_idx - WB_0];
118 }
119 
120 /**
121  * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
122  * @rm: DPU Resource Manager handle
123  * @sspp_idx: SSPP index
124  */
125 static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
126 {
127 	return rm->hw_sspp[sspp_idx - SSPP_NONE];
128 }
129 
130 #endif /* __DPU_RM_H__ */
131 
132