xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h (revision 3f0a50f345f78183f6e9b39c2f45ca5dcaa511ca)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DPU_RM_H__
7 #define __DPU_RM_H__
8 
9 #include <linux/list.h>
10 
11 #include "msm_kms.h"
12 #include "dpu_hw_top.h"
13 
14 struct dpu_global_state;
15 
16 /**
17  * struct dpu_rm - DPU dynamic hardware resource manager
18  * @pingpong_blks: array of pingpong hardware resources
19  * @mixer_blks: array of layer mixer hardware resources
20  * @ctl_blks: array of ctl hardware resources
21  * @hw_intf: array of intf hardware resources
22  * @dspp_blks: array of dspp hardware resources
23  */
24 struct dpu_rm {
25 	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
26 	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
27 	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
28 	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
29 	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
30 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
31 };
32 
33 /**
34  * dpu_rm_init - Read hardware catalog and create reservation tracking objects
35  *	for all HW blocks.
36  * @rm: DPU Resource Manager handle
37  * @cat: Pointer to hardware catalog
38  * @mmio: mapped register io address of MDP
39  * @Return: 0 on Success otherwise -ERROR
40  */
41 int dpu_rm_init(struct dpu_rm *rm,
42 		struct dpu_mdss_cfg *cat,
43 		void __iomem *mmio);
44 
45 /**
46  * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
47  * @rm: DPU Resource Manager handle
48  * @Return: 0 on Success otherwise -ERROR
49  */
50 int dpu_rm_destroy(struct dpu_rm *rm);
51 
52 /**
53  * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
54  *	the use connections and user requirements, specified through related
55  *	topology control properties, and reserve hardware blocks to that
56  *	display chain.
57  *	HW blocks can then be accessed through dpu_rm_get_* functions.
58  *	HW Reservations should be released via dpu_rm_release_hw.
59  * @rm: DPU Resource Manager handle
60  * @drm_enc: DRM Encoder handle
61  * @crtc_state: Proposed Atomic DRM CRTC State handle
62  * @topology: Pointer to topology info for the display
63  * @Return: 0 on Success otherwise -ERROR
64  */
65 int dpu_rm_reserve(struct dpu_rm *rm,
66 		struct dpu_global_state *global_state,
67 		struct drm_encoder *drm_enc,
68 		struct drm_crtc_state *crtc_state,
69 		struct msm_display_topology topology);
70 
71 /**
72  * dpu_rm_reserve - Given the encoder for the display chain, release any
73  *	HW blocks previously reserved for that use case.
74  * @rm: DPU Resource Manager handle
75  * @enc: DRM Encoder handle
76  * @Return: 0 on Success otherwise -ERROR
77  */
78 void dpu_rm_release(struct dpu_global_state *global_state,
79 		struct drm_encoder *enc);
80 
81 /**
82  * Get hw resources of the given type that are assigned to this encoder.
83  */
84 int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
85 	struct dpu_global_state *global_state, uint32_t enc_id,
86 	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
87 
88 /**
89  * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
90  * @rm: DPU Resource Manager handle
91  * @intf_idx: INTF's index
92  */
93 static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
94 {
95 	return rm->hw_intf[intf_idx - INTF_0];
96 }
97 
98 #endif /* __DPU_RM_H__ */
99 
100