1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "msm_mdss.h" 22 #include "dpu_kms.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_hw_util.h" 25 #include "dpu_trace.h" 26 #include "dpu_crtc.h" 27 #include "dpu_vbif.h" 28 #include "dpu_plane.h" 29 30 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 32 33 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 34 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 35 36 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 37 #define PHASE_STEP_SHIFT 21 38 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 39 #define PHASE_RESIDUAL 15 40 41 #define SHARP_STRENGTH_DEFAULT 32 42 #define SHARP_EDGE_THR_DEFAULT 112 43 #define SHARP_SMOOTH_THR_DEFAULT 8 44 #define SHARP_NOISE_THR_DEFAULT 2 45 46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 47 #define DPU_ZPOS_MAX 255 48 49 /* 50 * Default Preload Values 51 */ 52 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 53 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 54 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 55 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 56 57 #define DEFAULT_REFRESH_RATE 60 58 59 static const uint32_t qcom_compressed_supported_formats[] = { 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_ARGB8888, 62 DRM_FORMAT_XBGR8888, 63 DRM_FORMAT_XRGB8888, 64 DRM_FORMAT_ARGB2101010, 65 DRM_FORMAT_XRGB2101010, 66 DRM_FORMAT_BGR565, 67 68 DRM_FORMAT_NV12, 69 DRM_FORMAT_P010, 70 }; 71 72 /* 73 * struct dpu_plane - local dpu plane structure 74 * @aspace: address space pointer 75 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 76 * @catalog: Points to dpu catalog structure 77 * @revalidate: force revalidation of all the plane properties 78 */ 79 struct dpu_plane { 80 struct drm_plane base; 81 82 enum dpu_sspp pipe; 83 84 uint32_t color_fill; 85 bool is_error; 86 bool is_rt_pipe; 87 const struct dpu_mdss_cfg *catalog; 88 }; 89 90 static const uint64_t supported_format_modifiers[] = { 91 DRM_FORMAT_MOD_QCOM_COMPRESSED, 92 DRM_FORMAT_MOD_LINEAR, 93 DRM_FORMAT_MOD_INVALID 94 }; 95 96 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 97 98 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 99 { 100 struct msm_drm_private *priv = plane->dev->dev_private; 101 102 return to_dpu_kms(priv->kms); 103 } 104 105 /** 106 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 107 * @catalog: Points to dpu catalog structure 108 * @fmt: Pointer to source buffer format 109 * @mode: Pointer to drm display mode 110 * @pipe_cfg: Pointer to pipe configuration 111 * Result: Updates calculated bandwidth in the plane state. 112 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 113 * Prefill BW Equation: line src bytes * line_time 114 */ 115 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 116 const struct msm_format *fmt, 117 const struct drm_display_mode *mode, 118 struct dpu_sw_pipe_cfg *pipe_cfg) 119 { 120 int src_width, src_height, dst_height, fps; 121 u64 plane_pixel_rate, plane_bit_rate; 122 u64 plane_prefill_bw; 123 u64 plane_bw; 124 u32 hw_latency_lines; 125 u64 scale_factor; 126 int vbp, vpw, vfp; 127 128 src_width = drm_rect_width(&pipe_cfg->src_rect); 129 src_height = drm_rect_height(&pipe_cfg->src_rect); 130 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 131 fps = drm_mode_vrefresh(mode); 132 vbp = mode->vtotal - mode->vsync_end; 133 vpw = mode->vsync_end - mode->vsync_start; 134 vfp = mode->vsync_start - mode->vdisplay; 135 hw_latency_lines = catalog->perf->min_prefill_lines; 136 scale_factor = src_height > dst_height ? 137 mult_frac(src_height, 1, dst_height) : 1; 138 139 plane_pixel_rate = src_width * mode->vtotal * fps; 140 plane_bit_rate = plane_pixel_rate * fmt->bpp; 141 142 plane_bw = plane_bit_rate * scale_factor; 143 144 plane_prefill_bw = plane_bw * hw_latency_lines; 145 146 if ((vbp+vpw) > hw_latency_lines) 147 do_div(plane_prefill_bw, (vbp+vpw)); 148 else if ((vbp+vpw+vfp) < hw_latency_lines) 149 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 150 else 151 do_div(plane_prefill_bw, hw_latency_lines); 152 153 154 return max(plane_bw, plane_prefill_bw); 155 } 156 157 /** 158 * _dpu_plane_calc_clk - calculate clock required for a plane 159 * @mode: Pointer to drm display mode 160 * @pipe_cfg: Pointer to pipe configuration 161 * Result: Updates calculated clock in the plane state. 162 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 163 */ 164 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 165 struct dpu_sw_pipe_cfg *pipe_cfg) 166 { 167 int dst_width, src_height, dst_height, fps; 168 u64 plane_clk; 169 170 src_height = drm_rect_height(&pipe_cfg->src_rect); 171 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 172 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 173 fps = drm_mode_vrefresh(mode); 174 175 plane_clk = 176 dst_width * mode->vtotal * fps; 177 178 if (src_height > dst_height) { 179 plane_clk *= src_height; 180 do_div(plane_clk, dst_height); 181 } 182 183 return plane_clk; 184 } 185 186 /** 187 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 188 * @plane: Pointer to drm plane 189 * @pipe: Pointer to software pipe 190 * @lut_usage: LUT usecase 191 * @fmt: Pointer to source buffer format 192 * @src_width: width of source buffer 193 * Return: fill level corresponding to the source buffer/format or 0 if error 194 */ 195 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 196 struct dpu_sw_pipe *pipe, 197 enum dpu_qos_lut_usage lut_usage, 198 const struct msm_format *fmt, u32 src_width) 199 { 200 struct dpu_plane *pdpu; 201 u32 fixed_buff_size; 202 u32 total_fl; 203 204 if (!fmt || !pipe || !src_width || !fmt->bpp) { 205 DPU_ERROR("invalid arguments\n"); 206 return 0; 207 } 208 209 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 210 return 0; 211 212 pdpu = to_dpu_plane(plane); 213 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 214 215 /* FIXME: in multirect case account for the src_width of all the planes */ 216 217 if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { 218 if (fmt->chroma_sample == CHROMA_420) { 219 /* NV12 */ 220 total_fl = (fixed_buff_size / 2) / 221 ((src_width + 32) * fmt->bpp); 222 } else { 223 /* non NV12 */ 224 total_fl = (fixed_buff_size / 2) * 2 / 225 ((src_width + 32) * fmt->bpp); 226 } 227 } else { 228 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 229 total_fl = (fixed_buff_size / 2) * 2 / 230 ((src_width + 32) * fmt->bpp); 231 } else { 232 total_fl = (fixed_buff_size) * 2 / 233 ((src_width + 32) * fmt->bpp); 234 } 235 } 236 237 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n", 238 pipe->sspp->idx - SSPP_VIG0, 239 &fmt->pixel_format, 240 src_width, total_fl); 241 242 return total_fl; 243 } 244 245 /** 246 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 247 * @plane: Pointer to drm plane 248 * @pipe: Pointer to software pipe 249 * @fmt: Pointer to source buffer format 250 * @pipe_cfg: Pointer to pipe configuration 251 */ 252 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 253 struct dpu_sw_pipe *pipe, 254 const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 255 { 256 struct dpu_plane *pdpu = to_dpu_plane(plane); 257 struct dpu_hw_qos_cfg cfg; 258 u32 total_fl, lut_usage; 259 260 if (!pdpu->is_rt_pipe) { 261 lut_usage = DPU_QOS_LUT_USAGE_NRT; 262 } else { 263 if (fmt && MSM_FORMAT_IS_LINEAR(fmt)) 264 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 265 else 266 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 267 } 268 269 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 270 drm_rect_width(&pipe_cfg->src_rect)); 271 272 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 273 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 274 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 275 276 if (pipe->sspp->idx != SSPP_CURSOR0 && 277 pipe->sspp->idx != SSPP_CURSOR1 && 278 pdpu->is_rt_pipe) 279 cfg.danger_safe_en = true; 280 281 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 282 pdpu->pipe - SSPP_VIG0, 283 cfg.danger_safe_en, 284 pdpu->is_rt_pipe); 285 286 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 287 (fmt) ? fmt->pixel_format : 0, 288 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 289 290 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n", 291 pdpu->pipe - SSPP_VIG0, 292 fmt ? &fmt->pixel_format : NULL, 293 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 294 295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 296 (fmt) ? fmt->pixel_format : 0, 297 (fmt) ? fmt->fetch_mode : 0, 298 cfg.danger_lut, 299 cfg.safe_lut); 300 301 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", 302 pdpu->pipe - SSPP_VIG0, 303 fmt ? &fmt->pixel_format : NULL, 304 fmt ? fmt->fetch_mode : -1, 305 cfg.danger_lut, 306 cfg.safe_lut); 307 308 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 309 } 310 311 /** 312 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 313 * @plane: Pointer to drm plane 314 * @pipe: Pointer to software pipe 315 * @enable: true to enable QoS control 316 */ 317 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 318 struct dpu_sw_pipe *pipe, 319 bool enable) 320 { 321 struct dpu_plane *pdpu = to_dpu_plane(plane); 322 323 if (!pdpu->is_rt_pipe) 324 enable = false; 325 326 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 327 pdpu->pipe - SSPP_VIG0, 328 enable, 329 pdpu->is_rt_pipe); 330 331 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 332 enable); 333 } 334 335 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp, 336 struct dpu_hw_mdp *mdp, 337 bool enable, bool *forced_on) 338 { 339 if (sspp->ops.setup_clk_force_ctrl) { 340 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable); 341 return true; 342 } 343 344 if (mdp->ops.setup_clk_force_ctrl) { 345 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); 346 return true; 347 } 348 349 return false; 350 } 351 352 /** 353 * _dpu_plane_set_ot_limit - set OT limit for the given plane 354 * @plane: Pointer to drm plane 355 * @pipe: Pointer to software pipe 356 * @pipe_cfg: Pointer to pipe configuration 357 * @frame_rate: CRTC's frame rate 358 */ 359 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 360 struct dpu_sw_pipe *pipe, 361 struct dpu_sw_pipe_cfg *pipe_cfg, 362 int frame_rate) 363 { 364 struct dpu_plane *pdpu = to_dpu_plane(plane); 365 struct dpu_vbif_set_ot_params ot_params; 366 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 367 bool forced_on = false; 368 369 memset(&ot_params, 0, sizeof(ot_params)); 370 ot_params.xin_id = pipe->sspp->cap->xin_id; 371 ot_params.num = pipe->sspp->idx - SSPP_NONE; 372 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 373 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 374 ot_params.is_wfd = !pdpu->is_rt_pipe; 375 ot_params.frame_rate = frame_rate; 376 ot_params.vbif_idx = VBIF_RT; 377 ot_params.rd = true; 378 379 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 380 true, &forced_on)) 381 return; 382 383 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 384 385 if (forced_on) 386 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 387 false, &forced_on); 388 } 389 390 /** 391 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 392 * @plane: Pointer to drm plane 393 * @pipe: Pointer to software pipe 394 */ 395 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 396 struct dpu_sw_pipe *pipe) 397 { 398 struct dpu_plane *pdpu = to_dpu_plane(plane); 399 struct dpu_vbif_set_qos_params qos_params; 400 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 401 bool forced_on = false; 402 403 memset(&qos_params, 0, sizeof(qos_params)); 404 qos_params.vbif_idx = VBIF_RT; 405 qos_params.xin_id = pipe->sspp->cap->xin_id; 406 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 407 qos_params.is_rt = pdpu->is_rt_pipe; 408 409 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n", 410 qos_params.num, 411 qos_params.vbif_idx, 412 qos_params.xin_id, qos_params.is_rt); 413 414 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 415 true, &forced_on)) 416 return; 417 418 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 419 420 if (forced_on) 421 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 422 false, &forced_on); 423 } 424 425 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 426 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 427 struct dpu_hw_scaler3_cfg *scale_cfg, 428 const struct msm_format *fmt, 429 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 430 unsigned int rotation) 431 { 432 uint32_t i; 433 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 434 435 /* 436 * For inline rotation cases, scaler config is post-rotation, 437 * so swap the dimensions here. However, pixel extension will 438 * need pre-rotation settings. 439 */ 440 if (inline_rotation) 441 swap(src_w, src_h); 442 443 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 444 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 445 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 446 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 447 448 449 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 450 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 451 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 452 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 453 454 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 455 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 456 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 458 459 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 461 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 462 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 463 464 for (i = 0; i < DPU_MAX_PLANES; i++) { 465 scale_cfg->src_width[i] = src_w; 466 scale_cfg->src_height[i] = src_h; 467 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 468 scale_cfg->src_width[i] /= chroma_subsmpl_h; 469 scale_cfg->src_height[i] /= chroma_subsmpl_v; 470 } 471 472 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) { 473 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 474 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 475 } else { 476 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 477 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 478 } 479 } 480 if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 481 && (src_w == dst_w)) 482 return; 483 484 scale_cfg->dst_width = dst_w; 485 scale_cfg->dst_height = dst_h; 486 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 487 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 488 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 489 scale_cfg->lut_flag = 0; 490 scale_cfg->blend_cfg = 1; 491 scale_cfg->enable = 1; 492 } 493 494 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 495 struct dpu_hw_pixel_ext *pixel_ext, 496 uint32_t src_w, uint32_t src_h, 497 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 498 { 499 int i; 500 501 for (i = 0; i < DPU_MAX_PLANES; i++) { 502 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 503 src_w /= chroma_subsmpl_h; 504 src_h /= chroma_subsmpl_v; 505 } 506 507 pixel_ext->num_ext_pxls_top[i] = src_h; 508 pixel_ext->num_ext_pxls_left[i] = src_w; 509 } 510 } 511 512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 513 const struct msm_format *fmt) 514 { 515 const struct dpu_csc_cfg *csc_ptr; 516 517 if (!MSM_FORMAT_IS_YUV(fmt)) 518 return NULL; 519 520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 521 csc_ptr = &dpu_csc10_YUV2RGB_601L; 522 else 523 csc_ptr = &dpu_csc_YUV2RGB_601L; 524 525 return csc_ptr; 526 } 527 528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 529 const struct msm_format *fmt, bool color_fill, 530 struct dpu_sw_pipe_cfg *pipe_cfg) 531 { 532 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 533 const struct drm_format_info *info = drm_format_info(fmt->pixel_format); 534 struct dpu_hw_scaler3_cfg scaler3_cfg; 535 struct dpu_hw_pixel_ext pixel_ext; 536 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 537 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 538 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 539 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 540 541 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 542 memset(&pixel_ext, 0, sizeof(pixel_ext)); 543 544 /* don't chroma subsample if decimating */ 545 /* update scaler. calculate default config for QSEED3 */ 546 _dpu_plane_setup_scaler3(pipe_hw, 547 src_width, 548 src_height, 549 dst_width, 550 dst_height, 551 &scaler3_cfg, fmt, 552 info->hsub, info->vsub, 553 pipe_cfg->rotation); 554 555 /* configure pixel extension based on scalar config */ 556 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 557 src_width, src_height, info->hsub, info->vsub); 558 559 if (pipe_hw->ops.setup_pe) 560 pipe_hw->ops.setup_pe(pipe_hw, 561 &pixel_ext); 562 563 /** 564 * when programmed in multirect mode, scalar block will be 565 * bypassed. Still we need to update alpha and bitwidth 566 * ONLY for RECT0 567 */ 568 if (pipe_hw->ops.setup_scaler && 569 pipe->multirect_index != DPU_SSPP_RECT_1) 570 pipe_hw->ops.setup_scaler(pipe_hw, 571 &scaler3_cfg, 572 fmt); 573 } 574 575 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 576 struct dpu_sw_pipe *pipe, 577 struct drm_rect *dst_rect, 578 u32 fill_color, 579 const struct msm_format *fmt) 580 { 581 struct dpu_sw_pipe_cfg pipe_cfg; 582 583 /* update sspp */ 584 if (!pipe->sspp->ops.setup_solidfill) 585 return; 586 587 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 588 589 /* override scaler/decimation if solid fill */ 590 pipe_cfg.dst_rect = *dst_rect; 591 592 pipe_cfg.src_rect.x1 = 0; 593 pipe_cfg.src_rect.y1 = 0; 594 pipe_cfg.src_rect.x2 = 595 drm_rect_width(&pipe_cfg.dst_rect); 596 pipe_cfg.src_rect.y2 = 597 drm_rect_height(&pipe_cfg.dst_rect); 598 599 if (pipe->sspp->ops.setup_format) 600 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 601 602 if (pipe->sspp->ops.setup_rects) 603 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 604 605 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); 606 } 607 608 /** 609 * _dpu_plane_color_fill - enables color fill on plane 610 * @pdpu: Pointer to DPU plane object 611 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 612 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 613 */ 614 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 615 uint32_t color, uint32_t alpha) 616 { 617 const struct msm_format *fmt; 618 const struct drm_plane *plane = &pdpu->base; 619 struct msm_drm_private *priv = plane->dev->dev_private; 620 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 621 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 622 623 DPU_DEBUG_PLANE(pdpu, "\n"); 624 625 /* 626 * select fill format to match user property expectation, 627 * h/w only supports RGB variants 628 */ 629 fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0); 630 /* should not happen ever */ 631 if (!fmt) 632 return; 633 634 /* update sspp */ 635 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 636 fill_color, fmt); 637 638 if (pstate->r_pipe.sspp) 639 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 640 fill_color, fmt); 641 } 642 643 static int dpu_plane_prepare_fb(struct drm_plane *plane, 644 struct drm_plane_state *new_state) 645 { 646 struct drm_framebuffer *fb = new_state->fb; 647 struct dpu_plane *pdpu = to_dpu_plane(plane); 648 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 649 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 650 int ret; 651 652 if (!new_state->fb) 653 return 0; 654 655 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 656 657 /* cache aspace */ 658 pstate->aspace = kms->base.aspace; 659 660 /* 661 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 662 * we can use msm_atomic_prepare_fb() instead of doing the 663 * implicit fence and fb prepare by hand here. 664 */ 665 drm_gem_plane_helper_prepare_fb(plane, new_state); 666 667 if (pstate->aspace) { 668 ret = msm_framebuffer_prepare(new_state->fb, 669 pstate->aspace, pstate->needs_dirtyfb); 670 if (ret) { 671 DPU_ERROR("failed to prepare framebuffer\n"); 672 return ret; 673 } 674 } 675 676 return 0; 677 } 678 679 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 680 struct drm_plane_state *old_state) 681 { 682 struct dpu_plane *pdpu = to_dpu_plane(plane); 683 struct dpu_plane_state *old_pstate; 684 685 if (!old_state || !old_state->fb) 686 return; 687 688 old_pstate = to_dpu_plane_state(old_state); 689 690 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 691 692 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 693 old_pstate->needs_dirtyfb); 694 } 695 696 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 697 struct dpu_sw_pipe *pipe, 698 struct drm_rect src, 699 const struct msm_format *fmt) 700 { 701 const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; 702 size_t num_formats; 703 const u32 *supported_formats; 704 705 if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) 706 return -EINVAL; 707 708 if (!sblk->rotation_cfg) { 709 DPU_ERROR("invalid rotation cfg\n"); 710 return -EINVAL; 711 } 712 713 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 714 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 715 src.y2, sblk->rotation_cfg->rot_maxheight); 716 return -EINVAL; 717 } 718 719 supported_formats = sblk->rotation_cfg->rot_format_list; 720 num_formats = sblk->rotation_cfg->rot_num_formats; 721 722 if (!MSM_FORMAT_IS_UBWC(fmt) || 723 !dpu_find_format(fmt->pixel_format, supported_formats, num_formats)) 724 return -EINVAL; 725 726 return 0; 727 } 728 729 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 730 struct dpu_sw_pipe *pipe, 731 struct dpu_sw_pipe_cfg *pipe_cfg, 732 const struct drm_display_mode *mode, 733 struct drm_plane_state *new_plane_state) 734 { 735 uint32_t min_src_size; 736 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 737 int ret; 738 const struct msm_format *fmt; 739 uint32_t supported_rotations; 740 const struct dpu_sspp_cfg *pipe_hw_caps; 741 const struct dpu_sspp_sub_blks *sblk; 742 743 pipe_hw_caps = pipe->sspp->cap; 744 sblk = pipe->sspp->cap->sblk; 745 746 /* 747 * We already have verified scaling against platform limitations. 748 * Now check if the SSPP supports scaling at all. 749 */ 750 if (!sblk->scaler_blk.len && 751 ((drm_rect_width(&new_plane_state->src) >> 16 != 752 drm_rect_width(&new_plane_state->dst)) || 753 (drm_rect_height(&new_plane_state->src) >> 16 != 754 drm_rect_height(&new_plane_state->dst)))) 755 return -ERANGE; 756 757 fmt = msm_framebuffer_format(new_plane_state->fb); 758 759 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 760 761 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 762 supported_rotations |= DRM_MODE_ROTATE_90; 763 764 pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, 765 supported_rotations); 766 767 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; 768 769 if (MSM_FORMAT_IS_YUV(fmt) && 770 !pipe->sspp->cap->sblk->csc_blk.len) { 771 DPU_DEBUG_PLANE(pdpu, 772 "plane doesn't have csc for yuv\n"); 773 return -EINVAL; 774 } 775 776 /* check src bounds */ 777 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 778 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 779 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 780 DRM_RECT_ARG(&pipe_cfg->src_rect)); 781 return -E2BIG; 782 } 783 784 /* valid yuv image */ 785 if (MSM_FORMAT_IS_YUV(fmt) && 786 (pipe_cfg->src_rect.x1 & 0x1 || 787 pipe_cfg->src_rect.y1 & 0x1 || 788 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 789 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 790 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 791 DRM_RECT_ARG(&pipe_cfg->src_rect)); 792 return -EINVAL; 793 } 794 795 /* min dst support */ 796 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 797 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 798 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 799 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 800 return -EINVAL; 801 } 802 803 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { 804 ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); 805 if (ret) 806 return ret; 807 } 808 809 /* max clk check */ 810 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 811 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 812 return -E2BIG; 813 } 814 815 return 0; 816 } 817 818 #define MAX_UPSCALE_RATIO 20 819 #define MAX_DOWNSCALE_RATIO 4 820 821 static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, 822 struct drm_plane_state *new_plane_state, 823 const struct drm_crtc_state *crtc_state) 824 { 825 int i, ret = 0, min_scale, max_scale; 826 struct dpu_plane *pdpu = to_dpu_plane(plane); 827 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 828 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 829 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 830 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 831 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 832 struct drm_rect fb_rect = { 0 }; 833 uint32_t max_linewidth; 834 835 min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); 836 max_scale = MAX_DOWNSCALE_RATIO << 16; 837 838 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 839 min_scale, 840 max_scale, 841 true, true); 842 if (ret) { 843 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 844 return ret; 845 } 846 if (!new_plane_state->visible) 847 return 0; 848 849 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 850 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 851 DPU_ERROR("> %d plane stages assigned\n", 852 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 853 return -EINVAL; 854 } 855 856 /* state->src is 16.16, src_rect is not */ 857 drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); 858 859 pipe_cfg->dst_rect = new_plane_state->dst; 860 861 fb_rect.x2 = new_plane_state->fb->width; 862 fb_rect.y2 = new_plane_state->fb->height; 863 864 /* Ensure fb size is supported */ 865 if (drm_rect_width(&fb_rect) > DPU_MAX_IMG_WIDTH || 866 drm_rect_height(&fb_rect) > DPU_MAX_IMG_HEIGHT) { 867 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 868 DRM_RECT_ARG(&fb_rect)); 869 return -E2BIG; 870 } 871 872 ret = dpu_format_populate_plane_sizes(new_plane_state->fb, &pstate->layout); 873 if (ret) { 874 DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); 875 return ret; 876 } 877 878 for (i = 0; i < pstate->layout.num_planes; i++) 879 if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) 880 return -E2BIG; 881 882 max_linewidth = pdpu->catalog->caps->max_linewidth; 883 884 drm_rect_rotate(&pipe_cfg->src_rect, 885 new_plane_state->fb->width, new_plane_state->fb->height, 886 new_plane_state->rotation); 887 888 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 889 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 890 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 891 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 892 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 893 return -E2BIG; 894 } 895 896 *r_pipe_cfg = *pipe_cfg; 897 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 898 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 899 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 900 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 901 } else { 902 memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); 903 } 904 905 drm_rect_rotate_inv(&pipe_cfg->src_rect, 906 new_plane_state->fb->width, new_plane_state->fb->height, 907 new_plane_state->rotation); 908 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) 909 drm_rect_rotate_inv(&r_pipe_cfg->src_rect, 910 new_plane_state->fb->width, new_plane_state->fb->height, 911 new_plane_state->rotation); 912 913 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 914 915 return 0; 916 } 917 918 static int dpu_plane_is_multirect_capable(struct dpu_hw_sspp *sspp, 919 struct dpu_sw_pipe_cfg *pipe_cfg, 920 const struct msm_format *fmt) 921 { 922 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 923 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect)) 924 return false; 925 926 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) 927 return false; 928 929 if (MSM_FORMAT_IS_YUV(fmt)) 930 return false; 931 932 if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) && 933 !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features)) 934 return false; 935 936 return true; 937 } 938 939 static int dpu_plane_is_parallel_capable(struct dpu_sw_pipe_cfg *pipe_cfg, 940 const struct msm_format *fmt, 941 uint32_t max_linewidth) 942 { 943 if (MSM_FORMAT_IS_UBWC(fmt) && 944 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) 945 return false; 946 947 return true; 948 } 949 950 static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *sspp, 951 struct dpu_sw_pipe_cfg *pipe_cfg, 952 const struct msm_format *fmt, 953 uint32_t max_linewidth) 954 { 955 return dpu_plane_is_multirect_capable(sspp, pipe_cfg, fmt) && 956 dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); 957 } 958 959 960 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, 961 struct drm_atomic_state *state, 962 const struct drm_crtc_state *crtc_state) 963 { 964 struct drm_plane_state *new_plane_state = 965 drm_atomic_get_new_plane_state(state, plane); 966 struct dpu_plane *pdpu = to_dpu_plane(plane); 967 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 968 struct dpu_sw_pipe *pipe = &pstate->pipe; 969 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 970 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 971 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 972 int ret = 0; 973 974 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, 975 &crtc_state->adjusted_mode, 976 new_plane_state); 977 if (ret) 978 return ret; 979 980 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { 981 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, 982 &crtc_state->adjusted_mode, 983 new_plane_state); 984 if (ret) 985 return ret; 986 } 987 988 return 0; 989 } 990 991 static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, 992 struct dpu_sw_pipe *r_pipe, struct dpu_sw_pipe_cfg *r_pipe_cfg, 993 struct dpu_hw_sspp *sspp, const struct msm_format *fmt, 994 uint32_t max_linewidth) 995 { 996 r_pipe->sspp = NULL; 997 998 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 999 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1000 1001 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1002 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1003 1004 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { 1005 if (!dpu_plane_is_multirect_parallel_capable(pipe->sspp, pipe_cfg, fmt, max_linewidth) || 1006 !dpu_plane_is_multirect_parallel_capable(pipe->sspp, r_pipe_cfg, fmt, max_linewidth)) 1007 return false; 1008 1009 r_pipe->sspp = pipe->sspp; 1010 1011 pipe->multirect_index = DPU_SSPP_RECT_0; 1012 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1013 1014 r_pipe->multirect_index = DPU_SSPP_RECT_1; 1015 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1016 } 1017 1018 return true; 1019 } 1020 1021 static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, 1022 struct dpu_plane_state *prev_adjacent_pstate, 1023 const struct msm_format *fmt, 1024 uint32_t max_linewidth) 1025 { 1026 struct dpu_sw_pipe *pipe = &pstate->pipe; 1027 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1028 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1029 struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe; 1030 struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg; 1031 const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb); 1032 u16 max_tile_height = 1; 1033 1034 if (prev_adjacent_pstate->r_pipe.sspp != NULL || 1035 prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE) 1036 return false; 1037 1038 if (!dpu_plane_is_multirect_capable(pipe->sspp, pipe_cfg, fmt) || 1039 !dpu_plane_is_multirect_capable(prev_pipe->sspp, prev_pipe_cfg, prev_fmt)) 1040 return false; 1041 1042 if (MSM_FORMAT_IS_UBWC(fmt)) 1043 max_tile_height = max(max_tile_height, fmt->tile_height); 1044 1045 if (MSM_FORMAT_IS_UBWC(prev_fmt)) 1046 max_tile_height = max(max_tile_height, prev_fmt->tile_height); 1047 1048 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1049 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1050 1051 r_pipe->sspp = NULL; 1052 1053 if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && 1054 dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) && 1055 (pipe_cfg->dst_rect.x1 >= prev_pipe_cfg->dst_rect.x2 || 1056 prev_pipe_cfg->dst_rect.x1 >= pipe_cfg->dst_rect.x2)) { 1057 pipe->sspp = prev_pipe->sspp; 1058 1059 pipe->multirect_index = DPU_SSPP_RECT_1; 1060 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1061 1062 prev_pipe->multirect_index = DPU_SSPP_RECT_0; 1063 prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1064 1065 return true; 1066 } 1067 1068 if (pipe_cfg->dst_rect.y1 >= prev_pipe_cfg->dst_rect.y2 + 2 * max_tile_height || 1069 prev_pipe_cfg->dst_rect.y1 >= pipe_cfg->dst_rect.y2 + 2 * max_tile_height) { 1070 pipe->sspp = prev_pipe->sspp; 1071 1072 pipe->multirect_index = DPU_SSPP_RECT_1; 1073 pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 1074 1075 prev_pipe->multirect_index = DPU_SSPP_RECT_0; 1076 prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 1077 1078 return true; 1079 } 1080 1081 return false; 1082 } 1083 1084 static int dpu_plane_atomic_check(struct drm_plane *plane, 1085 struct drm_atomic_state *state) 1086 { 1087 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1088 plane); 1089 int ret = 0; 1090 struct dpu_plane *pdpu = to_dpu_plane(plane); 1091 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 1092 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1093 struct dpu_sw_pipe *pipe = &pstate->pipe; 1094 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1095 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1096 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1097 const struct drm_crtc_state *crtc_state = NULL; 1098 uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; 1099 1100 if (new_plane_state->crtc) 1101 crtc_state = drm_atomic_get_new_crtc_state(state, 1102 new_plane_state->crtc); 1103 1104 pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1105 1106 if (!pipe->sspp) 1107 return -EINVAL; 1108 1109 ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); 1110 if (ret) 1111 return ret; 1112 1113 if (!new_plane_state->visible) 1114 return 0; 1115 1116 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1117 pipe->sspp, 1118 msm_framebuffer_format(new_plane_state->fb), 1119 max_linewidth)) { 1120 DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT 1121 " max_line:%u, can't use split source\n", 1122 DRM_RECT_ARG(&pipe_cfg->src_rect), 1123 DRM_RECT_ARG(&r_pipe_cfg->src_rect), 1124 max_linewidth); 1125 return -E2BIG; 1126 } 1127 1128 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1129 } 1130 1131 static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, 1132 struct drm_atomic_state *state) 1133 { 1134 struct drm_plane_state *plane_state = 1135 drm_atomic_get_plane_state(state, plane); 1136 struct drm_plane_state *old_plane_state = 1137 drm_atomic_get_old_plane_state(state, plane); 1138 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1139 struct drm_crtc_state *crtc_state; 1140 int ret; 1141 1142 if (IS_ERR(plane_state)) 1143 return PTR_ERR(plane_state); 1144 1145 if (plane_state->crtc) 1146 crtc_state = drm_atomic_get_new_crtc_state(state, 1147 plane_state->crtc); 1148 1149 ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state); 1150 if (ret) 1151 return ret; 1152 1153 if (!plane_state->visible) { 1154 /* 1155 * resources are freed by dpu_crtc_assign_plane_resources(), 1156 * but clean them here. 1157 */ 1158 pstate->pipe.sspp = NULL; 1159 pstate->r_pipe.sspp = NULL; 1160 1161 return 0; 1162 } 1163 1164 /* 1165 * Force resource reallocation if the format of FB or src/dst have 1166 * changed. We might need to allocate different SSPP or SSPPs for this 1167 * plane than the one used previously. 1168 */ 1169 if (!old_plane_state || !old_plane_state->fb || 1170 old_plane_state->src_w != plane_state->src_w || 1171 old_plane_state->src_h != plane_state->src_h || 1172 old_plane_state->src_w != plane_state->src_w || 1173 old_plane_state->crtc_h != plane_state->crtc_h || 1174 msm_framebuffer_format(old_plane_state->fb) != 1175 msm_framebuffer_format(plane_state->fb)) 1176 crtc_state->planes_changed = true; 1177 1178 return 0; 1179 } 1180 1181 static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, 1182 struct dpu_global_state *global_state, 1183 struct drm_atomic_state *state, 1184 struct drm_plane_state *plane_state, 1185 struct drm_plane_state *prev_adjacent_plane_state) 1186 { 1187 const struct drm_crtc_state *crtc_state = NULL; 1188 struct drm_plane *plane = plane_state->plane; 1189 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1190 struct dpu_rm_sspp_requirements reqs; 1191 struct dpu_plane_state *pstate, *prev_adjacent_pstate; 1192 struct dpu_sw_pipe *pipe; 1193 struct dpu_sw_pipe *r_pipe; 1194 struct dpu_sw_pipe_cfg *pipe_cfg; 1195 struct dpu_sw_pipe_cfg *r_pipe_cfg; 1196 const struct msm_format *fmt; 1197 1198 if (plane_state->crtc) 1199 crtc_state = drm_atomic_get_new_crtc_state(state, 1200 plane_state->crtc); 1201 1202 pstate = to_dpu_plane_state(plane_state); 1203 prev_adjacent_pstate = prev_adjacent_plane_state ? 1204 to_dpu_plane_state(prev_adjacent_plane_state) : NULL; 1205 pipe = &pstate->pipe; 1206 r_pipe = &pstate->r_pipe; 1207 pipe_cfg = &pstate->pipe_cfg; 1208 r_pipe_cfg = &pstate->r_pipe_cfg; 1209 1210 pipe->sspp = NULL; 1211 r_pipe->sspp = NULL; 1212 1213 if (!plane_state->fb) 1214 return -EINVAL; 1215 1216 fmt = msm_framebuffer_format(plane_state->fb); 1217 reqs.yuv = MSM_FORMAT_IS_YUV(fmt); 1218 reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) || 1219 (plane_state->src_h >> 16 != plane_state->crtc_h); 1220 1221 reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); 1222 1223 if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { 1224 if (!prev_adjacent_pstate || 1225 !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, 1226 dpu_kms->catalog->caps->max_linewidth)) { 1227 pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1228 if (!pipe->sspp) 1229 return -ENODEV; 1230 1231 r_pipe->sspp = NULL; 1232 1233 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1234 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1235 1236 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1237 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1238 } 1239 } else { 1240 pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1241 if (!pipe->sspp) 1242 return -ENODEV; 1243 1244 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1245 pipe->sspp, 1246 msm_framebuffer_format(plane_state->fb), 1247 dpu_kms->catalog->caps->max_linewidth)) { 1248 /* multirect is not possible, use two SSPP blocks */ 1249 r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1250 if (!r_pipe->sspp) 1251 return -ENODEV; 1252 1253 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1254 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1255 1256 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1257 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1258 } 1259 } 1260 1261 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1262 } 1263 1264 int dpu_assign_plane_resources(struct dpu_global_state *global_state, 1265 struct drm_atomic_state *state, 1266 struct drm_crtc *crtc, 1267 struct drm_plane_state **states, 1268 unsigned int num_planes) 1269 { 1270 unsigned int i; 1271 struct drm_plane_state *prev_adjacent_plane_state = NULL; 1272 1273 for (i = 0; i < num_planes; i++) { 1274 struct drm_plane_state *plane_state = states[i]; 1275 1276 if (!plane_state || 1277 !plane_state->visible) 1278 continue; 1279 1280 int ret = dpu_plane_virtual_assign_resources(crtc, global_state, 1281 state, plane_state, 1282 prev_adjacent_plane_state); 1283 if (ret) 1284 break; 1285 1286 prev_adjacent_plane_state = plane_state; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 1293 { 1294 const struct msm_format *format = 1295 msm_framebuffer_format(pdpu->base.state->fb); 1296 const struct dpu_csc_cfg *csc_ptr; 1297 1298 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 1299 return; 1300 1301 csc_ptr = _dpu_plane_get_csc(pipe, format); 1302 if (!csc_ptr) 1303 return; 1304 1305 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 1306 csc_ptr->csc_mv[0], 1307 csc_ptr->csc_mv[1], 1308 csc_ptr->csc_mv[2]); 1309 1310 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 1311 1312 } 1313 1314 /** 1315 * dpu_plane_flush - final plane operations before commit flush 1316 * @plane: Pointer to drm plane structure 1317 */ 1318 void dpu_plane_flush(struct drm_plane *plane) 1319 { 1320 struct dpu_plane *pdpu; 1321 struct dpu_plane_state *pstate; 1322 1323 if (!plane || !plane->state) { 1324 DPU_ERROR("invalid plane\n"); 1325 return; 1326 } 1327 1328 pdpu = to_dpu_plane(plane); 1329 pstate = to_dpu_plane_state(plane->state); 1330 1331 /* 1332 * These updates have to be done immediately before the plane flush 1333 * timing, and may not be moved to the atomic_update/mode_set functions. 1334 */ 1335 if (pdpu->is_error) 1336 /* force white frame with 100% alpha pipe output on error */ 1337 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1338 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1339 /* force 100% alpha */ 1340 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1341 else { 1342 dpu_plane_flush_csc(pdpu, &pstate->pipe); 1343 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 1344 } 1345 1346 /* flag h/w flush complete */ 1347 if (plane->state) 1348 pstate->pending = false; 1349 } 1350 1351 /** 1352 * dpu_plane_set_error: enable/disable error condition 1353 * @plane: pointer to drm_plane structure 1354 * @error: error value to set 1355 */ 1356 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1357 { 1358 struct dpu_plane *pdpu; 1359 1360 if (!plane) 1361 return; 1362 1363 pdpu = to_dpu_plane(plane); 1364 pdpu->is_error = error; 1365 } 1366 1367 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1368 struct dpu_sw_pipe *pipe, 1369 struct dpu_sw_pipe_cfg *pipe_cfg, 1370 const struct msm_format *fmt, 1371 int frame_rate, 1372 struct dpu_hw_fmt_layout *layout) 1373 { 1374 uint32_t src_flags; 1375 struct dpu_plane *pdpu = to_dpu_plane(plane); 1376 struct drm_plane_state *state = plane->state; 1377 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1378 1379 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1380 trace_dpu_plane_set_scanout(pipe, layout); 1381 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1382 } 1383 1384 /* override for color fill */ 1385 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1386 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1387 1388 /* skip remaining processing on color fill */ 1389 return; 1390 } 1391 1392 if (pipe->sspp->ops.setup_rects) { 1393 pipe->sspp->ops.setup_rects(pipe, 1394 pipe_cfg); 1395 } 1396 1397 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); 1398 1399 if (pipe->sspp->ops.setup_multirect) 1400 pipe->sspp->ops.setup_multirect( 1401 pipe); 1402 1403 if (pipe->sspp->ops.setup_format) { 1404 unsigned int rotation = pipe_cfg->rotation; 1405 1406 src_flags = 0x0; 1407 1408 if (rotation & DRM_MODE_REFLECT_X) 1409 src_flags |= DPU_SSPP_FLIP_LR; 1410 1411 if (rotation & DRM_MODE_REFLECT_Y) 1412 src_flags |= DPU_SSPP_FLIP_UD; 1413 1414 if (rotation & DRM_MODE_ROTATE_90) 1415 src_flags |= DPU_SSPP_ROT_90; 1416 1417 /* update format */ 1418 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1419 1420 if (pipe->sspp->ops.setup_cdp) { 1421 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1422 1423 pipe->sspp->ops.setup_cdp(pipe, fmt, 1424 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1425 } 1426 } 1427 1428 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1429 1430 if (pipe->sspp->idx != SSPP_CURSOR0 && 1431 pipe->sspp->idx != SSPP_CURSOR1) 1432 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1433 1434 if (pstate->needs_qos_remap) 1435 _dpu_plane_set_qos_remap(plane, pipe); 1436 } 1437 1438 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, 1439 struct drm_plane_state *new_state) 1440 { 1441 struct dpu_plane *pdpu = to_dpu_plane(plane); 1442 struct drm_plane_state *state = plane->state; 1443 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1444 struct dpu_sw_pipe *pipe = &pstate->pipe; 1445 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1446 struct drm_crtc *crtc = state->crtc; 1447 struct drm_framebuffer *fb = state->fb; 1448 bool is_rt_pipe; 1449 const struct msm_format *fmt = 1450 msm_framebuffer_format(fb); 1451 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1452 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1453 1454 pstate->pending = true; 1455 1456 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1457 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1458 pdpu->is_rt_pipe = is_rt_pipe; 1459 1460 dpu_format_populate_addrs(pstate->aspace, new_state->fb, &pstate->layout); 1461 1462 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1463 ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1464 crtc->base.id, DRM_RECT_ARG(&state->dst), 1465 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); 1466 1467 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1468 drm_mode_vrefresh(&crtc->mode), 1469 &pstate->layout); 1470 1471 if (r_pipe->sspp) { 1472 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1473 drm_mode_vrefresh(&crtc->mode), 1474 &pstate->layout); 1475 } 1476 1477 if (pstate->needs_qos_remap) 1478 pstate->needs_qos_remap = false; 1479 1480 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1481 &crtc->mode, pipe_cfg); 1482 1483 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1484 1485 if (r_pipe->sspp) { 1486 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1487 1488 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1489 } 1490 } 1491 1492 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1493 { 1494 struct drm_plane_state *state = plane->state; 1495 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1496 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1497 1498 trace_dpu_plane_disable(DRMID(plane), false, 1499 pstate->pipe.multirect_mode); 1500 1501 if (r_pipe->sspp) { 1502 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1503 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1504 1505 if (r_pipe->sspp->ops.setup_multirect) 1506 r_pipe->sspp->ops.setup_multirect(r_pipe); 1507 } 1508 1509 pstate->pending = true; 1510 } 1511 1512 static void dpu_plane_atomic_update(struct drm_plane *plane, 1513 struct drm_atomic_state *state) 1514 { 1515 struct dpu_plane *pdpu = to_dpu_plane(plane); 1516 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1517 plane); 1518 1519 pdpu->is_error = false; 1520 1521 DPU_DEBUG_PLANE(pdpu, "\n"); 1522 1523 if (!new_state->visible) { 1524 _dpu_plane_atomic_disable(plane); 1525 } else { 1526 dpu_plane_sspp_atomic_update(plane, new_state); 1527 } 1528 } 1529 1530 static void dpu_plane_destroy_state(struct drm_plane *plane, 1531 struct drm_plane_state *state) 1532 { 1533 __drm_atomic_helper_plane_destroy_state(state); 1534 kfree(to_dpu_plane_state(state)); 1535 } 1536 1537 static struct drm_plane_state * 1538 dpu_plane_duplicate_state(struct drm_plane *plane) 1539 { 1540 struct dpu_plane *pdpu; 1541 struct dpu_plane_state *pstate; 1542 struct dpu_plane_state *old_state; 1543 1544 if (!plane) { 1545 DPU_ERROR("invalid plane\n"); 1546 return NULL; 1547 } else if (!plane->state) { 1548 DPU_ERROR("invalid plane state\n"); 1549 return NULL; 1550 } 1551 1552 old_state = to_dpu_plane_state(plane->state); 1553 pdpu = to_dpu_plane(plane); 1554 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1555 if (!pstate) { 1556 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1557 return NULL; 1558 } 1559 1560 DPU_DEBUG_PLANE(pdpu, "\n"); 1561 1562 pstate->pending = false; 1563 1564 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1565 1566 return &pstate->base; 1567 } 1568 1569 static const char * const multirect_mode_name[] = { 1570 [DPU_SSPP_MULTIRECT_NONE] = "none", 1571 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1572 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1573 }; 1574 1575 static const char * const multirect_index_name[] = { 1576 [DPU_SSPP_RECT_SOLO] = "solo", 1577 [DPU_SSPP_RECT_0] = "rect_0", 1578 [DPU_SSPP_RECT_1] = "rect_1", 1579 }; 1580 1581 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1582 { 1583 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1584 return "unknown"; 1585 1586 return multirect_mode_name[mode]; 1587 } 1588 1589 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1590 { 1591 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1592 return "unknown"; 1593 1594 return multirect_index_name[index]; 1595 } 1596 1597 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1598 const struct drm_plane_state *state) 1599 { 1600 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1601 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1602 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1603 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1604 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1605 1606 drm_printf(p, "\tstage=%d\n", pstate->stage); 1607 1608 if (pipe->sspp) { 1609 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1610 drm_printf(p, "\tmultirect_mode[0]=%s\n", 1611 dpu_get_multirect_mode(pipe->multirect_mode)); 1612 drm_printf(p, "\tmultirect_index[0]=%s\n", 1613 dpu_get_multirect_index(pipe->multirect_index)); 1614 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1615 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1616 } 1617 1618 if (r_pipe->sspp) { 1619 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1620 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1621 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1622 drm_printf(p, "\tmultirect_index[1]=%s\n", 1623 dpu_get_multirect_index(r_pipe->multirect_index)); 1624 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1625 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1626 } 1627 } 1628 1629 static void dpu_plane_reset(struct drm_plane *plane) 1630 { 1631 struct dpu_plane *pdpu; 1632 struct dpu_plane_state *pstate; 1633 1634 if (!plane) { 1635 DPU_ERROR("invalid plane\n"); 1636 return; 1637 } 1638 1639 pdpu = to_dpu_plane(plane); 1640 DPU_DEBUG_PLANE(pdpu, "\n"); 1641 1642 /* remove previous state, if present */ 1643 if (plane->state) { 1644 dpu_plane_destroy_state(plane, plane->state); 1645 plane->state = NULL; 1646 } 1647 1648 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1649 if (!pstate) { 1650 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1651 return; 1652 } 1653 1654 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1655 } 1656 1657 #ifdef CONFIG_DEBUG_FS 1658 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1659 { 1660 struct dpu_plane *pdpu = to_dpu_plane(plane); 1661 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1662 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1663 1664 if (!pdpu->is_rt_pipe) 1665 return; 1666 1667 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1668 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1669 if (pstate->r_pipe.sspp) 1670 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1671 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1672 } 1673 #endif 1674 1675 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1676 uint32_t format, uint64_t modifier) 1677 { 1678 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1679 bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0) && 1680 (dpu_kms->mdss->ubwc_dec_version == 0); 1681 1682 if (modifier == DRM_FORMAT_MOD_LINEAR) 1683 return true; 1684 1685 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc) 1686 return dpu_find_format(format, qcom_compressed_supported_formats, 1687 ARRAY_SIZE(qcom_compressed_supported_formats)); 1688 1689 return false; 1690 } 1691 1692 static const struct drm_plane_funcs dpu_plane_funcs = { 1693 .update_plane = drm_atomic_helper_update_plane, 1694 .disable_plane = drm_atomic_helper_disable_plane, 1695 .reset = dpu_plane_reset, 1696 .atomic_duplicate_state = dpu_plane_duplicate_state, 1697 .atomic_destroy_state = dpu_plane_destroy_state, 1698 .atomic_print_state = dpu_plane_atomic_print_state, 1699 .format_mod_supported = dpu_plane_format_mod_supported, 1700 }; 1701 1702 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1703 .prepare_fb = dpu_plane_prepare_fb, 1704 .cleanup_fb = dpu_plane_cleanup_fb, 1705 .atomic_check = dpu_plane_atomic_check, 1706 .atomic_update = dpu_plane_atomic_update, 1707 }; 1708 1709 static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { 1710 .prepare_fb = dpu_plane_prepare_fb, 1711 .cleanup_fb = dpu_plane_cleanup_fb, 1712 .atomic_check = dpu_plane_virtual_atomic_check, 1713 .atomic_update = dpu_plane_atomic_update, 1714 }; 1715 1716 /* initialize plane */ 1717 static struct drm_plane *dpu_plane_init_common(struct drm_device *dev, 1718 enum drm_plane_type type, 1719 unsigned long possible_crtcs, 1720 bool inline_rotation, 1721 const uint32_t *format_list, 1722 uint32_t num_formats, 1723 enum dpu_sspp pipe) 1724 { 1725 struct drm_plane *plane = NULL; 1726 struct dpu_plane *pdpu; 1727 struct msm_drm_private *priv = dev->dev_private; 1728 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1729 uint32_t supported_rotations; 1730 int ret; 1731 1732 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 1733 0xff, &dpu_plane_funcs, 1734 format_list, num_formats, 1735 supported_format_modifiers, type, NULL); 1736 if (IS_ERR(pdpu)) 1737 return ERR_CAST(pdpu); 1738 1739 /* cache local stuff for later */ 1740 plane = &pdpu->base; 1741 pdpu->pipe = pipe; 1742 1743 pdpu->catalog = kms->catalog; 1744 1745 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1746 if (ret) 1747 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1748 1749 drm_plane_create_alpha_property(plane); 1750 drm_plane_create_blend_mode_property(plane, 1751 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1752 BIT(DRM_MODE_BLEND_PREMULTI) | 1753 BIT(DRM_MODE_BLEND_COVERAGE)); 1754 1755 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1756 1757 if (inline_rotation) 1758 supported_rotations |= DRM_MODE_ROTATE_MASK; 1759 1760 drm_plane_create_rotation_property(plane, 1761 DRM_MODE_ROTATE_0, supported_rotations); 1762 1763 drm_plane_enable_fb_damage_clips(plane); 1764 1765 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1766 pipe, plane->base.id); 1767 return plane; 1768 } 1769 1770 /** 1771 * dpu_plane_init - create new dpu plane for the given pipe 1772 * @dev: Pointer to DRM device 1773 * @pipe: dpu hardware pipe identifier 1774 * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1775 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1776 * 1777 * Initialize the plane. 1778 */ 1779 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1780 uint32_t pipe, enum drm_plane_type type, 1781 unsigned long possible_crtcs) 1782 { 1783 struct drm_plane *plane = NULL; 1784 struct msm_drm_private *priv = dev->dev_private; 1785 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1786 struct dpu_hw_sspp *pipe_hw; 1787 1788 /* initialize underlying h/w driver */ 1789 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1790 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1791 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1792 return ERR_PTR(-EINVAL); 1793 } 1794 1795 1796 plane = dpu_plane_init_common(dev, type, possible_crtcs, 1797 pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION), 1798 pipe_hw->cap->sblk->format_list, 1799 pipe_hw->cap->sblk->num_formats, 1800 pipe); 1801 if (IS_ERR(plane)) 1802 return plane; 1803 1804 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1805 1806 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1807 pipe, plane->base.id); 1808 1809 return plane; 1810 } 1811 1812 /** 1813 * dpu_plane_init_virtual - create new virtualized DPU plane 1814 * @dev: Pointer to DRM device 1815 * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1816 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1817 * 1818 * Initialize the virtual plane with no backing SSPP / pipe. 1819 */ 1820 struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, 1821 enum drm_plane_type type, 1822 unsigned long possible_crtcs) 1823 { 1824 struct drm_plane *plane = NULL; 1825 struct msm_drm_private *priv = dev->dev_private; 1826 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1827 bool has_inline_rotation = false; 1828 const u32 *format_list = NULL; 1829 u32 num_formats = 0; 1830 int i; 1831 1832 /* Determine the largest configuration that we can implement */ 1833 for (i = 0; i < kms->catalog->sspp_count; i++) { 1834 const struct dpu_sspp_cfg *cfg = &kms->catalog->sspp[i]; 1835 1836 if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features)) 1837 has_inline_rotation = true; 1838 1839 if (!format_list || 1840 cfg->sblk->csc_blk.len) { 1841 format_list = cfg->sblk->format_list; 1842 num_formats = cfg->sblk->num_formats; 1843 } 1844 } 1845 1846 plane = dpu_plane_init_common(dev, type, possible_crtcs, 1847 has_inline_rotation, 1848 format_list, 1849 num_formats, 1850 SSPP_NONE); 1851 if (IS_ERR(plane)) 1852 return plane; 1853 1854 drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs); 1855 1856 DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id); 1857 1858 return plane; 1859 } 1860