1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_damage_helper.h> 16 #include <drm/drm_file.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 19 #include "msm_drv.h" 20 #include "dpu_kms.h" 21 #include "dpu_formats.h" 22 #include "dpu_hw_sspp.h" 23 #include "dpu_trace.h" 24 #include "dpu_crtc.h" 25 #include "dpu_vbif.h" 26 #include "dpu_plane.h" 27 28 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 30 31 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 33 34 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 35 #define PHASE_STEP_SHIFT 21 36 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 37 #define PHASE_RESIDUAL 15 38 39 #define SHARP_STRENGTH_DEFAULT 32 40 #define SHARP_EDGE_THR_DEFAULT 112 41 #define SHARP_SMOOTH_THR_DEFAULT 8 42 #define SHARP_NOISE_THR_DEFAULT 2 43 44 #define DPU_NAME_SIZE 12 45 46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 47 #define DPU_ZPOS_MAX 255 48 49 /* multirect rect index */ 50 enum { 51 R0, 52 R1, 53 R_MAX 54 }; 55 56 /* 57 * Default Preload Values 58 */ 59 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 60 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 61 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 62 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 63 64 #define DEFAULT_REFRESH_RATE 60 65 66 static const uint32_t qcom_compressed_supported_formats[] = { 67 DRM_FORMAT_ABGR8888, 68 DRM_FORMAT_ARGB8888, 69 DRM_FORMAT_XBGR8888, 70 DRM_FORMAT_XRGB8888, 71 DRM_FORMAT_BGR565, 72 73 DRM_FORMAT_NV12, 74 }; 75 76 /** 77 * enum dpu_plane_qos - Different qos configurations for each pipe 78 * 79 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 80 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 81 * this configuration is mutually exclusive from VBLANK_CTRL. 82 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 83 */ 84 enum dpu_plane_qos { 85 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 86 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 87 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 88 }; 89 90 /* 91 * struct dpu_plane - local dpu plane structure 92 * @aspace: address space pointer 93 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 94 * @mplane_list: List of multirect planes of the same pipe 95 * @catalog: Points to dpu catalog structure 96 * @revalidate: force revalidation of all the plane properties 97 */ 98 struct dpu_plane { 99 struct drm_plane base; 100 101 struct mutex lock; 102 103 enum dpu_sspp pipe; 104 uint32_t features; /* capabilities from catalog */ 105 106 struct dpu_hw_pipe *pipe_hw; 107 struct dpu_hw_pipe_cfg pipe_cfg; 108 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 109 uint32_t color_fill; 110 bool is_error; 111 bool is_rt_pipe; 112 bool is_virtual; 113 struct list_head mplane_list; 114 struct dpu_mdss_cfg *catalog; 115 116 struct dpu_csc_cfg *csc_ptr; 117 118 const struct dpu_sspp_sub_blks *pipe_sblk; 119 char pipe_name[DPU_NAME_SIZE]; 120 121 /* debugfs related stuff */ 122 struct dentry *debugfs_root; 123 struct dpu_debugfs_regset32 debugfs_src; 124 struct dpu_debugfs_regset32 debugfs_scaler; 125 struct dpu_debugfs_regset32 debugfs_csc; 126 bool debugfs_default_scale; 127 }; 128 129 static const uint64_t supported_format_modifiers[] = { 130 DRM_FORMAT_MOD_QCOM_COMPRESSED, 131 DRM_FORMAT_MOD_LINEAR, 132 DRM_FORMAT_MOD_INVALID 133 }; 134 135 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 136 137 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 138 { 139 struct msm_drm_private *priv = plane->dev->dev_private; 140 141 return to_dpu_kms(priv->kms); 142 } 143 144 /** 145 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 146 * @plane: Pointer to drm plane. 147 * @fb: Pointer to framebuffer associated with the given plane 148 * Result: Updates calculated bandwidth in the plane state. 149 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 150 * Prefill BW Equation: line src bytes * line_time 151 */ 152 static void _dpu_plane_calc_bw(struct drm_plane *plane, 153 struct drm_framebuffer *fb) 154 { 155 struct dpu_plane *pdpu = to_dpu_plane(plane); 156 struct dpu_plane_state *pstate; 157 struct drm_display_mode *mode; 158 const struct dpu_format *fmt = NULL; 159 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 160 int src_width, src_height, dst_height, fps; 161 u64 plane_prefill_bw; 162 u64 plane_bw; 163 u32 hw_latency_lines; 164 u64 scale_factor; 165 int vbp, vpw, vfp; 166 167 pstate = to_dpu_plane_state(plane->state); 168 mode = &plane->state->crtc->mode; 169 170 fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); 171 172 src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 173 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 174 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); 175 fps = drm_mode_vrefresh(mode); 176 vbp = mode->vtotal - mode->vsync_end; 177 vpw = mode->vsync_end - mode->vsync_start; 178 vfp = mode->vsync_start - mode->vdisplay; 179 hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; 180 scale_factor = src_height > dst_height ? 181 mult_frac(src_height, 1, dst_height) : 1; 182 183 plane_bw = 184 src_width * mode->vtotal * fps * fmt->bpp * 185 scale_factor; 186 187 plane_prefill_bw = 188 src_width * hw_latency_lines * fps * fmt->bpp * 189 scale_factor * mode->vtotal; 190 191 if ((vbp+vpw) > hw_latency_lines) 192 do_div(plane_prefill_bw, (vbp+vpw)); 193 else if ((vbp+vpw+vfp) < hw_latency_lines) 194 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 195 else 196 do_div(plane_prefill_bw, hw_latency_lines); 197 198 199 pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); 200 } 201 202 /** 203 * _dpu_plane_calc_clk - calculate clock required for a plane 204 * @plane: Pointer to drm plane. 205 * Result: Updates calculated clock in the plane state. 206 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 207 */ 208 static void _dpu_plane_calc_clk(struct drm_plane *plane) 209 { 210 struct dpu_plane *pdpu = to_dpu_plane(plane); 211 struct dpu_plane_state *pstate; 212 struct drm_display_mode *mode; 213 int dst_width, src_height, dst_height, fps; 214 215 pstate = to_dpu_plane_state(plane->state); 216 mode = &plane->state->crtc->mode; 217 218 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 219 dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect); 220 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); 221 fps = drm_mode_vrefresh(mode); 222 223 pstate->plane_clk = 224 dst_width * mode->vtotal * fps; 225 226 if (src_height > dst_height) { 227 pstate->plane_clk *= src_height; 228 do_div(pstate->plane_clk, dst_height); 229 } 230 } 231 232 /** 233 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 234 * @plane: Pointer to drm plane 235 * @fmt: Pointer to source buffer format 236 * @src_width: width of source buffer 237 * Return: fill level corresponding to the source buffer/format or 0 if error 238 */ 239 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 240 const struct dpu_format *fmt, u32 src_width) 241 { 242 struct dpu_plane *pdpu, *tmp; 243 struct dpu_plane_state *pstate; 244 u32 fixed_buff_size; 245 u32 total_fl; 246 247 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 248 DPU_ERROR("invalid arguments\n"); 249 return 0; 250 } 251 252 pdpu = to_dpu_plane(plane); 253 pstate = to_dpu_plane_state(plane->state); 254 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 255 256 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 257 if (!tmp->base.state->visible) 258 continue; 259 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 260 pdpu->base.base.id, tmp->base.base.id, 261 src_width, 262 drm_rect_width(&tmp->pipe_cfg.src_rect)); 263 src_width = max_t(u32, src_width, 264 drm_rect_width(&tmp->pipe_cfg.src_rect)); 265 } 266 267 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 268 if (fmt->chroma_sample == DPU_CHROMA_420) { 269 /* NV12 */ 270 total_fl = (fixed_buff_size / 2) / 271 ((src_width + 32) * fmt->bpp); 272 } else { 273 /* non NV12 */ 274 total_fl = (fixed_buff_size / 2) * 2 / 275 ((src_width + 32) * fmt->bpp); 276 } 277 } else { 278 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 279 total_fl = (fixed_buff_size / 2) * 2 / 280 ((src_width + 32) * fmt->bpp); 281 } else { 282 total_fl = (fixed_buff_size) * 2 / 283 ((src_width + 32) * fmt->bpp); 284 } 285 } 286 287 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 288 pdpu->pipe - SSPP_VIG0, 289 (char *)&fmt->base.pixel_format, 290 src_width, total_fl); 291 292 return total_fl; 293 } 294 295 /** 296 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level 297 * @tbl: Pointer to LUT table 298 * @total_fl: fill level 299 * Return: LUT setting corresponding to the fill level 300 */ 301 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 302 u32 total_fl) 303 { 304 int i; 305 306 if (!tbl || !tbl->nentry || !tbl->entries) 307 return 0; 308 309 for (i = 0; i < tbl->nentry; i++) 310 if (total_fl <= tbl->entries[i].fl) 311 return tbl->entries[i].lut; 312 313 /* if last fl is zero, use as default */ 314 if (!tbl->entries[i-1].fl) 315 return tbl->entries[i-1].lut; 316 317 return 0; 318 } 319 320 /** 321 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 322 * @plane: Pointer to drm plane 323 * @fb: Pointer to framebuffer associated with the given plane 324 */ 325 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 326 struct drm_framebuffer *fb) 327 { 328 struct dpu_plane *pdpu = to_dpu_plane(plane); 329 const struct dpu_format *fmt = NULL; 330 u64 qos_lut; 331 u32 total_fl = 0, lut_usage; 332 333 if (!pdpu->is_rt_pipe) { 334 lut_usage = DPU_QOS_LUT_USAGE_NRT; 335 } else { 336 fmt = dpu_get_dpu_format_ext( 337 fb->format->format, 338 fb->modifier); 339 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 340 drm_rect_width(&pdpu->pipe_cfg.src_rect)); 341 342 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 343 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 344 else 345 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 346 } 347 348 qos_lut = _dpu_plane_get_qos_lut( 349 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); 350 351 pdpu->pipe_qos_cfg.creq_lut = qos_lut; 352 353 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 354 (fmt) ? fmt->base.pixel_format : 0, 355 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 356 357 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 358 pdpu->pipe - SSPP_VIG0, 359 fmt ? (char *)&fmt->base.pixel_format : NULL, 360 pdpu->is_rt_pipe, total_fl, qos_lut); 361 362 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); 363 } 364 365 /** 366 * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane 367 * @plane: Pointer to drm plane 368 * @fb: Pointer to framebuffer associated with the given plane 369 */ 370 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 371 struct drm_framebuffer *fb) 372 { 373 struct dpu_plane *pdpu = to_dpu_plane(plane); 374 const struct dpu_format *fmt = NULL; 375 u32 danger_lut, safe_lut; 376 377 if (!pdpu->is_rt_pipe) { 378 danger_lut = pdpu->catalog->perf.danger_lut_tbl 379 [DPU_QOS_LUT_USAGE_NRT]; 380 safe_lut = pdpu->catalog->perf.safe_lut_tbl 381 [DPU_QOS_LUT_USAGE_NRT]; 382 } else { 383 fmt = dpu_get_dpu_format_ext( 384 fb->format->format, 385 fb->modifier); 386 387 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 388 danger_lut = pdpu->catalog->perf.danger_lut_tbl 389 [DPU_QOS_LUT_USAGE_LINEAR]; 390 safe_lut = pdpu->catalog->perf.safe_lut_tbl 391 [DPU_QOS_LUT_USAGE_LINEAR]; 392 } else { 393 danger_lut = pdpu->catalog->perf.danger_lut_tbl 394 [DPU_QOS_LUT_USAGE_MACROTILE]; 395 safe_lut = pdpu->catalog->perf.safe_lut_tbl 396 [DPU_QOS_LUT_USAGE_MACROTILE]; 397 } 398 } 399 400 pdpu->pipe_qos_cfg.danger_lut = danger_lut; 401 pdpu->pipe_qos_cfg.safe_lut = safe_lut; 402 403 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 404 (fmt) ? fmt->base.pixel_format : 0, 405 (fmt) ? fmt->fetch_mode : 0, 406 pdpu->pipe_qos_cfg.danger_lut, 407 pdpu->pipe_qos_cfg.safe_lut); 408 409 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 410 pdpu->pipe - SSPP_VIG0, 411 fmt ? (char *)&fmt->base.pixel_format : NULL, 412 fmt ? fmt->fetch_mode : -1, 413 pdpu->pipe_qos_cfg.danger_lut, 414 pdpu->pipe_qos_cfg.safe_lut); 415 416 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 417 &pdpu->pipe_qos_cfg); 418 } 419 420 /** 421 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 422 * @plane: Pointer to drm plane 423 * @enable: true to enable QoS control 424 * @flags: QoS control mode (enum dpu_plane_qos) 425 */ 426 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 427 bool enable, u32 flags) 428 { 429 struct dpu_plane *pdpu = to_dpu_plane(plane); 430 431 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 432 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; 433 pdpu->pipe_qos_cfg.danger_vblank = 434 pdpu->pipe_sblk->danger_vblank; 435 pdpu->pipe_qos_cfg.vblank_en = enable; 436 } 437 438 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 439 /* this feature overrules previous VBLANK_CTRL */ 440 pdpu->pipe_qos_cfg.vblank_en = false; 441 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 442 } 443 444 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 445 pdpu->pipe_qos_cfg.danger_safe_en = enable; 446 447 if (!pdpu->is_rt_pipe) { 448 pdpu->pipe_qos_cfg.vblank_en = false; 449 pdpu->pipe_qos_cfg.danger_safe_en = false; 450 } 451 452 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 453 pdpu->pipe - SSPP_VIG0, 454 pdpu->pipe_qos_cfg.danger_safe_en, 455 pdpu->pipe_qos_cfg.vblank_en, 456 pdpu->pipe_qos_cfg.creq_vblank, 457 pdpu->pipe_qos_cfg.danger_vblank, 458 pdpu->is_rt_pipe); 459 460 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 461 &pdpu->pipe_qos_cfg); 462 } 463 464 /** 465 * _dpu_plane_set_ot_limit - set OT limit for the given plane 466 * @plane: Pointer to drm plane 467 * @crtc: Pointer to drm crtc 468 */ 469 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 470 struct drm_crtc *crtc) 471 { 472 struct dpu_plane *pdpu = to_dpu_plane(plane); 473 struct dpu_vbif_set_ot_params ot_params; 474 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 475 476 memset(&ot_params, 0, sizeof(ot_params)); 477 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 478 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 479 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 480 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 481 ot_params.is_wfd = !pdpu->is_rt_pipe; 482 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 483 ot_params.vbif_idx = VBIF_RT; 484 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 485 ot_params.rd = true; 486 487 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 488 } 489 490 /** 491 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 492 * @plane: Pointer to drm plane 493 */ 494 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 495 { 496 struct dpu_plane *pdpu = to_dpu_plane(plane); 497 struct dpu_vbif_set_qos_params qos_params; 498 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 499 500 memset(&qos_params, 0, sizeof(qos_params)); 501 qos_params.vbif_idx = VBIF_RT; 502 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 503 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 504 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 505 qos_params.is_rt = pdpu->is_rt_pipe; 506 507 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 508 qos_params.num, 509 qos_params.vbif_idx, 510 qos_params.xin_id, qos_params.is_rt, 511 qos_params.clk_ctrl); 512 513 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 514 } 515 516 static void _dpu_plane_set_scanout(struct drm_plane *plane, 517 struct dpu_plane_state *pstate, 518 struct dpu_hw_pipe_cfg *pipe_cfg, 519 struct drm_framebuffer *fb) 520 { 521 struct dpu_plane *pdpu = to_dpu_plane(plane); 522 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 523 struct msm_gem_address_space *aspace = kms->base.aspace; 524 int ret; 525 526 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 527 if (ret == -EAGAIN) 528 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 529 else if (ret) 530 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 531 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 532 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 533 &pipe_cfg->layout, 534 pstate->multirect_index); 535 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 536 pstate->multirect_index); 537 } 538 } 539 540 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 541 struct dpu_plane_state *pstate, 542 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 543 struct dpu_hw_scaler3_cfg *scale_cfg, 544 const struct dpu_format *fmt, 545 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 546 { 547 uint32_t i; 548 549 memset(scale_cfg, 0, sizeof(*scale_cfg)); 550 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); 551 552 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 553 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 554 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 555 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 556 557 558 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 559 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 560 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 561 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 562 563 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 564 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 565 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 566 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 567 568 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 569 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 570 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 571 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 572 573 for (i = 0; i < DPU_MAX_PLANES; i++) { 574 scale_cfg->src_width[i] = src_w; 575 scale_cfg->src_height[i] = src_h; 576 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 577 scale_cfg->src_width[i] /= chroma_subsmpl_h; 578 scale_cfg->src_height[i] /= chroma_subsmpl_v; 579 } 580 581 if (pdpu->pipe_hw->cap->features & 582 BIT(DPU_SSPP_SCALER_QSEED4)) { 583 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 584 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 585 } else { 586 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 587 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 588 } 589 590 pstate->pixel_ext.num_ext_pxls_top[i] = 591 scale_cfg->src_height[i]; 592 pstate->pixel_ext.num_ext_pxls_left[i] = 593 scale_cfg->src_width[i]; 594 } 595 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 596 && (src_w == dst_w)) 597 return; 598 599 scale_cfg->dst_width = dst_w; 600 scale_cfg->dst_height = dst_h; 601 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 602 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 603 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 604 scale_cfg->lut_flag = 0; 605 scale_cfg->blend_cfg = 1; 606 scale_cfg->enable = 1; 607 } 608 609 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) 610 { 611 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 612 { 613 /* S15.16 format */ 614 0x00012A00, 0x00000000, 0x00019880, 615 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 616 0x00012A00, 0x00020480, 0x00000000, 617 }, 618 /* signed bias */ 619 { 0xfff0, 0xff80, 0xff80,}, 620 { 0x0, 0x0, 0x0,}, 621 /* unsigned clamp */ 622 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 623 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 624 }; 625 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 626 { 627 /* S15.16 format */ 628 0x00012A00, 0x00000000, 0x00019880, 629 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 630 0x00012A00, 0x00020480, 0x00000000, 631 }, 632 /* signed bias */ 633 { 0xffc0, 0xfe00, 0xfe00,}, 634 { 0x0, 0x0, 0x0,}, 635 /* unsigned clamp */ 636 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 637 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 638 }; 639 640 if (!pdpu) { 641 DPU_ERROR("invalid plane\n"); 642 return; 643 } 644 645 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) 646 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; 647 else 648 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; 649 650 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 651 pdpu->csc_ptr->csc_mv[0], 652 pdpu->csc_ptr->csc_mv[1], 653 pdpu->csc_ptr->csc_mv[2]); 654 } 655 656 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 657 struct dpu_plane_state *pstate, 658 const struct dpu_format *fmt, bool color_fill) 659 { 660 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 661 662 /* don't chroma subsample if decimating */ 663 /* update scaler. calculate default config for QSEED3 */ 664 _dpu_plane_setup_scaler3(pdpu, pstate, 665 drm_rect_width(&pdpu->pipe_cfg.src_rect), 666 drm_rect_height(&pdpu->pipe_cfg.src_rect), 667 drm_rect_width(&pdpu->pipe_cfg.dst_rect), 668 drm_rect_height(&pdpu->pipe_cfg.dst_rect), 669 &pstate->scaler3_cfg, fmt, 670 info->hsub, info->vsub); 671 } 672 673 /** 674 * _dpu_plane_color_fill - enables color fill on plane 675 * @pdpu: Pointer to DPU plane object 676 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 677 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 678 * Returns: 0 on success 679 */ 680 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 681 uint32_t color, uint32_t alpha) 682 { 683 const struct dpu_format *fmt; 684 const struct drm_plane *plane = &pdpu->base; 685 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 686 687 DPU_DEBUG_PLANE(pdpu, "\n"); 688 689 /* 690 * select fill format to match user property expectation, 691 * h/w only supports RGB variants 692 */ 693 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 694 695 /* update sspp */ 696 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 697 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 698 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 699 pstate->multirect_index); 700 701 /* override scaler/decimation if solid fill */ 702 pdpu->pipe_cfg.src_rect.x1 = 0; 703 pdpu->pipe_cfg.src_rect.y1 = 0; 704 pdpu->pipe_cfg.src_rect.x2 = 705 drm_rect_width(&pdpu->pipe_cfg.dst_rect); 706 pdpu->pipe_cfg.src_rect.y2 = 707 drm_rect_height(&pdpu->pipe_cfg.dst_rect); 708 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); 709 710 if (pdpu->pipe_hw->ops.setup_format) 711 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 712 fmt, DPU_SSPP_SOLID_FILL, 713 pstate->multirect_index); 714 715 if (pdpu->pipe_hw->ops.setup_rects) 716 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 717 &pdpu->pipe_cfg, 718 pstate->multirect_index); 719 720 if (pdpu->pipe_hw->ops.setup_pe) 721 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 722 &pstate->pixel_ext); 723 724 if (pdpu->pipe_hw->ops.setup_scaler && 725 pstate->multirect_index != DPU_SSPP_RECT_1) 726 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 727 &pdpu->pipe_cfg, &pstate->pixel_ext, 728 &pstate->scaler3_cfg); 729 } 730 731 return 0; 732 } 733 734 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 735 { 736 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 737 738 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 739 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 740 } 741 742 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 743 { 744 struct dpu_plane_state *pstate[R_MAX]; 745 const struct drm_plane_state *drm_state[R_MAX]; 746 struct drm_rect src[R_MAX], dst[R_MAX]; 747 struct dpu_plane *dpu_plane[R_MAX]; 748 const struct dpu_format *fmt[R_MAX]; 749 int i, buffer_lines; 750 unsigned int max_tile_height = 1; 751 bool parallel_fetch_qualified = true; 752 bool has_tiled_rect = false; 753 754 for (i = 0; i < R_MAX; i++) { 755 const struct msm_format *msm_fmt; 756 757 drm_state[i] = i ? plane->r1 : plane->r0; 758 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 759 fmt[i] = to_dpu_format(msm_fmt); 760 761 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 762 has_tiled_rect = true; 763 if (fmt[i]->tile_height > max_tile_height) 764 max_tile_height = fmt[i]->tile_height; 765 } 766 } 767 768 for (i = 0; i < R_MAX; i++) { 769 int width_threshold; 770 771 pstate[i] = to_dpu_plane_state(drm_state[i]); 772 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 773 774 if (pstate[i] == NULL) { 775 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 776 drm_state[i]->plane->base.id); 777 return -EINVAL; 778 } 779 780 src[i].x1 = drm_state[i]->src_x >> 16; 781 src[i].y1 = drm_state[i]->src_y >> 16; 782 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 783 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 784 785 dst[i] = drm_plane_state_dest(drm_state[i]); 786 787 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 788 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 789 DPU_ERROR_PLANE(dpu_plane[i], 790 "scaling is not supported in multirect mode\n"); 791 return -EINVAL; 792 } 793 794 if (DPU_FORMAT_IS_YUV(fmt[i])) { 795 DPU_ERROR_PLANE(dpu_plane[i], 796 "Unsupported format for multirect mode\n"); 797 return -EINVAL; 798 } 799 800 /** 801 * SSPP PD_MEM is split half - one for each RECT. 802 * Tiled formats need 5 lines of buffering while fetching 803 * whereas linear formats need only 2 lines. 804 * So we cannot support more than half of the supported SSPP 805 * width for tiled formats. 806 */ 807 width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; 808 if (has_tiled_rect) 809 width_threshold /= 2; 810 811 if (parallel_fetch_qualified && 812 drm_rect_width(&src[i]) > width_threshold) 813 parallel_fetch_qualified = false; 814 815 } 816 817 /* Validate RECT's and set the mode */ 818 819 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 820 if (parallel_fetch_qualified) { 821 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 822 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 823 824 goto done; 825 } 826 827 /* TIME_MX Mode */ 828 buffer_lines = 2 * max_tile_height; 829 830 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 831 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 832 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 833 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 834 } else { 835 DPU_ERROR( 836 "No multirect mode possible for the planes (%d - %d)\n", 837 drm_state[R0]->plane->base.id, 838 drm_state[R1]->plane->base.id); 839 return -EINVAL; 840 } 841 842 done: 843 if (dpu_plane[R0]->is_virtual) { 844 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 845 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 846 } else { 847 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 848 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 849 } 850 851 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 852 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 853 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 854 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 855 return 0; 856 } 857 858 /** 859 * dpu_plane_get_ctl_flush - get control flush for the given plane 860 * @plane: Pointer to drm plane structure 861 * @ctl: Pointer to hardware control driver 862 * @flush_sspp: Pointer to sspp flush control word 863 */ 864 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 865 u32 *flush_sspp) 866 { 867 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 868 } 869 870 static int dpu_plane_prepare_fb(struct drm_plane *plane, 871 struct drm_plane_state *new_state) 872 { 873 struct drm_framebuffer *fb = new_state->fb; 874 struct dpu_plane *pdpu = to_dpu_plane(plane); 875 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 876 struct dpu_hw_fmt_layout layout; 877 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 878 int ret; 879 880 if (!new_state->fb) 881 return 0; 882 883 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 884 885 /* cache aspace */ 886 pstate->aspace = kms->base.aspace; 887 888 /* 889 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 890 * we can use msm_atomic_prepare_fb() instead of doing the 891 * implicit fence and fb prepare by hand here. 892 */ 893 drm_gem_plane_helper_prepare_fb(plane, new_state); 894 895 if (pstate->aspace) { 896 ret = msm_framebuffer_prepare(new_state->fb, 897 pstate->aspace); 898 if (ret) { 899 DPU_ERROR("failed to prepare framebuffer\n"); 900 return ret; 901 } 902 } 903 904 /* validate framebuffer layout before commit */ 905 ret = dpu_format_populate_layout(pstate->aspace, 906 new_state->fb, &layout); 907 if (ret) { 908 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 909 return ret; 910 } 911 912 return 0; 913 } 914 915 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 916 struct drm_plane_state *old_state) 917 { 918 struct dpu_plane *pdpu = to_dpu_plane(plane); 919 struct dpu_plane_state *old_pstate; 920 921 if (!old_state || !old_state->fb) 922 return; 923 924 old_pstate = to_dpu_plane_state(old_state); 925 926 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 927 928 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace); 929 } 930 931 static bool dpu_plane_validate_src(struct drm_rect *src, 932 struct drm_rect *fb_rect, 933 uint32_t min_src_size) 934 { 935 /* Ensure fb size is supported */ 936 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 937 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 938 return false; 939 940 /* Ensure src rect is above the minimum size */ 941 if (drm_rect_width(src) < min_src_size || 942 drm_rect_height(src) < min_src_size) 943 return false; 944 945 /* Ensure src is fully encapsulated in fb */ 946 return drm_rect_intersect(fb_rect, src) && 947 drm_rect_equals(fb_rect, src); 948 } 949 950 static int dpu_plane_atomic_check(struct drm_plane *plane, 951 struct drm_atomic_state *state) 952 { 953 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 954 plane); 955 int ret = 0, min_scale; 956 struct dpu_plane *pdpu = to_dpu_plane(plane); 957 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 958 const struct drm_crtc_state *crtc_state = NULL; 959 const struct dpu_format *fmt; 960 struct drm_rect src, dst, fb_rect = { 0 }; 961 uint32_t min_src_size, max_linewidth; 962 963 if (new_plane_state->crtc) 964 crtc_state = drm_atomic_get_new_crtc_state(state, 965 new_plane_state->crtc); 966 967 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale); 968 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 969 min_scale, 970 pdpu->pipe_sblk->maxdwnscale << 16, 971 true, true); 972 if (ret) { 973 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 974 return ret; 975 } 976 if (!new_plane_state->visible) 977 return 0; 978 979 src.x1 = new_plane_state->src_x >> 16; 980 src.y1 = new_plane_state->src_y >> 16; 981 src.x2 = src.x1 + (new_plane_state->src_w >> 16); 982 src.y2 = src.y1 + (new_plane_state->src_h >> 16); 983 984 dst = drm_plane_state_dest(new_plane_state); 985 986 fb_rect.x2 = new_plane_state->fb->width; 987 fb_rect.y2 = new_plane_state->fb->height; 988 989 max_linewidth = pdpu->catalog->caps->max_linewidth; 990 991 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 992 993 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 994 995 if (DPU_FORMAT_IS_YUV(fmt) && 996 (!(pdpu->features & DPU_SSPP_SCALER) || 997 !(pdpu->features & (BIT(DPU_SSPP_CSC) 998 | BIT(DPU_SSPP_CSC_10BIT))))) { 999 DPU_DEBUG_PLANE(pdpu, 1000 "plane doesn't have scaler/csc for yuv\n"); 1001 return -EINVAL; 1002 1003 /* check src bounds */ 1004 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 1005 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 1006 DRM_RECT_ARG(&src)); 1007 return -E2BIG; 1008 1009 /* valid yuv image */ 1010 } else if (DPU_FORMAT_IS_YUV(fmt) && 1011 (src.x1 & 0x1 || src.y1 & 0x1 || 1012 drm_rect_width(&src) & 0x1 || 1013 drm_rect_height(&src) & 0x1)) { 1014 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 1015 DRM_RECT_ARG(&src)); 1016 return -EINVAL; 1017 1018 /* min dst support */ 1019 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 1020 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 1021 DRM_RECT_ARG(&dst)); 1022 return -EINVAL; 1023 1024 /* check decimated source width */ 1025 } else if (drm_rect_width(&src) > max_linewidth) { 1026 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 1027 DRM_RECT_ARG(&src), max_linewidth); 1028 return -E2BIG; 1029 } 1030 1031 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 1032 1033 return 0; 1034 } 1035 1036 void dpu_plane_flush(struct drm_plane *plane) 1037 { 1038 struct dpu_plane *pdpu; 1039 struct dpu_plane_state *pstate; 1040 1041 if (!plane || !plane->state) { 1042 DPU_ERROR("invalid plane\n"); 1043 return; 1044 } 1045 1046 pdpu = to_dpu_plane(plane); 1047 pstate = to_dpu_plane_state(plane->state); 1048 1049 /* 1050 * These updates have to be done immediately before the plane flush 1051 * timing, and may not be moved to the atomic_update/mode_set functions. 1052 */ 1053 if (pdpu->is_error) 1054 /* force white frame with 100% alpha pipe output on error */ 1055 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1056 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1057 /* force 100% alpha */ 1058 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1059 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) 1060 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); 1061 1062 /* flag h/w flush complete */ 1063 if (plane->state) 1064 pstate->pending = false; 1065 } 1066 1067 /** 1068 * dpu_plane_set_error: enable/disable error condition 1069 * @plane: pointer to drm_plane structure 1070 * @error: error value to set 1071 */ 1072 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1073 { 1074 struct dpu_plane *pdpu; 1075 1076 if (!plane) 1077 return; 1078 1079 pdpu = to_dpu_plane(plane); 1080 pdpu->is_error = error; 1081 } 1082 1083 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1084 { 1085 uint32_t src_flags; 1086 struct dpu_plane *pdpu = to_dpu_plane(plane); 1087 struct drm_plane_state *state = plane->state; 1088 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1089 struct drm_crtc *crtc = state->crtc; 1090 struct drm_framebuffer *fb = state->fb; 1091 bool is_rt_pipe, update_qos_remap; 1092 const struct dpu_format *fmt = 1093 to_dpu_format(msm_framebuffer_format(fb)); 1094 1095 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); 1096 1097 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); 1098 1099 pstate->pending = true; 1100 1101 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1102 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1103 1104 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1105 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1106 crtc->base.id, DRM_RECT_ARG(&state->dst), 1107 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1108 1109 pdpu->pipe_cfg.src_rect = state->src; 1110 1111 /* state->src is 16.16, src_rect is not */ 1112 pdpu->pipe_cfg.src_rect.x1 >>= 16; 1113 pdpu->pipe_cfg.src_rect.x2 >>= 16; 1114 pdpu->pipe_cfg.src_rect.y1 >>= 16; 1115 pdpu->pipe_cfg.src_rect.y2 >>= 16; 1116 1117 pdpu->pipe_cfg.dst_rect = state->dst; 1118 1119 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); 1120 1121 /* override for color fill */ 1122 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1123 /* skip remaining processing on color fill */ 1124 return; 1125 } 1126 1127 if (pdpu->pipe_hw->ops.setup_rects) { 1128 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1129 &pdpu->pipe_cfg, 1130 pstate->multirect_index); 1131 } 1132 1133 if (pdpu->pipe_hw->ops.setup_pe && 1134 (pstate->multirect_index != DPU_SSPP_RECT_1)) 1135 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 1136 &pstate->pixel_ext); 1137 1138 /** 1139 * when programmed in multirect mode, scalar block will be 1140 * bypassed. Still we need to update alpha and bitwidth 1141 * ONLY for RECT0 1142 */ 1143 if (pdpu->pipe_hw->ops.setup_scaler && 1144 pstate->multirect_index != DPU_SSPP_RECT_1) 1145 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 1146 &pdpu->pipe_cfg, &pstate->pixel_ext, 1147 &pstate->scaler3_cfg); 1148 1149 if (pdpu->pipe_hw->ops.setup_multirect) 1150 pdpu->pipe_hw->ops.setup_multirect( 1151 pdpu->pipe_hw, 1152 pstate->multirect_index, 1153 pstate->multirect_mode); 1154 1155 if (pdpu->pipe_hw->ops.setup_format) { 1156 unsigned int rotation; 1157 1158 src_flags = 0x0; 1159 1160 rotation = drm_rotation_simplify(state->rotation, 1161 DRM_MODE_ROTATE_0 | 1162 DRM_MODE_REFLECT_X | 1163 DRM_MODE_REFLECT_Y); 1164 1165 if (rotation & DRM_MODE_REFLECT_X) 1166 src_flags |= DPU_SSPP_FLIP_LR; 1167 1168 if (rotation & DRM_MODE_REFLECT_Y) 1169 src_flags |= DPU_SSPP_FLIP_UD; 1170 1171 /* update format */ 1172 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1173 pstate->multirect_index); 1174 1175 if (pdpu->pipe_hw->ops.setup_cdp) { 1176 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; 1177 1178 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); 1179 1180 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg 1181 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1182 cdp_cfg->ubwc_meta_enable = 1183 DPU_FORMAT_IS_UBWC(fmt); 1184 cdp_cfg->tile_amortize_enable = 1185 DPU_FORMAT_IS_UBWC(fmt) || 1186 DPU_FORMAT_IS_TILE(fmt); 1187 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1188 1189 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); 1190 } 1191 1192 /* update csc */ 1193 if (DPU_FORMAT_IS_YUV(fmt)) 1194 _dpu_plane_setup_csc(pdpu); 1195 else 1196 pdpu->csc_ptr = 0; 1197 } 1198 1199 _dpu_plane_set_qos_lut(plane, fb); 1200 _dpu_plane_set_danger_lut(plane, fb); 1201 1202 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1203 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1204 _dpu_plane_set_ot_limit(plane, crtc); 1205 } 1206 1207 update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) || 1208 pstate->needs_qos_remap; 1209 1210 if (update_qos_remap) { 1211 if (is_rt_pipe != pdpu->is_rt_pipe) 1212 pdpu->is_rt_pipe = is_rt_pipe; 1213 else if (pstate->needs_qos_remap) 1214 pstate->needs_qos_remap = false; 1215 _dpu_plane_set_qos_remap(plane); 1216 } 1217 1218 _dpu_plane_calc_bw(plane, fb); 1219 1220 _dpu_plane_calc_clk(plane); 1221 } 1222 1223 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1224 { 1225 struct dpu_plane *pdpu = to_dpu_plane(plane); 1226 struct drm_plane_state *state = plane->state; 1227 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1228 1229 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1230 pstate->multirect_mode); 1231 1232 pstate->pending = true; 1233 1234 if (is_dpu_plane_virtual(plane) && 1235 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1236 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1237 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1238 } 1239 1240 static void dpu_plane_atomic_update(struct drm_plane *plane, 1241 struct drm_atomic_state *state) 1242 { 1243 struct dpu_plane *pdpu = to_dpu_plane(plane); 1244 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1245 plane); 1246 1247 pdpu->is_error = false; 1248 1249 DPU_DEBUG_PLANE(pdpu, "\n"); 1250 1251 if (!new_state->visible) { 1252 _dpu_plane_atomic_disable(plane); 1253 } else { 1254 dpu_plane_sspp_atomic_update(plane); 1255 } 1256 } 1257 1258 static void dpu_plane_destroy(struct drm_plane *plane) 1259 { 1260 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1261 1262 DPU_DEBUG_PLANE(pdpu, "\n"); 1263 1264 if (pdpu) { 1265 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1266 1267 mutex_destroy(&pdpu->lock); 1268 1269 /* this will destroy the states as well */ 1270 drm_plane_cleanup(plane); 1271 1272 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1273 1274 kfree(pdpu); 1275 } 1276 } 1277 1278 static void dpu_plane_destroy_state(struct drm_plane *plane, 1279 struct drm_plane_state *state) 1280 { 1281 __drm_atomic_helper_plane_destroy_state(state); 1282 kfree(to_dpu_plane_state(state)); 1283 } 1284 1285 static struct drm_plane_state * 1286 dpu_plane_duplicate_state(struct drm_plane *plane) 1287 { 1288 struct dpu_plane *pdpu; 1289 struct dpu_plane_state *pstate; 1290 struct dpu_plane_state *old_state; 1291 1292 if (!plane) { 1293 DPU_ERROR("invalid plane\n"); 1294 return NULL; 1295 } else if (!plane->state) { 1296 DPU_ERROR("invalid plane state\n"); 1297 return NULL; 1298 } 1299 1300 old_state = to_dpu_plane_state(plane->state); 1301 pdpu = to_dpu_plane(plane); 1302 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1303 if (!pstate) { 1304 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1305 return NULL; 1306 } 1307 1308 DPU_DEBUG_PLANE(pdpu, "\n"); 1309 1310 pstate->pending = false; 1311 1312 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1313 1314 return &pstate->base; 1315 } 1316 1317 static void dpu_plane_reset(struct drm_plane *plane) 1318 { 1319 struct dpu_plane *pdpu; 1320 struct dpu_plane_state *pstate; 1321 1322 if (!plane) { 1323 DPU_ERROR("invalid plane\n"); 1324 return; 1325 } 1326 1327 pdpu = to_dpu_plane(plane); 1328 DPU_DEBUG_PLANE(pdpu, "\n"); 1329 1330 /* remove previous state, if present */ 1331 if (plane->state) { 1332 dpu_plane_destroy_state(plane, plane->state); 1333 plane->state = 0; 1334 } 1335 1336 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1337 if (!pstate) { 1338 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1339 return; 1340 } 1341 1342 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1343 } 1344 1345 #ifdef CONFIG_DEBUG_FS 1346 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1347 { 1348 struct dpu_plane *pdpu = to_dpu_plane(plane); 1349 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1350 1351 if (!pdpu->is_rt_pipe) 1352 return; 1353 1354 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1355 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1356 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1357 } 1358 1359 static ssize_t _dpu_plane_danger_read(struct file *file, 1360 char __user *buff, size_t count, loff_t *ppos) 1361 { 1362 struct dpu_kms *kms = file->private_data; 1363 int len; 1364 char buf[40]; 1365 1366 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 1367 1368 return simple_read_from_buffer(buff, count, ppos, buf, len); 1369 } 1370 1371 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 1372 { 1373 struct drm_plane *plane; 1374 1375 drm_for_each_plane(plane, kms->dev) { 1376 if (plane->fb && plane->state) { 1377 dpu_plane_danger_signal_ctrl(plane, enable); 1378 DPU_DEBUG("plane:%d img:%dx%d ", 1379 plane->base.id, plane->fb->width, 1380 plane->fb->height); 1381 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 1382 plane->state->src_x >> 16, 1383 plane->state->src_y >> 16, 1384 plane->state->src_w >> 16, 1385 plane->state->src_h >> 16, 1386 plane->state->crtc_x, plane->state->crtc_y, 1387 plane->state->crtc_w, plane->state->crtc_h); 1388 } else { 1389 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 1390 } 1391 } 1392 } 1393 1394 static ssize_t _dpu_plane_danger_write(struct file *file, 1395 const char __user *user_buf, size_t count, loff_t *ppos) 1396 { 1397 struct dpu_kms *kms = file->private_data; 1398 int disable_panic; 1399 int ret; 1400 1401 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 1402 if (ret) 1403 return ret; 1404 1405 if (disable_panic) { 1406 /* Disable panic signal for all active pipes */ 1407 DPU_DEBUG("Disabling danger:\n"); 1408 _dpu_plane_set_danger_state(kms, false); 1409 kms->has_danger_ctrl = false; 1410 } else { 1411 /* Enable panic signal for all active pipes */ 1412 DPU_DEBUG("Enabling danger:\n"); 1413 kms->has_danger_ctrl = true; 1414 _dpu_plane_set_danger_state(kms, true); 1415 } 1416 1417 return count; 1418 } 1419 1420 static const struct file_operations dpu_plane_danger_enable = { 1421 .open = simple_open, 1422 .read = _dpu_plane_danger_read, 1423 .write = _dpu_plane_danger_write, 1424 }; 1425 1426 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1427 { 1428 struct dpu_plane *pdpu = to_dpu_plane(plane); 1429 struct dpu_kms *kms = _dpu_plane_get_kms(plane); 1430 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; 1431 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 1432 1433 /* create overall sub-directory for the pipe */ 1434 pdpu->debugfs_root = 1435 debugfs_create_dir(pdpu->pipe_name, 1436 plane->dev->primary->debugfs_root); 1437 1438 /* don't error check these */ 1439 debugfs_create_x32("features", 0600, 1440 pdpu->debugfs_root, &pdpu->features); 1441 1442 /* add register dump support */ 1443 dpu_debugfs_setup_regset32(&pdpu->debugfs_src, 1444 sblk->src_blk.base + cfg->base, 1445 sblk->src_blk.len, 1446 kms); 1447 dpu_debugfs_create_regset32("src_blk", 0400, 1448 pdpu->debugfs_root, &pdpu->debugfs_src); 1449 1450 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 1451 cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || 1452 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || 1453 cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) { 1454 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, 1455 sblk->scaler_blk.base + cfg->base, 1456 sblk->scaler_blk.len, 1457 kms); 1458 dpu_debugfs_create_regset32("scaler_blk", 0400, 1459 pdpu->debugfs_root, 1460 &pdpu->debugfs_scaler); 1461 debugfs_create_bool("default_scaling", 1462 0600, 1463 pdpu->debugfs_root, 1464 &pdpu->debugfs_default_scale); 1465 } 1466 1467 if (cfg->features & BIT(DPU_SSPP_CSC) || 1468 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { 1469 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, 1470 sblk->csc_blk.base + cfg->base, 1471 sblk->csc_blk.len, 1472 kms); 1473 dpu_debugfs_create_regset32("csc_blk", 0400, 1474 pdpu->debugfs_root, &pdpu->debugfs_csc); 1475 } 1476 1477 debugfs_create_u32("xin_id", 1478 0400, 1479 pdpu->debugfs_root, 1480 (u32 *) &cfg->xin_id); 1481 debugfs_create_u32("clk_ctrl", 1482 0400, 1483 pdpu->debugfs_root, 1484 (u32 *) &cfg->clk_ctrl); 1485 debugfs_create_x32("creq_vblank", 1486 0600, 1487 pdpu->debugfs_root, 1488 (u32 *) &sblk->creq_vblank); 1489 debugfs_create_x32("danger_vblank", 1490 0600, 1491 pdpu->debugfs_root, 1492 (u32 *) &sblk->danger_vblank); 1493 1494 debugfs_create_file("disable_danger", 1495 0600, 1496 pdpu->debugfs_root, 1497 kms, &dpu_plane_danger_enable); 1498 1499 return 0; 1500 } 1501 #else 1502 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1503 { 1504 return 0; 1505 } 1506 #endif 1507 1508 static int dpu_plane_late_register(struct drm_plane *plane) 1509 { 1510 return _dpu_plane_init_debugfs(plane); 1511 } 1512 1513 static void dpu_plane_early_unregister(struct drm_plane *plane) 1514 { 1515 struct dpu_plane *pdpu = to_dpu_plane(plane); 1516 1517 debugfs_remove_recursive(pdpu->debugfs_root); 1518 } 1519 1520 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1521 uint32_t format, uint64_t modifier) 1522 { 1523 if (modifier == DRM_FORMAT_MOD_LINEAR) 1524 return true; 1525 1526 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) { 1527 int i; 1528 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) { 1529 if (format == qcom_compressed_supported_formats[i]) 1530 return true; 1531 } 1532 } 1533 1534 return false; 1535 } 1536 1537 static const struct drm_plane_funcs dpu_plane_funcs = { 1538 .update_plane = drm_atomic_helper_update_plane, 1539 .disable_plane = drm_atomic_helper_disable_plane, 1540 .destroy = dpu_plane_destroy, 1541 .reset = dpu_plane_reset, 1542 .atomic_duplicate_state = dpu_plane_duplicate_state, 1543 .atomic_destroy_state = dpu_plane_destroy_state, 1544 .late_register = dpu_plane_late_register, 1545 .early_unregister = dpu_plane_early_unregister, 1546 .format_mod_supported = dpu_plane_format_mod_supported, 1547 }; 1548 1549 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1550 .prepare_fb = dpu_plane_prepare_fb, 1551 .cleanup_fb = dpu_plane_cleanup_fb, 1552 .atomic_check = dpu_plane_atomic_check, 1553 .atomic_update = dpu_plane_atomic_update, 1554 }; 1555 1556 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1557 { 1558 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1559 } 1560 1561 bool is_dpu_plane_virtual(struct drm_plane *plane) 1562 { 1563 return plane ? to_dpu_plane(plane)->is_virtual : false; 1564 } 1565 1566 /* initialize plane */ 1567 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1568 uint32_t pipe, enum drm_plane_type type, 1569 unsigned long possible_crtcs, u32 master_plane_id) 1570 { 1571 struct drm_plane *plane = NULL, *master_plane = NULL; 1572 const uint32_t *format_list; 1573 struct dpu_plane *pdpu; 1574 struct msm_drm_private *priv = dev->dev_private; 1575 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1576 int zpos_max = DPU_ZPOS_MAX; 1577 uint32_t num_formats; 1578 int ret = -EINVAL; 1579 1580 /* create and zero local structure */ 1581 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1582 if (!pdpu) { 1583 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1584 ret = -ENOMEM; 1585 return ERR_PTR(ret); 1586 } 1587 1588 /* cache local stuff for later */ 1589 plane = &pdpu->base; 1590 pdpu->pipe = pipe; 1591 pdpu->is_virtual = (master_plane_id != 0); 1592 INIT_LIST_HEAD(&pdpu->mplane_list); 1593 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1594 if (master_plane) { 1595 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1596 1597 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1598 } 1599 1600 /* initialize underlying h/w driver */ 1601 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1602 master_plane_id != 0); 1603 if (IS_ERR(pdpu->pipe_hw)) { 1604 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1605 ret = PTR_ERR(pdpu->pipe_hw); 1606 goto clean_plane; 1607 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1608 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1609 goto clean_sspp; 1610 } 1611 1612 /* cache features mask for later */ 1613 pdpu->features = pdpu->pipe_hw->cap->features; 1614 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; 1615 if (!pdpu->pipe_sblk) { 1616 DPU_ERROR("[%u]invalid sblk\n", pipe); 1617 goto clean_sspp; 1618 } 1619 1620 if (pdpu->is_virtual) { 1621 format_list = pdpu->pipe_sblk->virt_format_list; 1622 num_formats = pdpu->pipe_sblk->virt_num_formats; 1623 } 1624 else { 1625 format_list = pdpu->pipe_sblk->format_list; 1626 num_formats = pdpu->pipe_sblk->num_formats; 1627 } 1628 1629 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1630 format_list, num_formats, 1631 supported_format_modifiers, type, NULL); 1632 if (ret) 1633 goto clean_sspp; 1634 1635 pdpu->catalog = kms->catalog; 1636 1637 if (kms->catalog->mixer_count && 1638 kms->catalog->mixer[0].sblk->maxblendstages) { 1639 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1640 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1641 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1642 } 1643 1644 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1645 if (ret) 1646 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1647 1648 drm_plane_create_alpha_property(plane); 1649 drm_plane_create_blend_mode_property(plane, 1650 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1651 BIT(DRM_MODE_BLEND_PREMULTI) | 1652 BIT(DRM_MODE_BLEND_COVERAGE)); 1653 1654 drm_plane_create_rotation_property(plane, 1655 DRM_MODE_ROTATE_0, 1656 DRM_MODE_ROTATE_0 | 1657 DRM_MODE_ROTATE_180 | 1658 DRM_MODE_REFLECT_X | 1659 DRM_MODE_REFLECT_Y); 1660 1661 drm_plane_enable_fb_damage_clips(plane); 1662 1663 /* success! finalize initialization */ 1664 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1665 1666 /* save user friendly pipe name for later */ 1667 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); 1668 1669 mutex_init(&pdpu->lock); 1670 1671 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, 1672 pipe, plane->base.id, master_plane_id); 1673 return plane; 1674 1675 clean_sspp: 1676 if (pdpu && pdpu->pipe_hw) 1677 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1678 clean_plane: 1679 kfree(pdpu); 1680 return ERR_PTR(ret); 1681 } 1682