1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "msm_mdss.h" 22 #include "dpu_kms.h" 23 #include "dpu_formats.h" 24 #include "dpu_hw_sspp.h" 25 #include "dpu_hw_util.h" 26 #include "dpu_trace.h" 27 #include "dpu_crtc.h" 28 #include "dpu_vbif.h" 29 #include "dpu_plane.h" 30 31 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 33 34 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 35 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 36 37 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 38 #define PHASE_STEP_SHIFT 21 39 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 40 #define PHASE_RESIDUAL 15 41 42 #define SHARP_STRENGTH_DEFAULT 32 43 #define SHARP_EDGE_THR_DEFAULT 112 44 #define SHARP_SMOOTH_THR_DEFAULT 8 45 #define SHARP_NOISE_THR_DEFAULT 2 46 47 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 48 #define DPU_ZPOS_MAX 255 49 50 /* 51 * Default Preload Values 52 */ 53 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 54 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 55 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 56 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 57 58 #define DEFAULT_REFRESH_RATE 60 59 60 static const uint32_t qcom_compressed_supported_formats[] = { 61 DRM_FORMAT_ABGR8888, 62 DRM_FORMAT_ARGB8888, 63 DRM_FORMAT_XBGR8888, 64 DRM_FORMAT_XRGB8888, 65 DRM_FORMAT_ARGB2101010, 66 DRM_FORMAT_XRGB2101010, 67 DRM_FORMAT_BGR565, 68 69 DRM_FORMAT_NV12, 70 DRM_FORMAT_P010, 71 }; 72 73 /* 74 * struct dpu_plane - local dpu plane structure 75 * @aspace: address space pointer 76 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 77 * @catalog: Points to dpu catalog structure 78 * @revalidate: force revalidation of all the plane properties 79 */ 80 struct dpu_plane { 81 struct drm_plane base; 82 83 enum dpu_sspp pipe; 84 85 uint32_t color_fill; 86 bool is_error; 87 bool is_rt_pipe; 88 const struct dpu_mdss_cfg *catalog; 89 }; 90 91 static const uint64_t supported_format_modifiers[] = { 92 DRM_FORMAT_MOD_QCOM_COMPRESSED, 93 DRM_FORMAT_MOD_LINEAR, 94 DRM_FORMAT_MOD_INVALID 95 }; 96 97 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 98 99 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 100 { 101 struct msm_drm_private *priv = plane->dev->dev_private; 102 103 return to_dpu_kms(priv->kms); 104 } 105 106 /** 107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 108 * @catalog: Points to dpu catalog structure 109 * @fmt: Pointer to source buffer format 110 * @mode: Pointer to drm display mode 111 * @pipe_cfg: Pointer to pipe configuration 112 * Result: Updates calculated bandwidth in the plane state. 113 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 114 * Prefill BW Equation: line src bytes * line_time 115 */ 116 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 117 const struct msm_format *fmt, 118 const struct drm_display_mode *mode, 119 struct dpu_sw_pipe_cfg *pipe_cfg) 120 { 121 int src_width, src_height, dst_height, fps; 122 u64 plane_pixel_rate, plane_bit_rate; 123 u64 plane_prefill_bw; 124 u64 plane_bw; 125 u32 hw_latency_lines; 126 u64 scale_factor; 127 int vbp, vpw, vfp; 128 129 src_width = drm_rect_width(&pipe_cfg->src_rect); 130 src_height = drm_rect_height(&pipe_cfg->src_rect); 131 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 132 fps = drm_mode_vrefresh(mode); 133 vbp = mode->vtotal - mode->vsync_end; 134 vpw = mode->vsync_end - mode->vsync_start; 135 vfp = mode->vsync_start - mode->vdisplay; 136 hw_latency_lines = catalog->perf->min_prefill_lines; 137 scale_factor = src_height > dst_height ? 138 mult_frac(src_height, 1, dst_height) : 1; 139 140 plane_pixel_rate = src_width * mode->vtotal * fps; 141 plane_bit_rate = plane_pixel_rate * fmt->bpp; 142 143 plane_bw = plane_bit_rate * scale_factor; 144 145 plane_prefill_bw = plane_bw * hw_latency_lines; 146 147 if ((vbp+vpw) > hw_latency_lines) 148 do_div(plane_prefill_bw, (vbp+vpw)); 149 else if ((vbp+vpw+vfp) < hw_latency_lines) 150 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 151 else 152 do_div(plane_prefill_bw, hw_latency_lines); 153 154 155 return max(plane_bw, plane_prefill_bw); 156 } 157 158 /** 159 * _dpu_plane_calc_clk - calculate clock required for a plane 160 * @mode: Pointer to drm display mode 161 * @pipe_cfg: Pointer to pipe configuration 162 * Result: Updates calculated clock in the plane state. 163 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 164 */ 165 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 166 struct dpu_sw_pipe_cfg *pipe_cfg) 167 { 168 int dst_width, src_height, dst_height, fps; 169 u64 plane_clk; 170 171 src_height = drm_rect_height(&pipe_cfg->src_rect); 172 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 173 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 174 fps = drm_mode_vrefresh(mode); 175 176 plane_clk = 177 dst_width * mode->vtotal * fps; 178 179 if (src_height > dst_height) { 180 plane_clk *= src_height; 181 do_div(plane_clk, dst_height); 182 } 183 184 return plane_clk; 185 } 186 187 /** 188 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 189 * @plane: Pointer to drm plane 190 * @pipe: Pointer to software pipe 191 * @lut_usage: LUT usecase 192 * @fmt: Pointer to source buffer format 193 * @src_width: width of source buffer 194 * Return: fill level corresponding to the source buffer/format or 0 if error 195 */ 196 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 197 struct dpu_sw_pipe *pipe, 198 enum dpu_qos_lut_usage lut_usage, 199 const struct msm_format *fmt, u32 src_width) 200 { 201 struct dpu_plane *pdpu; 202 u32 fixed_buff_size; 203 u32 total_fl; 204 205 if (!fmt || !pipe || !src_width || !fmt->bpp) { 206 DPU_ERROR("invalid arguments\n"); 207 return 0; 208 } 209 210 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 211 return 0; 212 213 pdpu = to_dpu_plane(plane); 214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 215 216 /* FIXME: in multirect case account for the src_width of all the planes */ 217 218 if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { 219 if (fmt->chroma_sample == CHROMA_420) { 220 /* NV12 */ 221 total_fl = (fixed_buff_size / 2) / 222 ((src_width + 32) * fmt->bpp); 223 } else { 224 /* non NV12 */ 225 total_fl = (fixed_buff_size / 2) * 2 / 226 ((src_width + 32) * fmt->bpp); 227 } 228 } else { 229 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 230 total_fl = (fixed_buff_size / 2) * 2 / 231 ((src_width + 32) * fmt->bpp); 232 } else { 233 total_fl = (fixed_buff_size) * 2 / 234 ((src_width + 32) * fmt->bpp); 235 } 236 } 237 238 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n", 239 pipe->sspp->idx - SSPP_VIG0, 240 &fmt->pixel_format, 241 src_width, total_fl); 242 243 return total_fl; 244 } 245 246 /** 247 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 248 * @plane: Pointer to drm plane 249 * @pipe: Pointer to software pipe 250 * @fmt: Pointer to source buffer format 251 * @pipe_cfg: Pointer to pipe configuration 252 */ 253 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 254 struct dpu_sw_pipe *pipe, 255 const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 256 { 257 struct dpu_plane *pdpu = to_dpu_plane(plane); 258 struct dpu_hw_qos_cfg cfg; 259 u32 total_fl, lut_usage; 260 261 if (!pdpu->is_rt_pipe) { 262 lut_usage = DPU_QOS_LUT_USAGE_NRT; 263 } else { 264 if (fmt && MSM_FORMAT_IS_LINEAR(fmt)) 265 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 266 else 267 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 268 } 269 270 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 271 drm_rect_width(&pipe_cfg->src_rect)); 272 273 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 274 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 276 277 if (pipe->sspp->idx != SSPP_CURSOR0 && 278 pipe->sspp->idx != SSPP_CURSOR1 && 279 pdpu->is_rt_pipe) 280 cfg.danger_safe_en = true; 281 282 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 283 pdpu->pipe - SSPP_VIG0, 284 cfg.danger_safe_en, 285 pdpu->is_rt_pipe); 286 287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 288 (fmt) ? fmt->pixel_format : 0, 289 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 290 291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n", 292 pdpu->pipe - SSPP_VIG0, 293 fmt ? &fmt->pixel_format : NULL, 294 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 295 296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 297 (fmt) ? fmt->pixel_format : 0, 298 (fmt) ? fmt->fetch_mode : 0, 299 cfg.danger_lut, 300 cfg.safe_lut); 301 302 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", 303 pdpu->pipe - SSPP_VIG0, 304 fmt ? &fmt->pixel_format : NULL, 305 fmt ? fmt->fetch_mode : -1, 306 cfg.danger_lut, 307 cfg.safe_lut); 308 309 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 310 } 311 312 /** 313 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 314 * @plane: Pointer to drm plane 315 * @pipe: Pointer to software pipe 316 * @enable: true to enable QoS control 317 */ 318 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 319 struct dpu_sw_pipe *pipe, 320 bool enable) 321 { 322 struct dpu_plane *pdpu = to_dpu_plane(plane); 323 324 if (!pdpu->is_rt_pipe) 325 enable = false; 326 327 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 328 pdpu->pipe - SSPP_VIG0, 329 enable, 330 pdpu->is_rt_pipe); 331 332 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 333 enable); 334 } 335 336 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp, 337 struct dpu_hw_mdp *mdp, 338 bool enable, bool *forced_on) 339 { 340 if (sspp->ops.setup_clk_force_ctrl) { 341 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable); 342 return true; 343 } 344 345 if (mdp->ops.setup_clk_force_ctrl) { 346 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); 347 return true; 348 } 349 350 return false; 351 } 352 353 /** 354 * _dpu_plane_set_ot_limit - set OT limit for the given plane 355 * @plane: Pointer to drm plane 356 * @pipe: Pointer to software pipe 357 * @pipe_cfg: Pointer to pipe configuration 358 * @frame_rate: CRTC's frame rate 359 */ 360 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 361 struct dpu_sw_pipe *pipe, 362 struct dpu_sw_pipe_cfg *pipe_cfg, 363 int frame_rate) 364 { 365 struct dpu_plane *pdpu = to_dpu_plane(plane); 366 struct dpu_vbif_set_ot_params ot_params; 367 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 368 bool forced_on = false; 369 370 memset(&ot_params, 0, sizeof(ot_params)); 371 ot_params.xin_id = pipe->sspp->cap->xin_id; 372 ot_params.num = pipe->sspp->idx - SSPP_NONE; 373 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 374 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 375 ot_params.is_wfd = !pdpu->is_rt_pipe; 376 ot_params.frame_rate = frame_rate; 377 ot_params.vbif_idx = VBIF_RT; 378 ot_params.rd = true; 379 380 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 381 true, &forced_on)) 382 return; 383 384 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 385 386 if (forced_on) 387 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 388 false, &forced_on); 389 } 390 391 /** 392 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 393 * @plane: Pointer to drm plane 394 * @pipe: Pointer to software pipe 395 */ 396 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 397 struct dpu_sw_pipe *pipe) 398 { 399 struct dpu_plane *pdpu = to_dpu_plane(plane); 400 struct dpu_vbif_set_qos_params qos_params; 401 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 402 bool forced_on = false; 403 404 memset(&qos_params, 0, sizeof(qos_params)); 405 qos_params.vbif_idx = VBIF_RT; 406 qos_params.xin_id = pipe->sspp->cap->xin_id; 407 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 408 qos_params.is_rt = pdpu->is_rt_pipe; 409 410 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n", 411 qos_params.num, 412 qos_params.vbif_idx, 413 qos_params.xin_id, qos_params.is_rt); 414 415 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 416 true, &forced_on)) 417 return; 418 419 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 420 421 if (forced_on) 422 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 423 false, &forced_on); 424 } 425 426 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 427 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 428 struct dpu_hw_scaler3_cfg *scale_cfg, 429 const struct msm_format *fmt, 430 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 431 unsigned int rotation) 432 { 433 uint32_t i; 434 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 435 436 /* 437 * For inline rotation cases, scaler config is post-rotation, 438 * so swap the dimensions here. However, pixel extension will 439 * need pre-rotation settings. 440 */ 441 if (inline_rotation) 442 swap(src_w, src_h); 443 444 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 445 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 446 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 447 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 448 449 450 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 451 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 452 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 453 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 454 455 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 456 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 458 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 459 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 461 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 462 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 463 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 464 465 for (i = 0; i < DPU_MAX_PLANES; i++) { 466 scale_cfg->src_width[i] = src_w; 467 scale_cfg->src_height[i] = src_h; 468 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 469 scale_cfg->src_width[i] /= chroma_subsmpl_h; 470 scale_cfg->src_height[i] /= chroma_subsmpl_v; 471 } 472 473 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) { 474 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 475 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 476 } else { 477 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 478 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 479 } 480 } 481 if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 482 && (src_w == dst_w)) 483 return; 484 485 scale_cfg->dst_width = dst_w; 486 scale_cfg->dst_height = dst_h; 487 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 488 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 489 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 490 scale_cfg->lut_flag = 0; 491 scale_cfg->blend_cfg = 1; 492 scale_cfg->enable = 1; 493 } 494 495 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 496 struct dpu_hw_pixel_ext *pixel_ext, 497 uint32_t src_w, uint32_t src_h, 498 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 499 { 500 int i; 501 502 for (i = 0; i < DPU_MAX_PLANES; i++) { 503 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 504 src_w /= chroma_subsmpl_h; 505 src_h /= chroma_subsmpl_v; 506 } 507 508 pixel_ext->num_ext_pxls_top[i] = src_h; 509 pixel_ext->num_ext_pxls_left[i] = src_w; 510 } 511 } 512 513 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 514 const struct msm_format *fmt) 515 { 516 const struct dpu_csc_cfg *csc_ptr; 517 518 if (!MSM_FORMAT_IS_YUV(fmt)) 519 return NULL; 520 521 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 522 csc_ptr = &dpu_csc10_YUV2RGB_601L; 523 else 524 csc_ptr = &dpu_csc_YUV2RGB_601L; 525 526 return csc_ptr; 527 } 528 529 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 530 const struct msm_format *fmt, bool color_fill, 531 struct dpu_sw_pipe_cfg *pipe_cfg, 532 unsigned int rotation) 533 { 534 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 535 const struct drm_format_info *info = drm_format_info(fmt->pixel_format); 536 struct dpu_hw_scaler3_cfg scaler3_cfg; 537 struct dpu_hw_pixel_ext pixel_ext; 538 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 539 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 540 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 541 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 542 543 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 544 memset(&pixel_ext, 0, sizeof(pixel_ext)); 545 546 /* don't chroma subsample if decimating */ 547 /* update scaler. calculate default config for QSEED3 */ 548 _dpu_plane_setup_scaler3(pipe_hw, 549 src_width, 550 src_height, 551 dst_width, 552 dst_height, 553 &scaler3_cfg, fmt, 554 info->hsub, info->vsub, 555 rotation); 556 557 /* configure pixel extension based on scalar config */ 558 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 559 src_width, src_height, info->hsub, info->vsub); 560 561 if (pipe_hw->ops.setup_pe) 562 pipe_hw->ops.setup_pe(pipe_hw, 563 &pixel_ext); 564 565 /** 566 * when programmed in multirect mode, scalar block will be 567 * bypassed. Still we need to update alpha and bitwidth 568 * ONLY for RECT0 569 */ 570 if (pipe_hw->ops.setup_scaler && 571 pipe->multirect_index != DPU_SSPP_RECT_1) 572 pipe_hw->ops.setup_scaler(pipe_hw, 573 &scaler3_cfg, 574 fmt); 575 } 576 577 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 578 struct dpu_sw_pipe *pipe, 579 struct drm_rect *dst_rect, 580 u32 fill_color, 581 const struct msm_format *fmt) 582 { 583 struct dpu_sw_pipe_cfg pipe_cfg; 584 585 /* update sspp */ 586 if (!pipe->sspp->ops.setup_solidfill) 587 return; 588 589 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 590 591 /* override scaler/decimation if solid fill */ 592 pipe_cfg.dst_rect = *dst_rect; 593 594 pipe_cfg.src_rect.x1 = 0; 595 pipe_cfg.src_rect.y1 = 0; 596 pipe_cfg.src_rect.x2 = 597 drm_rect_width(&pipe_cfg.dst_rect); 598 pipe_cfg.src_rect.y2 = 599 drm_rect_height(&pipe_cfg.dst_rect); 600 601 if (pipe->sspp->ops.setup_format) 602 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 603 604 if (pipe->sspp->ops.setup_rects) 605 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 606 607 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 608 } 609 610 /** 611 * _dpu_plane_color_fill - enables color fill on plane 612 * @pdpu: Pointer to DPU plane object 613 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 614 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 615 */ 616 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 617 uint32_t color, uint32_t alpha) 618 { 619 const struct msm_format *fmt; 620 const struct drm_plane *plane = &pdpu->base; 621 struct msm_drm_private *priv = plane->dev->dev_private; 622 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 623 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 624 625 DPU_DEBUG_PLANE(pdpu, "\n"); 626 627 /* 628 * select fill format to match user property expectation, 629 * h/w only supports RGB variants 630 */ 631 fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0); 632 /* should not happen ever */ 633 if (!fmt) 634 return; 635 636 /* update sspp */ 637 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 638 fill_color, fmt); 639 640 if (pstate->r_pipe.sspp) 641 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 642 fill_color, fmt); 643 } 644 645 static int dpu_plane_prepare_fb(struct drm_plane *plane, 646 struct drm_plane_state *new_state) 647 { 648 struct drm_framebuffer *fb = new_state->fb; 649 struct dpu_plane *pdpu = to_dpu_plane(plane); 650 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 651 struct dpu_hw_fmt_layout layout; 652 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 653 int ret; 654 655 if (!new_state->fb) 656 return 0; 657 658 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 659 660 /* cache aspace */ 661 pstate->aspace = kms->base.aspace; 662 663 /* 664 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 665 * we can use msm_atomic_prepare_fb() instead of doing the 666 * implicit fence and fb prepare by hand here. 667 */ 668 drm_gem_plane_helper_prepare_fb(plane, new_state); 669 670 if (pstate->aspace) { 671 ret = msm_framebuffer_prepare(new_state->fb, 672 pstate->aspace, pstate->needs_dirtyfb); 673 if (ret) { 674 DPU_ERROR("failed to prepare framebuffer\n"); 675 return ret; 676 } 677 } 678 679 /* validate framebuffer layout before commit */ 680 ret = dpu_format_populate_layout(pstate->aspace, 681 new_state->fb, &layout); 682 if (ret) { 683 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 684 return ret; 685 } 686 687 return 0; 688 } 689 690 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 691 struct drm_plane_state *old_state) 692 { 693 struct dpu_plane *pdpu = to_dpu_plane(plane); 694 struct dpu_plane_state *old_pstate; 695 696 if (!old_state || !old_state->fb) 697 return; 698 699 old_pstate = to_dpu_plane_state(old_state); 700 701 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 702 703 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 704 old_pstate->needs_dirtyfb); 705 } 706 707 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 708 const struct dpu_sspp_sub_blks *sblk, 709 struct drm_rect src, const struct msm_format *fmt) 710 { 711 size_t num_formats; 712 const u32 *supported_formats; 713 714 if (!sblk->rotation_cfg) { 715 DPU_ERROR("invalid rotation cfg\n"); 716 return -EINVAL; 717 } 718 719 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 720 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 721 src.y2, sblk->rotation_cfg->rot_maxheight); 722 return -EINVAL; 723 } 724 725 supported_formats = sblk->rotation_cfg->rot_format_list; 726 num_formats = sblk->rotation_cfg->rot_num_formats; 727 728 if (!MSM_FORMAT_IS_UBWC(fmt) || 729 !dpu_find_format(fmt->pixel_format, supported_formats, num_formats)) 730 return -EINVAL; 731 732 return 0; 733 } 734 735 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 736 struct dpu_sw_pipe *pipe, 737 struct dpu_sw_pipe_cfg *pipe_cfg, 738 const struct msm_format *fmt, 739 const struct drm_display_mode *mode) 740 { 741 uint32_t min_src_size; 742 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 743 744 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; 745 746 if (MSM_FORMAT_IS_YUV(fmt) && 747 (!pipe->sspp->cap->sblk->scaler_blk.len || 748 !pipe->sspp->cap->sblk->csc_blk.len)) { 749 DPU_DEBUG_PLANE(pdpu, 750 "plane doesn't have scaler/csc for yuv\n"); 751 return -EINVAL; 752 } 753 754 /* check src bounds */ 755 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 756 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 757 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 758 DRM_RECT_ARG(&pipe_cfg->src_rect)); 759 return -E2BIG; 760 } 761 762 /* valid yuv image */ 763 if (MSM_FORMAT_IS_YUV(fmt) && 764 (pipe_cfg->src_rect.x1 & 0x1 || 765 pipe_cfg->src_rect.y1 & 0x1 || 766 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 767 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 768 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 769 DRM_RECT_ARG(&pipe_cfg->src_rect)); 770 return -EINVAL; 771 } 772 773 /* min dst support */ 774 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 775 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 776 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 777 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 778 return -EINVAL; 779 } 780 781 /* max clk check */ 782 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 783 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 784 return -E2BIG; 785 } 786 787 return 0; 788 } 789 790 static int dpu_plane_atomic_check(struct drm_plane *plane, 791 struct drm_atomic_state *state) 792 { 793 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 794 plane); 795 int ret = 0, min_scale; 796 struct dpu_plane *pdpu = to_dpu_plane(plane); 797 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 798 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 799 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 800 struct dpu_sw_pipe *pipe = &pstate->pipe; 801 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 802 const struct drm_crtc_state *crtc_state = NULL; 803 const struct msm_format *fmt; 804 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 805 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 806 struct drm_rect fb_rect = { 0 }; 807 uint32_t max_linewidth; 808 unsigned int rotation; 809 uint32_t supported_rotations; 810 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 811 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 812 813 if (new_plane_state->crtc) 814 crtc_state = drm_atomic_get_new_crtc_state(state, 815 new_plane_state->crtc); 816 817 min_scale = FRAC_16_16(1, sblk->maxupscale); 818 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 819 min_scale, 820 sblk->maxdwnscale << 16, 821 true, true); 822 if (ret) { 823 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 824 return ret; 825 } 826 if (!new_plane_state->visible) 827 return 0; 828 829 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 830 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 831 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 832 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 833 r_pipe->sspp = NULL; 834 835 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 836 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 837 DPU_ERROR("> %d plane stages assigned\n", 838 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 839 return -EINVAL; 840 } 841 842 pipe_cfg->src_rect = new_plane_state->src; 843 844 /* state->src is 16.16, src_rect is not */ 845 pipe_cfg->src_rect.x1 >>= 16; 846 pipe_cfg->src_rect.x2 >>= 16; 847 pipe_cfg->src_rect.y1 >>= 16; 848 pipe_cfg->src_rect.y2 >>= 16; 849 850 pipe_cfg->dst_rect = new_plane_state->dst; 851 852 fb_rect.x2 = new_plane_state->fb->width; 853 fb_rect.y2 = new_plane_state->fb->height; 854 855 /* Ensure fb size is supported */ 856 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || 857 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { 858 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 859 DRM_RECT_ARG(&fb_rect)); 860 return -E2BIG; 861 } 862 863 fmt = msm_framebuffer_format(new_plane_state->fb); 864 865 max_linewidth = pdpu->catalog->caps->max_linewidth; 866 867 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 868 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 869 /* 870 * In parallel multirect case only the half of the usual width 871 * is supported for tiled formats. If we are here, we know that 872 * full width is more than max_linewidth, thus each rect is 873 * wider than allowed. 874 */ 875 if (MSM_FORMAT_IS_UBWC(fmt) && 876 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 877 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 878 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 879 return -E2BIG; 880 } 881 882 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 883 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 884 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 885 return -E2BIG; 886 } 887 888 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 889 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 890 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 891 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 892 MSM_FORMAT_IS_YUV(fmt)) { 893 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 894 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 895 return -E2BIG; 896 } 897 898 /* 899 * Use multirect for wide plane. We do not support dynamic 900 * assignment of SSPPs, so we know the configuration. 901 */ 902 pipe->multirect_index = DPU_SSPP_RECT_0; 903 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 904 905 r_pipe->sspp = pipe->sspp; 906 r_pipe->multirect_index = DPU_SSPP_RECT_1; 907 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 908 909 *r_pipe_cfg = *pipe_cfg; 910 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 911 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 912 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 913 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 914 } 915 916 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); 917 if (ret) 918 return ret; 919 920 if (r_pipe->sspp) { 921 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, 922 &crtc_state->adjusted_mode); 923 if (ret) 924 return ret; 925 } 926 927 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 928 929 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 930 supported_rotations |= DRM_MODE_ROTATE_90; 931 932 rotation = drm_rotation_simplify(new_plane_state->rotation, 933 supported_rotations); 934 935 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 936 (rotation & DRM_MODE_ROTATE_90)) { 937 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 938 if (ret) 939 return ret; 940 } 941 942 pstate->rotation = rotation; 943 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 944 945 return 0; 946 } 947 948 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 949 { 950 const struct msm_format *format = 951 msm_framebuffer_format(pdpu->base.state->fb); 952 const struct dpu_csc_cfg *csc_ptr; 953 954 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 955 return; 956 957 csc_ptr = _dpu_plane_get_csc(pipe, format); 958 if (!csc_ptr) 959 return; 960 961 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 962 csc_ptr->csc_mv[0], 963 csc_ptr->csc_mv[1], 964 csc_ptr->csc_mv[2]); 965 966 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 967 968 } 969 970 void dpu_plane_flush(struct drm_plane *plane) 971 { 972 struct dpu_plane *pdpu; 973 struct dpu_plane_state *pstate; 974 975 if (!plane || !plane->state) { 976 DPU_ERROR("invalid plane\n"); 977 return; 978 } 979 980 pdpu = to_dpu_plane(plane); 981 pstate = to_dpu_plane_state(plane->state); 982 983 /* 984 * These updates have to be done immediately before the plane flush 985 * timing, and may not be moved to the atomic_update/mode_set functions. 986 */ 987 if (pdpu->is_error) 988 /* force white frame with 100% alpha pipe output on error */ 989 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 990 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 991 /* force 100% alpha */ 992 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 993 else { 994 dpu_plane_flush_csc(pdpu, &pstate->pipe); 995 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 996 } 997 998 /* flag h/w flush complete */ 999 if (plane->state) 1000 pstate->pending = false; 1001 } 1002 1003 /** 1004 * dpu_plane_set_error: enable/disable error condition 1005 * @plane: pointer to drm_plane structure 1006 * @error: error value to set 1007 */ 1008 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1009 { 1010 struct dpu_plane *pdpu; 1011 1012 if (!plane) 1013 return; 1014 1015 pdpu = to_dpu_plane(plane); 1016 pdpu->is_error = error; 1017 } 1018 1019 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1020 struct dpu_sw_pipe *pipe, 1021 struct dpu_sw_pipe_cfg *pipe_cfg, 1022 const struct msm_format *fmt, 1023 int frame_rate, 1024 struct dpu_hw_fmt_layout *layout) 1025 { 1026 uint32_t src_flags; 1027 struct dpu_plane *pdpu = to_dpu_plane(plane); 1028 struct drm_plane_state *state = plane->state; 1029 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1030 1031 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1032 trace_dpu_plane_set_scanout(pipe, layout); 1033 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1034 } 1035 1036 /* override for color fill */ 1037 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1038 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1039 1040 /* skip remaining processing on color fill */ 1041 return; 1042 } 1043 1044 if (pipe->sspp->ops.setup_rects) { 1045 pipe->sspp->ops.setup_rects(pipe, 1046 pipe_cfg); 1047 } 1048 1049 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1050 1051 if (pipe->sspp->ops.setup_multirect) 1052 pipe->sspp->ops.setup_multirect( 1053 pipe); 1054 1055 if (pipe->sspp->ops.setup_format) { 1056 unsigned int rotation = pstate->rotation; 1057 1058 src_flags = 0x0; 1059 1060 if (rotation & DRM_MODE_REFLECT_X) 1061 src_flags |= DPU_SSPP_FLIP_LR; 1062 1063 if (rotation & DRM_MODE_REFLECT_Y) 1064 src_flags |= DPU_SSPP_FLIP_UD; 1065 1066 if (rotation & DRM_MODE_ROTATE_90) 1067 src_flags |= DPU_SSPP_ROT_90; 1068 1069 /* update format */ 1070 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1071 1072 if (pipe->sspp->ops.setup_cdp) { 1073 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1074 1075 pipe->sspp->ops.setup_cdp(pipe, fmt, 1076 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1077 } 1078 } 1079 1080 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1081 1082 if (pipe->sspp->idx != SSPP_CURSOR0 && 1083 pipe->sspp->idx != SSPP_CURSOR1) 1084 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1085 1086 if (pstate->needs_qos_remap) 1087 _dpu_plane_set_qos_remap(plane, pipe); 1088 } 1089 1090 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1091 { 1092 struct dpu_plane *pdpu = to_dpu_plane(plane); 1093 struct drm_plane_state *state = plane->state; 1094 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1095 struct dpu_sw_pipe *pipe = &pstate->pipe; 1096 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1097 struct drm_crtc *crtc = state->crtc; 1098 struct drm_framebuffer *fb = state->fb; 1099 bool is_rt_pipe; 1100 const struct msm_format *fmt = 1101 msm_framebuffer_format(fb); 1102 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1103 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1104 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 1105 struct msm_gem_address_space *aspace = kms->base.aspace; 1106 struct dpu_hw_fmt_layout layout; 1107 bool layout_valid = false; 1108 int ret; 1109 1110 ret = dpu_format_populate_layout(aspace, fb, &layout); 1111 if (ret) 1112 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 1113 else 1114 layout_valid = true; 1115 1116 pstate->pending = true; 1117 1118 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1119 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1120 pdpu->is_rt_pipe = is_rt_pipe; 1121 1122 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1123 ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1124 crtc->base.id, DRM_RECT_ARG(&state->dst), 1125 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); 1126 1127 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1128 drm_mode_vrefresh(&crtc->mode), 1129 layout_valid ? &layout : NULL); 1130 1131 if (r_pipe->sspp) { 1132 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1133 drm_mode_vrefresh(&crtc->mode), 1134 layout_valid ? &layout : NULL); 1135 } 1136 1137 if (pstate->needs_qos_remap) 1138 pstate->needs_qos_remap = false; 1139 1140 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1141 &crtc->mode, pipe_cfg); 1142 1143 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1144 1145 if (r_pipe->sspp) { 1146 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1147 1148 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1149 } 1150 } 1151 1152 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1153 { 1154 struct drm_plane_state *state = plane->state; 1155 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1156 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1157 1158 trace_dpu_plane_disable(DRMID(plane), false, 1159 pstate->pipe.multirect_mode); 1160 1161 if (r_pipe->sspp) { 1162 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1163 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1164 1165 if (r_pipe->sspp->ops.setup_multirect) 1166 r_pipe->sspp->ops.setup_multirect(r_pipe); 1167 } 1168 1169 pstate->pending = true; 1170 } 1171 1172 static void dpu_plane_atomic_update(struct drm_plane *plane, 1173 struct drm_atomic_state *state) 1174 { 1175 struct dpu_plane *pdpu = to_dpu_plane(plane); 1176 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1177 plane); 1178 1179 pdpu->is_error = false; 1180 1181 DPU_DEBUG_PLANE(pdpu, "\n"); 1182 1183 if (!new_state->visible) { 1184 _dpu_plane_atomic_disable(plane); 1185 } else { 1186 dpu_plane_sspp_atomic_update(plane); 1187 } 1188 } 1189 1190 static void dpu_plane_destroy_state(struct drm_plane *plane, 1191 struct drm_plane_state *state) 1192 { 1193 __drm_atomic_helper_plane_destroy_state(state); 1194 kfree(to_dpu_plane_state(state)); 1195 } 1196 1197 static struct drm_plane_state * 1198 dpu_plane_duplicate_state(struct drm_plane *plane) 1199 { 1200 struct dpu_plane *pdpu; 1201 struct dpu_plane_state *pstate; 1202 struct dpu_plane_state *old_state; 1203 1204 if (!plane) { 1205 DPU_ERROR("invalid plane\n"); 1206 return NULL; 1207 } else if (!plane->state) { 1208 DPU_ERROR("invalid plane state\n"); 1209 return NULL; 1210 } 1211 1212 old_state = to_dpu_plane_state(plane->state); 1213 pdpu = to_dpu_plane(plane); 1214 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1215 if (!pstate) { 1216 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1217 return NULL; 1218 } 1219 1220 DPU_DEBUG_PLANE(pdpu, "\n"); 1221 1222 pstate->pending = false; 1223 1224 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1225 1226 return &pstate->base; 1227 } 1228 1229 static const char * const multirect_mode_name[] = { 1230 [DPU_SSPP_MULTIRECT_NONE] = "none", 1231 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1232 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1233 }; 1234 1235 static const char * const multirect_index_name[] = { 1236 [DPU_SSPP_RECT_SOLO] = "solo", 1237 [DPU_SSPP_RECT_0] = "rect_0", 1238 [DPU_SSPP_RECT_1] = "rect_1", 1239 }; 1240 1241 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1242 { 1243 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1244 return "unknown"; 1245 1246 return multirect_mode_name[mode]; 1247 } 1248 1249 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1250 { 1251 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1252 return "unknown"; 1253 1254 return multirect_index_name[index]; 1255 } 1256 1257 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1258 const struct drm_plane_state *state) 1259 { 1260 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1261 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1262 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1263 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1264 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1265 1266 drm_printf(p, "\tstage=%d\n", pstate->stage); 1267 1268 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1269 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); 1270 drm_printf(p, "\tmultirect_index[0]=%s\n", 1271 dpu_get_multirect_index(pipe->multirect_index)); 1272 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1273 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1274 1275 if (r_pipe->sspp) { 1276 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1277 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1278 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1279 drm_printf(p, "\tmultirect_index[1]=%s\n", 1280 dpu_get_multirect_index(r_pipe->multirect_index)); 1281 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1282 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1283 } 1284 } 1285 1286 static void dpu_plane_reset(struct drm_plane *plane) 1287 { 1288 struct dpu_plane *pdpu; 1289 struct dpu_plane_state *pstate; 1290 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1291 1292 if (!plane) { 1293 DPU_ERROR("invalid plane\n"); 1294 return; 1295 } 1296 1297 pdpu = to_dpu_plane(plane); 1298 DPU_DEBUG_PLANE(pdpu, "\n"); 1299 1300 /* remove previous state, if present */ 1301 if (plane->state) { 1302 dpu_plane_destroy_state(plane, plane->state); 1303 plane->state = NULL; 1304 } 1305 1306 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1307 if (!pstate) { 1308 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1309 return; 1310 } 1311 1312 /* 1313 * Set the SSPP here until we have proper virtualized DPU planes. 1314 * This is the place where the state is allocated, so fill it fully. 1315 */ 1316 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1317 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1318 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1319 1320 pstate->r_pipe.sspp = NULL; 1321 1322 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1323 } 1324 1325 #ifdef CONFIG_DEBUG_FS 1326 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1327 { 1328 struct dpu_plane *pdpu = to_dpu_plane(plane); 1329 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1330 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1331 1332 if (!pdpu->is_rt_pipe) 1333 return; 1334 1335 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1336 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1337 if (pstate->r_pipe.sspp) 1338 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1339 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1340 } 1341 #endif 1342 1343 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1344 uint32_t format, uint64_t modifier) 1345 { 1346 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1347 bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0) && 1348 (dpu_kms->mdss->ubwc_dec_version == 0); 1349 1350 if (modifier == DRM_FORMAT_MOD_LINEAR) 1351 return true; 1352 1353 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc) 1354 return dpu_find_format(format, qcom_compressed_supported_formats, 1355 ARRAY_SIZE(qcom_compressed_supported_formats)); 1356 1357 return false; 1358 } 1359 1360 static const struct drm_plane_funcs dpu_plane_funcs = { 1361 .update_plane = drm_atomic_helper_update_plane, 1362 .disable_plane = drm_atomic_helper_disable_plane, 1363 .reset = dpu_plane_reset, 1364 .atomic_duplicate_state = dpu_plane_duplicate_state, 1365 .atomic_destroy_state = dpu_plane_destroy_state, 1366 .atomic_print_state = dpu_plane_atomic_print_state, 1367 .format_mod_supported = dpu_plane_format_mod_supported, 1368 }; 1369 1370 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1371 .prepare_fb = dpu_plane_prepare_fb, 1372 .cleanup_fb = dpu_plane_cleanup_fb, 1373 .atomic_check = dpu_plane_atomic_check, 1374 .atomic_update = dpu_plane_atomic_update, 1375 }; 1376 1377 /* initialize plane */ 1378 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1379 uint32_t pipe, enum drm_plane_type type, 1380 unsigned long possible_crtcs) 1381 { 1382 struct drm_plane *plane = NULL; 1383 const uint32_t *format_list; 1384 struct dpu_plane *pdpu; 1385 struct msm_drm_private *priv = dev->dev_private; 1386 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1387 struct dpu_hw_sspp *pipe_hw; 1388 uint32_t num_formats; 1389 uint32_t supported_rotations; 1390 int ret; 1391 1392 /* initialize underlying h/w driver */ 1393 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1394 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1395 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1396 return ERR_PTR(-EINVAL); 1397 } 1398 1399 format_list = pipe_hw->cap->sblk->format_list; 1400 num_formats = pipe_hw->cap->sblk->num_formats; 1401 1402 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 1403 0xff, &dpu_plane_funcs, 1404 format_list, num_formats, 1405 supported_format_modifiers, type, NULL); 1406 if (IS_ERR(pdpu)) 1407 return ERR_CAST(pdpu); 1408 1409 /* cache local stuff for later */ 1410 plane = &pdpu->base; 1411 pdpu->pipe = pipe; 1412 1413 pdpu->catalog = kms->catalog; 1414 1415 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1416 if (ret) 1417 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1418 1419 drm_plane_create_alpha_property(plane); 1420 drm_plane_create_blend_mode_property(plane, 1421 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1422 BIT(DRM_MODE_BLEND_PREMULTI) | 1423 BIT(DRM_MODE_BLEND_COVERAGE)); 1424 1425 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1426 1427 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1428 supported_rotations |= DRM_MODE_ROTATE_MASK; 1429 1430 drm_plane_create_rotation_property(plane, 1431 DRM_MODE_ROTATE_0, supported_rotations); 1432 1433 drm_plane_enable_fb_damage_clips(plane); 1434 1435 /* success! finalize initialization */ 1436 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1437 1438 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1439 pipe, plane->base.id); 1440 return plane; 1441 } 1442