1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_hw_util.h" 25 #include "dpu_trace.h" 26 #include "dpu_crtc.h" 27 #include "dpu_vbif.h" 28 #include "dpu_plane.h" 29 30 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 32 33 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 34 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 35 36 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 37 #define PHASE_STEP_SHIFT 21 38 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 39 #define PHASE_RESIDUAL 15 40 41 #define SHARP_STRENGTH_DEFAULT 32 42 #define SHARP_EDGE_THR_DEFAULT 112 43 #define SHARP_SMOOTH_THR_DEFAULT 8 44 #define SHARP_NOISE_THR_DEFAULT 2 45 46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 47 #define DPU_ZPOS_MAX 255 48 49 /* 50 * Default Preload Values 51 */ 52 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 53 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 54 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 55 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 56 57 #define DEFAULT_REFRESH_RATE 60 58 59 static const uint32_t qcom_compressed_supported_formats[] = { 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_ARGB8888, 62 DRM_FORMAT_XBGR8888, 63 DRM_FORMAT_XRGB8888, 64 DRM_FORMAT_ARGB2101010, 65 DRM_FORMAT_XRGB2101010, 66 DRM_FORMAT_BGR565, 67 68 DRM_FORMAT_NV12, 69 DRM_FORMAT_P010, 70 }; 71 72 /* 73 * struct dpu_plane - local dpu plane structure 74 * @aspace: address space pointer 75 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 76 * @catalog: Points to dpu catalog structure 77 * @revalidate: force revalidation of all the plane properties 78 */ 79 struct dpu_plane { 80 struct drm_plane base; 81 82 enum dpu_sspp pipe; 83 84 uint32_t color_fill; 85 bool is_error; 86 bool is_rt_pipe; 87 const struct dpu_mdss_cfg *catalog; 88 }; 89 90 static const uint64_t supported_format_modifiers[] = { 91 DRM_FORMAT_MOD_QCOM_COMPRESSED, 92 DRM_FORMAT_MOD_LINEAR, 93 DRM_FORMAT_MOD_INVALID 94 }; 95 96 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 97 98 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 99 { 100 struct msm_drm_private *priv = plane->dev->dev_private; 101 102 return to_dpu_kms(priv->kms); 103 } 104 105 /** 106 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 107 * @catalog: Points to dpu catalog structure 108 * @fmt: Pointer to source buffer format 109 * @mode: Pointer to drm display mode 110 * @pipe_cfg: Pointer to pipe configuration 111 * Result: Updates calculated bandwidth in the plane state. 112 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 113 * Prefill BW Equation: line src bytes * line_time 114 */ 115 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 116 const struct dpu_format *fmt, 117 const struct drm_display_mode *mode, 118 struct dpu_sw_pipe_cfg *pipe_cfg) 119 { 120 int src_width, src_height, dst_height, fps; 121 u64 plane_pixel_rate, plane_bit_rate; 122 u64 plane_prefill_bw; 123 u64 plane_bw; 124 u32 hw_latency_lines; 125 u64 scale_factor; 126 int vbp, vpw, vfp; 127 128 src_width = drm_rect_width(&pipe_cfg->src_rect); 129 src_height = drm_rect_height(&pipe_cfg->src_rect); 130 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 131 fps = drm_mode_vrefresh(mode); 132 vbp = mode->vtotal - mode->vsync_end; 133 vpw = mode->vsync_end - mode->vsync_start; 134 vfp = mode->vsync_start - mode->vdisplay; 135 hw_latency_lines = catalog->perf->min_prefill_lines; 136 scale_factor = src_height > dst_height ? 137 mult_frac(src_height, 1, dst_height) : 1; 138 139 plane_pixel_rate = src_width * mode->vtotal * fps; 140 plane_bit_rate = plane_pixel_rate * fmt->bpp; 141 142 plane_bw = plane_bit_rate * scale_factor; 143 144 plane_prefill_bw = plane_bw * hw_latency_lines; 145 146 if ((vbp+vpw) > hw_latency_lines) 147 do_div(plane_prefill_bw, (vbp+vpw)); 148 else if ((vbp+vpw+vfp) < hw_latency_lines) 149 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 150 else 151 do_div(plane_prefill_bw, hw_latency_lines); 152 153 154 return max(plane_bw, plane_prefill_bw); 155 } 156 157 /** 158 * _dpu_plane_calc_clk - calculate clock required for a plane 159 * @mode: Pointer to drm display mode 160 * @pipe_cfg: Pointer to pipe configuration 161 * Result: Updates calculated clock in the plane state. 162 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 163 */ 164 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 165 struct dpu_sw_pipe_cfg *pipe_cfg) 166 { 167 int dst_width, src_height, dst_height, fps; 168 u64 plane_clk; 169 170 src_height = drm_rect_height(&pipe_cfg->src_rect); 171 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 172 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 173 fps = drm_mode_vrefresh(mode); 174 175 plane_clk = 176 dst_width * mode->vtotal * fps; 177 178 if (src_height > dst_height) { 179 plane_clk *= src_height; 180 do_div(plane_clk, dst_height); 181 } 182 183 return plane_clk; 184 } 185 186 /** 187 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 188 * @plane: Pointer to drm plane 189 * @pipe: Pointer to software pipe 190 * @lut_usage: LUT usecase 191 * @fmt: Pointer to source buffer format 192 * @src_width: width of source buffer 193 * Return: fill level corresponding to the source buffer/format or 0 if error 194 */ 195 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 196 struct dpu_sw_pipe *pipe, 197 enum dpu_qos_lut_usage lut_usage, 198 const struct dpu_format *fmt, u32 src_width) 199 { 200 struct dpu_plane *pdpu; 201 u32 fixed_buff_size; 202 u32 total_fl; 203 204 if (!fmt || !pipe || !src_width || !fmt->bpp) { 205 DPU_ERROR("invalid arguments\n"); 206 return 0; 207 } 208 209 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 210 return 0; 211 212 pdpu = to_dpu_plane(plane); 213 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 214 215 /* FIXME: in multirect case account for the src_width of all the planes */ 216 217 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 218 if (fmt->chroma_sample == DPU_CHROMA_420) { 219 /* NV12 */ 220 total_fl = (fixed_buff_size / 2) / 221 ((src_width + 32) * fmt->bpp); 222 } else { 223 /* non NV12 */ 224 total_fl = (fixed_buff_size / 2) * 2 / 225 ((src_width + 32) * fmt->bpp); 226 } 227 } else { 228 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 229 total_fl = (fixed_buff_size / 2) * 2 / 230 ((src_width + 32) * fmt->bpp); 231 } else { 232 total_fl = (fixed_buff_size) * 2 / 233 ((src_width + 32) * fmt->bpp); 234 } 235 } 236 237 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 238 pipe->sspp->idx - SSPP_VIG0, 239 (char *)&fmt->base.pixel_format, 240 src_width, total_fl); 241 242 return total_fl; 243 } 244 245 /** 246 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 247 * @plane: Pointer to drm plane 248 * @pipe: Pointer to software pipe 249 * @fmt: Pointer to source buffer format 250 * @pipe_cfg: Pointer to pipe configuration 251 */ 252 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 253 struct dpu_sw_pipe *pipe, 254 const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 255 { 256 struct dpu_plane *pdpu = to_dpu_plane(plane); 257 struct dpu_hw_qos_cfg cfg; 258 u32 total_fl, lut_usage; 259 260 if (!pdpu->is_rt_pipe) { 261 lut_usage = DPU_QOS_LUT_USAGE_NRT; 262 } else { 263 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 264 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 265 else 266 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 267 } 268 269 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 270 drm_rect_width(&pipe_cfg->src_rect)); 271 272 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 273 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 274 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 275 276 if (pipe->sspp->idx != SSPP_CURSOR0 && 277 pipe->sspp->idx != SSPP_CURSOR1 && 278 pdpu->is_rt_pipe) 279 cfg.danger_safe_en = true; 280 281 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 282 pdpu->pipe - SSPP_VIG0, 283 cfg.danger_safe_en, 284 pdpu->is_rt_pipe); 285 286 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 287 (fmt) ? fmt->base.pixel_format : 0, 288 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 289 290 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 291 pdpu->pipe - SSPP_VIG0, 292 fmt ? (char *)&fmt->base.pixel_format : NULL, 293 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 294 295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 296 (fmt) ? fmt->base.pixel_format : 0, 297 (fmt) ? fmt->fetch_mode : 0, 298 cfg.danger_lut, 299 cfg.safe_lut); 300 301 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 302 pdpu->pipe - SSPP_VIG0, 303 fmt ? (char *)&fmt->base.pixel_format : NULL, 304 fmt ? fmt->fetch_mode : -1, 305 cfg.danger_lut, 306 cfg.safe_lut); 307 308 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 309 } 310 311 /** 312 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 313 * @plane: Pointer to drm plane 314 * @pipe: Pointer to software pipe 315 * @enable: true to enable QoS control 316 */ 317 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 318 struct dpu_sw_pipe *pipe, 319 bool enable) 320 { 321 struct dpu_plane *pdpu = to_dpu_plane(plane); 322 323 if (!pdpu->is_rt_pipe) 324 enable = false; 325 326 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 327 pdpu->pipe - SSPP_VIG0, 328 enable, 329 pdpu->is_rt_pipe); 330 331 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 332 enable); 333 } 334 335 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp, 336 struct dpu_hw_mdp *mdp, 337 bool enable, bool *forced_on) 338 { 339 if (sspp->ops.setup_clk_force_ctrl) { 340 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable); 341 return true; 342 } 343 344 if (mdp->ops.setup_clk_force_ctrl) { 345 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); 346 return true; 347 } 348 349 return false; 350 } 351 352 /** 353 * _dpu_plane_set_ot_limit - set OT limit for the given plane 354 * @plane: Pointer to drm plane 355 * @pipe: Pointer to software pipe 356 * @pipe_cfg: Pointer to pipe configuration 357 * @frame_rate: CRTC's frame rate 358 */ 359 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 360 struct dpu_sw_pipe *pipe, 361 struct dpu_sw_pipe_cfg *pipe_cfg, 362 int frame_rate) 363 { 364 struct dpu_plane *pdpu = to_dpu_plane(plane); 365 struct dpu_vbif_set_ot_params ot_params; 366 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 367 bool forced_on = false; 368 369 memset(&ot_params, 0, sizeof(ot_params)); 370 ot_params.xin_id = pipe->sspp->cap->xin_id; 371 ot_params.num = pipe->sspp->idx - SSPP_NONE; 372 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 373 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 374 ot_params.is_wfd = !pdpu->is_rt_pipe; 375 ot_params.frame_rate = frame_rate; 376 ot_params.vbif_idx = VBIF_RT; 377 ot_params.rd = true; 378 379 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 380 true, &forced_on)) 381 return; 382 383 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 384 385 if (forced_on) 386 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 387 false, &forced_on); 388 } 389 390 /** 391 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 392 * @plane: Pointer to drm plane 393 * @pipe: Pointer to software pipe 394 */ 395 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 396 struct dpu_sw_pipe *pipe) 397 { 398 struct dpu_plane *pdpu = to_dpu_plane(plane); 399 struct dpu_vbif_set_qos_params qos_params; 400 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 401 bool forced_on = false; 402 403 memset(&qos_params, 0, sizeof(qos_params)); 404 qos_params.vbif_idx = VBIF_RT; 405 qos_params.xin_id = pipe->sspp->cap->xin_id; 406 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 407 qos_params.is_rt = pdpu->is_rt_pipe; 408 409 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n", 410 qos_params.num, 411 qos_params.vbif_idx, 412 qos_params.xin_id, qos_params.is_rt); 413 414 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 415 true, &forced_on)) 416 return; 417 418 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 419 420 if (forced_on) 421 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 422 false, &forced_on); 423 } 424 425 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 426 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 427 struct dpu_hw_scaler3_cfg *scale_cfg, 428 const struct dpu_format *fmt, 429 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 430 unsigned int rotation) 431 { 432 uint32_t i; 433 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 434 435 /* 436 * For inline rotation cases, scaler config is post-rotation, 437 * so swap the dimensions here. However, pixel extension will 438 * need pre-rotation settings. 439 */ 440 if (inline_rotation) 441 swap(src_w, src_h); 442 443 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 444 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 445 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 446 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 447 448 449 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 450 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 451 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 452 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 453 454 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 455 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 456 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 458 459 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 461 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 462 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 463 464 for (i = 0; i < DPU_MAX_PLANES; i++) { 465 scale_cfg->src_width[i] = src_w; 466 scale_cfg->src_height[i] = src_h; 467 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 468 scale_cfg->src_width[i] /= chroma_subsmpl_h; 469 scale_cfg->src_height[i] /= chroma_subsmpl_v; 470 } 471 472 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) { 473 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 474 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 475 } else { 476 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 477 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 478 } 479 } 480 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 481 && (src_w == dst_w)) 482 return; 483 484 scale_cfg->dst_width = dst_w; 485 scale_cfg->dst_height = dst_h; 486 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 487 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 488 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 489 scale_cfg->lut_flag = 0; 490 scale_cfg->blend_cfg = 1; 491 scale_cfg->enable = 1; 492 } 493 494 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 495 struct dpu_hw_pixel_ext *pixel_ext, 496 uint32_t src_w, uint32_t src_h, 497 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 498 { 499 int i; 500 501 for (i = 0; i < DPU_MAX_PLANES; i++) { 502 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 503 src_w /= chroma_subsmpl_h; 504 src_h /= chroma_subsmpl_v; 505 } 506 507 pixel_ext->num_ext_pxls_top[i] = src_h; 508 pixel_ext->num_ext_pxls_left[i] = src_w; 509 } 510 } 511 512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 513 const struct dpu_format *fmt) 514 { 515 const struct dpu_csc_cfg *csc_ptr; 516 517 if (!DPU_FORMAT_IS_YUV(fmt)) 518 return NULL; 519 520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 521 csc_ptr = &dpu_csc10_YUV2RGB_601L; 522 else 523 csc_ptr = &dpu_csc_YUV2RGB_601L; 524 525 return csc_ptr; 526 } 527 528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 529 const struct dpu_format *fmt, bool color_fill, 530 struct dpu_sw_pipe_cfg *pipe_cfg, 531 unsigned int rotation) 532 { 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 534 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 535 struct dpu_hw_scaler3_cfg scaler3_cfg; 536 struct dpu_hw_pixel_ext pixel_ext; 537 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 538 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 539 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 540 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 541 542 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 543 memset(&pixel_ext, 0, sizeof(pixel_ext)); 544 545 /* don't chroma subsample if decimating */ 546 /* update scaler. calculate default config for QSEED3 */ 547 _dpu_plane_setup_scaler3(pipe_hw, 548 src_width, 549 src_height, 550 dst_width, 551 dst_height, 552 &scaler3_cfg, fmt, 553 info->hsub, info->vsub, 554 rotation); 555 556 /* configure pixel extension based on scalar config */ 557 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 558 src_width, src_height, info->hsub, info->vsub); 559 560 if (pipe_hw->ops.setup_pe) 561 pipe_hw->ops.setup_pe(pipe_hw, 562 &pixel_ext); 563 564 /** 565 * when programmed in multirect mode, scalar block will be 566 * bypassed. Still we need to update alpha and bitwidth 567 * ONLY for RECT0 568 */ 569 if (pipe_hw->ops.setup_scaler && 570 pipe->multirect_index != DPU_SSPP_RECT_1) 571 pipe_hw->ops.setup_scaler(pipe_hw, 572 &scaler3_cfg, 573 fmt); 574 } 575 576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 577 struct dpu_sw_pipe *pipe, 578 struct drm_rect *dst_rect, 579 u32 fill_color, 580 const struct dpu_format *fmt) 581 { 582 struct dpu_sw_pipe_cfg pipe_cfg; 583 584 /* update sspp */ 585 if (!pipe->sspp->ops.setup_solidfill) 586 return; 587 588 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 589 590 /* override scaler/decimation if solid fill */ 591 pipe_cfg.dst_rect = *dst_rect; 592 593 pipe_cfg.src_rect.x1 = 0; 594 pipe_cfg.src_rect.y1 = 0; 595 pipe_cfg.src_rect.x2 = 596 drm_rect_width(&pipe_cfg.dst_rect); 597 pipe_cfg.src_rect.y2 = 598 drm_rect_height(&pipe_cfg.dst_rect); 599 600 if (pipe->sspp->ops.setup_format) 601 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 602 603 if (pipe->sspp->ops.setup_rects) 604 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 607 } 608 609 /** 610 * _dpu_plane_color_fill - enables color fill on plane 611 * @pdpu: Pointer to DPU plane object 612 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 613 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 614 */ 615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 616 uint32_t color, uint32_t alpha) 617 { 618 const struct dpu_format *fmt; 619 const struct drm_plane *plane = &pdpu->base; 620 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 621 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 622 623 DPU_DEBUG_PLANE(pdpu, "\n"); 624 625 /* 626 * select fill format to match user property expectation, 627 * h/w only supports RGB variants 628 */ 629 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 630 /* should not happen ever */ 631 if (!fmt) 632 return; 633 634 /* update sspp */ 635 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 636 fill_color, fmt); 637 638 if (pstate->r_pipe.sspp) 639 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 640 fill_color, fmt); 641 } 642 643 static int dpu_plane_prepare_fb(struct drm_plane *plane, 644 struct drm_plane_state *new_state) 645 { 646 struct drm_framebuffer *fb = new_state->fb; 647 struct dpu_plane *pdpu = to_dpu_plane(plane); 648 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 649 struct dpu_hw_fmt_layout layout; 650 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 651 int ret; 652 653 if (!new_state->fb) 654 return 0; 655 656 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 657 658 /* cache aspace */ 659 pstate->aspace = kms->base.aspace; 660 661 /* 662 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 663 * we can use msm_atomic_prepare_fb() instead of doing the 664 * implicit fence and fb prepare by hand here. 665 */ 666 drm_gem_plane_helper_prepare_fb(plane, new_state); 667 668 if (pstate->aspace) { 669 ret = msm_framebuffer_prepare(new_state->fb, 670 pstate->aspace, pstate->needs_dirtyfb); 671 if (ret) { 672 DPU_ERROR("failed to prepare framebuffer\n"); 673 return ret; 674 } 675 } 676 677 /* validate framebuffer layout before commit */ 678 ret = dpu_format_populate_layout(pstate->aspace, 679 new_state->fb, &layout); 680 if (ret) { 681 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 682 return ret; 683 } 684 685 return 0; 686 } 687 688 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 689 struct drm_plane_state *old_state) 690 { 691 struct dpu_plane *pdpu = to_dpu_plane(plane); 692 struct dpu_plane_state *old_pstate; 693 694 if (!old_state || !old_state->fb) 695 return; 696 697 old_pstate = to_dpu_plane_state(old_state); 698 699 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 700 701 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 702 old_pstate->needs_dirtyfb); 703 } 704 705 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 706 const struct dpu_sspp_sub_blks *sblk, 707 struct drm_rect src, const struct dpu_format *fmt) 708 { 709 size_t num_formats; 710 const u32 *supported_formats; 711 712 if (!sblk->rotation_cfg) { 713 DPU_ERROR("invalid rotation cfg\n"); 714 return -EINVAL; 715 } 716 717 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 718 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 719 src.y2, sblk->rotation_cfg->rot_maxheight); 720 return -EINVAL; 721 } 722 723 supported_formats = sblk->rotation_cfg->rot_format_list; 724 num_formats = sblk->rotation_cfg->rot_num_formats; 725 726 if (!DPU_FORMAT_IS_UBWC(fmt) || 727 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 728 return -EINVAL; 729 730 return 0; 731 } 732 733 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 734 struct dpu_sw_pipe *pipe, 735 struct dpu_sw_pipe_cfg *pipe_cfg, 736 const struct dpu_format *fmt, 737 const struct drm_display_mode *mode) 738 { 739 uint32_t min_src_size; 740 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 741 742 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 743 744 if (DPU_FORMAT_IS_YUV(fmt) && 745 (!pipe->sspp->cap->sblk->scaler_blk.len || 746 !pipe->sspp->cap->sblk->csc_blk.len)) { 747 DPU_DEBUG_PLANE(pdpu, 748 "plane doesn't have scaler/csc for yuv\n"); 749 return -EINVAL; 750 } 751 752 /* check src bounds */ 753 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 754 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 755 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 756 DRM_RECT_ARG(&pipe_cfg->src_rect)); 757 return -E2BIG; 758 } 759 760 /* valid yuv image */ 761 if (DPU_FORMAT_IS_YUV(fmt) && 762 (pipe_cfg->src_rect.x1 & 0x1 || 763 pipe_cfg->src_rect.y1 & 0x1 || 764 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 765 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 766 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 767 DRM_RECT_ARG(&pipe_cfg->src_rect)); 768 return -EINVAL; 769 } 770 771 /* min dst support */ 772 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 773 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 774 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 775 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 776 return -EINVAL; 777 } 778 779 /* max clk check */ 780 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 781 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 782 return -E2BIG; 783 } 784 785 return 0; 786 } 787 788 static int dpu_plane_atomic_check(struct drm_plane *plane, 789 struct drm_atomic_state *state) 790 { 791 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 792 plane); 793 int ret = 0, min_scale; 794 struct dpu_plane *pdpu = to_dpu_plane(plane); 795 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 796 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 797 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 798 struct dpu_sw_pipe *pipe = &pstate->pipe; 799 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 800 const struct drm_crtc_state *crtc_state = NULL; 801 const struct dpu_format *fmt; 802 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 803 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 804 struct drm_rect fb_rect = { 0 }; 805 uint32_t max_linewidth; 806 unsigned int rotation; 807 uint32_t supported_rotations; 808 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 809 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 810 811 if (new_plane_state->crtc) 812 crtc_state = drm_atomic_get_new_crtc_state(state, 813 new_plane_state->crtc); 814 815 min_scale = FRAC_16_16(1, sblk->maxupscale); 816 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 817 min_scale, 818 sblk->maxdwnscale << 16, 819 true, true); 820 if (ret) { 821 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 822 return ret; 823 } 824 if (!new_plane_state->visible) 825 return 0; 826 827 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 828 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 829 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 830 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 831 r_pipe->sspp = NULL; 832 833 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 834 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 835 DPU_ERROR("> %d plane stages assigned\n", 836 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 837 return -EINVAL; 838 } 839 840 pipe_cfg->src_rect = new_plane_state->src; 841 842 /* state->src is 16.16, src_rect is not */ 843 pipe_cfg->src_rect.x1 >>= 16; 844 pipe_cfg->src_rect.x2 >>= 16; 845 pipe_cfg->src_rect.y1 >>= 16; 846 pipe_cfg->src_rect.y2 >>= 16; 847 848 pipe_cfg->dst_rect = new_plane_state->dst; 849 850 fb_rect.x2 = new_plane_state->fb->width; 851 fb_rect.y2 = new_plane_state->fb->height; 852 853 /* Ensure fb size is supported */ 854 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || 855 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { 856 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 857 DRM_RECT_ARG(&fb_rect)); 858 return -E2BIG; 859 } 860 861 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 862 863 max_linewidth = pdpu->catalog->caps->max_linewidth; 864 865 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 866 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 867 /* 868 * In parallel multirect case only the half of the usual width 869 * is supported for tiled formats. If we are here, we know that 870 * full width is more than max_linewidth, thus each rect is 871 * wider than allowed. 872 */ 873 if (DPU_FORMAT_IS_UBWC(fmt) && 874 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 875 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 876 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 877 return -E2BIG; 878 } 879 880 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 881 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 882 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 883 return -E2BIG; 884 } 885 886 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 887 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 888 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 889 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 890 DPU_FORMAT_IS_YUV(fmt)) { 891 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 892 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 893 return -E2BIG; 894 } 895 896 /* 897 * Use multirect for wide plane. We do not support dynamic 898 * assignment of SSPPs, so we know the configuration. 899 */ 900 pipe->multirect_index = DPU_SSPP_RECT_0; 901 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 902 903 r_pipe->sspp = pipe->sspp; 904 r_pipe->multirect_index = DPU_SSPP_RECT_1; 905 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 906 907 *r_pipe_cfg = *pipe_cfg; 908 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 909 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 910 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 911 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 912 } 913 914 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); 915 if (ret) 916 return ret; 917 918 if (r_pipe->sspp) { 919 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, 920 &crtc_state->adjusted_mode); 921 if (ret) 922 return ret; 923 } 924 925 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 926 927 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 928 supported_rotations |= DRM_MODE_ROTATE_90; 929 930 rotation = drm_rotation_simplify(new_plane_state->rotation, 931 supported_rotations); 932 933 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 934 (rotation & DRM_MODE_ROTATE_90)) { 935 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 936 if (ret) 937 return ret; 938 } 939 940 pstate->rotation = rotation; 941 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 942 943 return 0; 944 } 945 946 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 947 { 948 const struct dpu_format *format = 949 to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); 950 const struct dpu_csc_cfg *csc_ptr; 951 952 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 953 return; 954 955 csc_ptr = _dpu_plane_get_csc(pipe, format); 956 if (!csc_ptr) 957 return; 958 959 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 960 csc_ptr->csc_mv[0], 961 csc_ptr->csc_mv[1], 962 csc_ptr->csc_mv[2]); 963 964 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 965 966 } 967 968 void dpu_plane_flush(struct drm_plane *plane) 969 { 970 struct dpu_plane *pdpu; 971 struct dpu_plane_state *pstate; 972 973 if (!plane || !plane->state) { 974 DPU_ERROR("invalid plane\n"); 975 return; 976 } 977 978 pdpu = to_dpu_plane(plane); 979 pstate = to_dpu_plane_state(plane->state); 980 981 /* 982 * These updates have to be done immediately before the plane flush 983 * timing, and may not be moved to the atomic_update/mode_set functions. 984 */ 985 if (pdpu->is_error) 986 /* force white frame with 100% alpha pipe output on error */ 987 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 988 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 989 /* force 100% alpha */ 990 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 991 else { 992 dpu_plane_flush_csc(pdpu, &pstate->pipe); 993 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 994 } 995 996 /* flag h/w flush complete */ 997 if (plane->state) 998 pstate->pending = false; 999 } 1000 1001 /** 1002 * dpu_plane_set_error: enable/disable error condition 1003 * @plane: pointer to drm_plane structure 1004 * @error: error value to set 1005 */ 1006 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1007 { 1008 struct dpu_plane *pdpu; 1009 1010 if (!plane) 1011 return; 1012 1013 pdpu = to_dpu_plane(plane); 1014 pdpu->is_error = error; 1015 } 1016 1017 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1018 struct dpu_sw_pipe *pipe, 1019 struct dpu_sw_pipe_cfg *pipe_cfg, 1020 const struct dpu_format *fmt, 1021 int frame_rate, 1022 struct dpu_hw_fmt_layout *layout) 1023 { 1024 uint32_t src_flags; 1025 struct dpu_plane *pdpu = to_dpu_plane(plane); 1026 struct drm_plane_state *state = plane->state; 1027 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1028 1029 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1030 trace_dpu_plane_set_scanout(pipe, layout); 1031 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1032 } 1033 1034 /* override for color fill */ 1035 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1036 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1037 1038 /* skip remaining processing on color fill */ 1039 return; 1040 } 1041 1042 if (pipe->sspp->ops.setup_rects) { 1043 pipe->sspp->ops.setup_rects(pipe, 1044 pipe_cfg); 1045 } 1046 1047 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1048 1049 if (pipe->sspp->ops.setup_multirect) 1050 pipe->sspp->ops.setup_multirect( 1051 pipe); 1052 1053 if (pipe->sspp->ops.setup_format) { 1054 unsigned int rotation = pstate->rotation; 1055 1056 src_flags = 0x0; 1057 1058 if (rotation & DRM_MODE_REFLECT_X) 1059 src_flags |= DPU_SSPP_FLIP_LR; 1060 1061 if (rotation & DRM_MODE_REFLECT_Y) 1062 src_flags |= DPU_SSPP_FLIP_UD; 1063 1064 if (rotation & DRM_MODE_ROTATE_90) 1065 src_flags |= DPU_SSPP_ROT_90; 1066 1067 /* update format */ 1068 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1069 1070 if (pipe->sspp->ops.setup_cdp) { 1071 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1072 1073 pipe->sspp->ops.setup_cdp(pipe, fmt, 1074 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1075 } 1076 } 1077 1078 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1079 1080 if (pipe->sspp->idx != SSPP_CURSOR0 && 1081 pipe->sspp->idx != SSPP_CURSOR1) 1082 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1083 1084 if (pstate->needs_qos_remap) 1085 _dpu_plane_set_qos_remap(plane, pipe); 1086 } 1087 1088 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1089 { 1090 struct dpu_plane *pdpu = to_dpu_plane(plane); 1091 struct drm_plane_state *state = plane->state; 1092 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1093 struct dpu_sw_pipe *pipe = &pstate->pipe; 1094 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1095 struct drm_crtc *crtc = state->crtc; 1096 struct drm_framebuffer *fb = state->fb; 1097 bool is_rt_pipe; 1098 const struct dpu_format *fmt = 1099 to_dpu_format(msm_framebuffer_format(fb)); 1100 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1101 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1102 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 1103 struct msm_gem_address_space *aspace = kms->base.aspace; 1104 struct dpu_hw_fmt_layout layout; 1105 bool layout_valid = false; 1106 int ret; 1107 1108 ret = dpu_format_populate_layout(aspace, fb, &layout); 1109 if (ret) 1110 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 1111 else 1112 layout_valid = true; 1113 1114 pstate->pending = true; 1115 1116 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1117 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1118 pdpu->is_rt_pipe = is_rt_pipe; 1119 1120 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1121 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1122 crtc->base.id, DRM_RECT_ARG(&state->dst), 1123 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1124 1125 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1126 drm_mode_vrefresh(&crtc->mode), 1127 layout_valid ? &layout : NULL); 1128 1129 if (r_pipe->sspp) { 1130 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1131 drm_mode_vrefresh(&crtc->mode), 1132 layout_valid ? &layout : NULL); 1133 } 1134 1135 if (pstate->needs_qos_remap) 1136 pstate->needs_qos_remap = false; 1137 1138 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1139 &crtc->mode, pipe_cfg); 1140 1141 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1142 1143 if (r_pipe->sspp) { 1144 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1145 1146 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1147 } 1148 } 1149 1150 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1151 { 1152 struct drm_plane_state *state = plane->state; 1153 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1154 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1155 1156 trace_dpu_plane_disable(DRMID(plane), false, 1157 pstate->pipe.multirect_mode); 1158 1159 if (r_pipe->sspp) { 1160 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1161 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1162 1163 if (r_pipe->sspp->ops.setup_multirect) 1164 r_pipe->sspp->ops.setup_multirect(r_pipe); 1165 } 1166 1167 pstate->pending = true; 1168 } 1169 1170 static void dpu_plane_atomic_update(struct drm_plane *plane, 1171 struct drm_atomic_state *state) 1172 { 1173 struct dpu_plane *pdpu = to_dpu_plane(plane); 1174 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1175 plane); 1176 1177 pdpu->is_error = false; 1178 1179 DPU_DEBUG_PLANE(pdpu, "\n"); 1180 1181 if (!new_state->visible) { 1182 _dpu_plane_atomic_disable(plane); 1183 } else { 1184 dpu_plane_sspp_atomic_update(plane); 1185 } 1186 } 1187 1188 static void dpu_plane_destroy_state(struct drm_plane *plane, 1189 struct drm_plane_state *state) 1190 { 1191 __drm_atomic_helper_plane_destroy_state(state); 1192 kfree(to_dpu_plane_state(state)); 1193 } 1194 1195 static struct drm_plane_state * 1196 dpu_plane_duplicate_state(struct drm_plane *plane) 1197 { 1198 struct dpu_plane *pdpu; 1199 struct dpu_plane_state *pstate; 1200 struct dpu_plane_state *old_state; 1201 1202 if (!plane) { 1203 DPU_ERROR("invalid plane\n"); 1204 return NULL; 1205 } else if (!plane->state) { 1206 DPU_ERROR("invalid plane state\n"); 1207 return NULL; 1208 } 1209 1210 old_state = to_dpu_plane_state(plane->state); 1211 pdpu = to_dpu_plane(plane); 1212 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1213 if (!pstate) { 1214 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1215 return NULL; 1216 } 1217 1218 DPU_DEBUG_PLANE(pdpu, "\n"); 1219 1220 pstate->pending = false; 1221 1222 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1223 1224 return &pstate->base; 1225 } 1226 1227 static const char * const multirect_mode_name[] = { 1228 [DPU_SSPP_MULTIRECT_NONE] = "none", 1229 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1230 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1231 }; 1232 1233 static const char * const multirect_index_name[] = { 1234 [DPU_SSPP_RECT_SOLO] = "solo", 1235 [DPU_SSPP_RECT_0] = "rect_0", 1236 [DPU_SSPP_RECT_1] = "rect_1", 1237 }; 1238 1239 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1240 { 1241 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1242 return "unknown"; 1243 1244 return multirect_mode_name[mode]; 1245 } 1246 1247 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1248 { 1249 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1250 return "unknown"; 1251 1252 return multirect_index_name[index]; 1253 } 1254 1255 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1256 const struct drm_plane_state *state) 1257 { 1258 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1259 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1260 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1261 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1262 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1263 1264 drm_printf(p, "\tstage=%d\n", pstate->stage); 1265 1266 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1267 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); 1268 drm_printf(p, "\tmultirect_index[0]=%s\n", 1269 dpu_get_multirect_index(pipe->multirect_index)); 1270 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1271 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1272 1273 if (r_pipe->sspp) { 1274 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1275 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1276 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1277 drm_printf(p, "\tmultirect_index[1]=%s\n", 1278 dpu_get_multirect_index(r_pipe->multirect_index)); 1279 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1280 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1281 } 1282 } 1283 1284 static void dpu_plane_reset(struct drm_plane *plane) 1285 { 1286 struct dpu_plane *pdpu; 1287 struct dpu_plane_state *pstate; 1288 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1289 1290 if (!plane) { 1291 DPU_ERROR("invalid plane\n"); 1292 return; 1293 } 1294 1295 pdpu = to_dpu_plane(plane); 1296 DPU_DEBUG_PLANE(pdpu, "\n"); 1297 1298 /* remove previous state, if present */ 1299 if (plane->state) { 1300 dpu_plane_destroy_state(plane, plane->state); 1301 plane->state = NULL; 1302 } 1303 1304 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1305 if (!pstate) { 1306 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1307 return; 1308 } 1309 1310 /* 1311 * Set the SSPP here until we have proper virtualized DPU planes. 1312 * This is the place where the state is allocated, so fill it fully. 1313 */ 1314 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1315 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1316 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1317 1318 pstate->r_pipe.sspp = NULL; 1319 1320 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1321 } 1322 1323 #ifdef CONFIG_DEBUG_FS 1324 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1325 { 1326 struct dpu_plane *pdpu = to_dpu_plane(plane); 1327 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1328 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1329 1330 if (!pdpu->is_rt_pipe) 1331 return; 1332 1333 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1334 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1335 if (pstate->r_pipe.sspp) 1336 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1337 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1338 } 1339 #endif 1340 1341 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1342 uint32_t format, uint64_t modifier) 1343 { 1344 if (modifier == DRM_FORMAT_MOD_LINEAR) 1345 return true; 1346 1347 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1348 return dpu_find_format(format, qcom_compressed_supported_formats, 1349 ARRAY_SIZE(qcom_compressed_supported_formats)); 1350 1351 return false; 1352 } 1353 1354 static const struct drm_plane_funcs dpu_plane_funcs = { 1355 .update_plane = drm_atomic_helper_update_plane, 1356 .disable_plane = drm_atomic_helper_disable_plane, 1357 .reset = dpu_plane_reset, 1358 .atomic_duplicate_state = dpu_plane_duplicate_state, 1359 .atomic_destroy_state = dpu_plane_destroy_state, 1360 .atomic_print_state = dpu_plane_atomic_print_state, 1361 .format_mod_supported = dpu_plane_format_mod_supported, 1362 }; 1363 1364 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1365 .prepare_fb = dpu_plane_prepare_fb, 1366 .cleanup_fb = dpu_plane_cleanup_fb, 1367 .atomic_check = dpu_plane_atomic_check, 1368 .atomic_update = dpu_plane_atomic_update, 1369 }; 1370 1371 /* initialize plane */ 1372 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1373 uint32_t pipe, enum drm_plane_type type, 1374 unsigned long possible_crtcs) 1375 { 1376 struct drm_plane *plane = NULL; 1377 const uint32_t *format_list; 1378 struct dpu_plane *pdpu; 1379 struct msm_drm_private *priv = dev->dev_private; 1380 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1381 struct dpu_hw_sspp *pipe_hw; 1382 uint32_t num_formats; 1383 uint32_t supported_rotations; 1384 int ret; 1385 1386 /* initialize underlying h/w driver */ 1387 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1388 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1389 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1390 return ERR_PTR(-EINVAL); 1391 } 1392 1393 format_list = pipe_hw->cap->sblk->format_list; 1394 num_formats = pipe_hw->cap->sblk->num_formats; 1395 1396 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 1397 0xff, &dpu_plane_funcs, 1398 format_list, num_formats, 1399 supported_format_modifiers, type, NULL); 1400 if (IS_ERR(pdpu)) 1401 return ERR_CAST(pdpu); 1402 1403 /* cache local stuff for later */ 1404 plane = &pdpu->base; 1405 pdpu->pipe = pipe; 1406 1407 pdpu->catalog = kms->catalog; 1408 1409 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1410 if (ret) 1411 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1412 1413 drm_plane_create_alpha_property(plane); 1414 drm_plane_create_blend_mode_property(plane, 1415 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1416 BIT(DRM_MODE_BLEND_PREMULTI) | 1417 BIT(DRM_MODE_BLEND_COVERAGE)); 1418 1419 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1420 1421 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1422 supported_rotations |= DRM_MODE_ROTATE_MASK; 1423 1424 drm_plane_create_rotation_property(plane, 1425 DRM_MODE_ROTATE_0, supported_rotations); 1426 1427 drm_plane_enable_fb_damage_clips(plane); 1428 1429 /* success! finalize initialization */ 1430 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1431 1432 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1433 pipe, plane->base.id); 1434 return plane; 1435 } 1436