1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include <linux/soc/qcom/ubwc.h> 21 22 #include "msm_drv.h" 23 #include "dpu_kms.h" 24 #include "dpu_hw_sspp.h" 25 #include "dpu_hw_util.h" 26 #include "dpu_trace.h" 27 #include "dpu_crtc.h" 28 #include "dpu_vbif.h" 29 #include "dpu_plane.h" 30 31 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 33 34 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 35 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 36 37 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 38 #define PHASE_STEP_SHIFT 21 39 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 40 #define PHASE_RESIDUAL 15 41 42 #define SHARP_STRENGTH_DEFAULT 32 43 #define SHARP_EDGE_THR_DEFAULT 112 44 #define SHARP_SMOOTH_THR_DEFAULT 8 45 #define SHARP_NOISE_THR_DEFAULT 2 46 47 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 48 #define DPU_ZPOS_MAX 255 49 50 /* 51 * Default Preload Values 52 */ 53 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 54 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 55 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 56 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 57 58 #define DEFAULT_REFRESH_RATE 60 59 60 static const uint32_t qcom_compressed_supported_formats[] = { 61 DRM_FORMAT_ABGR8888, 62 DRM_FORMAT_ARGB8888, 63 DRM_FORMAT_XBGR8888, 64 DRM_FORMAT_XRGB8888, 65 DRM_FORMAT_ARGB2101010, 66 DRM_FORMAT_XRGB2101010, 67 DRM_FORMAT_BGR565, 68 69 DRM_FORMAT_NV12, 70 DRM_FORMAT_P010, 71 }; 72 73 /* 74 * struct dpu_plane - local dpu plane structure 75 * @vm: address space pointer 76 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 77 * @catalog: Points to dpu catalog structure 78 * @revalidate: force revalidation of all the plane properties 79 */ 80 struct dpu_plane { 81 struct drm_plane base; 82 83 enum dpu_sspp pipe; 84 85 uint32_t color_fill; 86 bool is_error; 87 bool is_rt_pipe; 88 const struct dpu_mdss_cfg *catalog; 89 }; 90 91 static const uint64_t supported_format_modifiers[] = { 92 DRM_FORMAT_MOD_QCOM_COMPRESSED, 93 DRM_FORMAT_MOD_LINEAR, 94 DRM_FORMAT_MOD_INVALID 95 }; 96 97 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 98 99 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 100 { 101 struct msm_drm_private *priv = plane->dev->dev_private; 102 103 return to_dpu_kms(priv->kms); 104 } 105 106 /** 107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 108 * @catalog: Points to dpu catalog structure 109 * @fmt: Pointer to source buffer format 110 * @mode: Pointer to drm display mode 111 * @pipe_cfg: Pointer to pipe configuration 112 * Result: Updates calculated bandwidth in the plane state. 113 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 114 * Prefill BW Equation: line src bytes * line_time 115 */ 116 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 117 const struct msm_format *fmt, 118 const struct drm_display_mode *mode, 119 struct dpu_sw_pipe_cfg *pipe_cfg) 120 { 121 int src_width, src_height, dst_height, fps; 122 u64 plane_pixel_rate, plane_bit_rate; 123 u64 plane_prefill_bw; 124 u64 plane_bw; 125 u32 hw_latency_lines; 126 u64 scale_factor; 127 int vbp, vpw, vfp; 128 129 src_width = drm_rect_width(&pipe_cfg->src_rect); 130 src_height = drm_rect_height(&pipe_cfg->src_rect); 131 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 132 fps = drm_mode_vrefresh(mode); 133 vbp = mode->vtotal - mode->vsync_end; 134 vpw = mode->vsync_end - mode->vsync_start; 135 vfp = mode->vsync_start - mode->vdisplay; 136 hw_latency_lines = catalog->perf->min_prefill_lines; 137 scale_factor = src_height > dst_height ? 138 mult_frac(src_height, 1, dst_height) : 1; 139 140 plane_pixel_rate = src_width * mode->vtotal * fps; 141 plane_bit_rate = plane_pixel_rate * fmt->bpp; 142 143 plane_bw = plane_bit_rate * scale_factor; 144 145 plane_prefill_bw = plane_bw * hw_latency_lines; 146 147 if ((vbp+vpw) > hw_latency_lines) 148 do_div(plane_prefill_bw, (vbp+vpw)); 149 else if ((vbp+vpw+vfp) < hw_latency_lines) 150 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 151 else 152 do_div(plane_prefill_bw, hw_latency_lines); 153 154 155 return max(plane_bw, plane_prefill_bw); 156 } 157 158 /** 159 * _dpu_plane_calc_clk - calculate clock required for a plane 160 * @mode: Pointer to drm display mode 161 * @pipe_cfg: Pointer to pipe configuration 162 * Result: Updates calculated clock in the plane state. 163 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 164 */ 165 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 166 struct dpu_sw_pipe_cfg *pipe_cfg) 167 { 168 int dst_width, src_height, dst_height, fps; 169 u64 plane_clk; 170 171 src_height = drm_rect_height(&pipe_cfg->src_rect); 172 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 173 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 174 fps = drm_mode_vrefresh(mode); 175 176 plane_clk = 177 dst_width * mode->vtotal * fps; 178 179 if (src_height > dst_height) { 180 plane_clk *= src_height; 181 do_div(plane_clk, dst_height); 182 } 183 184 return plane_clk; 185 } 186 187 /** 188 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 189 * @plane: Pointer to drm plane 190 * @pipe: Pointer to software pipe 191 * @lut_usage: LUT usecase 192 * @fmt: Pointer to source buffer format 193 * @src_width: width of source buffer 194 * Return: fill level corresponding to the source buffer/format or 0 if error 195 */ 196 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 197 struct dpu_sw_pipe *pipe, 198 enum dpu_qos_lut_usage lut_usage, 199 const struct msm_format *fmt, u32 src_width) 200 { 201 struct dpu_plane *pdpu; 202 u32 fixed_buff_size; 203 u32 total_fl; 204 205 if (!fmt || !pipe || !src_width || !fmt->bpp) { 206 DPU_ERROR("invalid arguments\n"); 207 return 0; 208 } 209 210 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 211 return 0; 212 213 pdpu = to_dpu_plane(plane); 214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 215 216 /* FIXME: in multirect case account for the src_width of all the planes */ 217 218 if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { 219 if (fmt->chroma_sample == CHROMA_420) { 220 /* NV12 */ 221 total_fl = (fixed_buff_size / 2) / 222 ((src_width + 32) * fmt->bpp); 223 } else { 224 /* non NV12 */ 225 total_fl = (fixed_buff_size / 2) * 2 / 226 ((src_width + 32) * fmt->bpp); 227 } 228 } else { 229 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 230 total_fl = (fixed_buff_size / 2) * 2 / 231 ((src_width + 32) * fmt->bpp); 232 } else { 233 total_fl = (fixed_buff_size) * 2 / 234 ((src_width + 32) * fmt->bpp); 235 } 236 } 237 238 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n", 239 pipe->sspp->idx - SSPP_VIG0, 240 &fmt->pixel_format, 241 src_width, total_fl); 242 243 return total_fl; 244 } 245 246 /** 247 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 248 * @plane: Pointer to drm plane 249 * @pipe: Pointer to software pipe 250 * @fmt: Pointer to source buffer format 251 * @pipe_cfg: Pointer to pipe configuration 252 */ 253 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 254 struct dpu_sw_pipe *pipe, 255 const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 256 { 257 struct dpu_plane *pdpu = to_dpu_plane(plane); 258 struct dpu_hw_qos_cfg cfg; 259 u32 total_fl, lut_usage; 260 261 if (!pdpu->is_rt_pipe) { 262 lut_usage = DPU_QOS_LUT_USAGE_NRT; 263 } else { 264 if (fmt && MSM_FORMAT_IS_LINEAR(fmt)) 265 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 266 else 267 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 268 } 269 270 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 271 drm_rect_width(&pipe_cfg->src_rect)); 272 273 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 274 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 276 277 if (pipe->sspp->idx != SSPP_CURSOR0 && 278 pipe->sspp->idx != SSPP_CURSOR1 && 279 pdpu->is_rt_pipe) 280 cfg.danger_safe_en = true; 281 282 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 283 pdpu->pipe - SSPP_VIG0, 284 cfg.danger_safe_en, 285 pdpu->is_rt_pipe); 286 287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 288 (fmt) ? fmt->pixel_format : 0, 289 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 290 291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n", 292 pdpu->pipe - SSPP_VIG0, 293 fmt ? &fmt->pixel_format : NULL, 294 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 295 296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 297 (fmt) ? fmt->pixel_format : 0, 298 (fmt) ? fmt->fetch_mode : 0, 299 cfg.danger_lut, 300 cfg.safe_lut); 301 302 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", 303 pdpu->pipe - SSPP_VIG0, 304 fmt ? &fmt->pixel_format : NULL, 305 fmt ? fmt->fetch_mode : -1, 306 cfg.danger_lut, 307 cfg.safe_lut); 308 309 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 310 } 311 312 /** 313 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 314 * @plane: Pointer to drm plane 315 * @pipe: Pointer to software pipe 316 * @enable: true to enable QoS control 317 */ 318 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 319 struct dpu_sw_pipe *pipe, 320 bool enable) 321 { 322 struct dpu_plane *pdpu = to_dpu_plane(plane); 323 324 if (!pdpu->is_rt_pipe) 325 enable = false; 326 327 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 328 pdpu->pipe - SSPP_VIG0, 329 enable, 330 pdpu->is_rt_pipe); 331 332 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 333 enable); 334 } 335 336 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp, 337 struct dpu_hw_mdp *mdp, 338 bool enable, bool *forced_on) 339 { 340 if (sspp->ops.setup_clk_force_ctrl) { 341 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable); 342 return true; 343 } 344 345 if (mdp->ops.setup_clk_force_ctrl) { 346 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); 347 return true; 348 } 349 350 return false; 351 } 352 353 /** 354 * _dpu_plane_set_ot_limit - set OT limit for the given plane 355 * @plane: Pointer to drm plane 356 * @pipe: Pointer to software pipe 357 * @pipe_cfg: Pointer to pipe configuration 358 * @frame_rate: CRTC's frame rate 359 */ 360 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 361 struct dpu_sw_pipe *pipe, 362 struct dpu_sw_pipe_cfg *pipe_cfg, 363 int frame_rate) 364 { 365 struct dpu_plane *pdpu = to_dpu_plane(plane); 366 struct dpu_vbif_set_ot_params ot_params; 367 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 368 bool forced_on = false; 369 370 memset(&ot_params, 0, sizeof(ot_params)); 371 ot_params.xin_id = pipe->sspp->cap->xin_id; 372 ot_params.num = pipe->sspp->idx - SSPP_NONE; 373 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 374 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 375 ot_params.is_wfd = !pdpu->is_rt_pipe; 376 ot_params.frame_rate = frame_rate; 377 ot_params.vbif_idx = VBIF_RT; 378 ot_params.rd = true; 379 380 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 381 true, &forced_on)) 382 return; 383 384 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 385 386 if (forced_on) 387 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 388 false, &forced_on); 389 } 390 391 /** 392 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 393 * @plane: Pointer to drm plane 394 * @pipe: Pointer to software pipe 395 */ 396 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 397 struct dpu_sw_pipe *pipe) 398 { 399 struct dpu_plane *pdpu = to_dpu_plane(plane); 400 struct dpu_vbif_set_qos_params qos_params; 401 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 402 bool forced_on = false; 403 404 memset(&qos_params, 0, sizeof(qos_params)); 405 qos_params.vbif_idx = VBIF_RT; 406 qos_params.xin_id = pipe->sspp->cap->xin_id; 407 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 408 qos_params.is_rt = pdpu->is_rt_pipe; 409 410 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n", 411 qos_params.num, 412 qos_params.vbif_idx, 413 qos_params.xin_id, qos_params.is_rt); 414 415 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 416 true, &forced_on)) 417 return; 418 419 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 420 421 if (forced_on) 422 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, 423 false, &forced_on); 424 } 425 426 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 427 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 428 struct dpu_hw_scaler3_cfg *scale_cfg, 429 const struct msm_format *fmt, 430 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 431 unsigned int rotation) 432 { 433 uint32_t i; 434 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 435 436 /* 437 * For inline rotation cases, scaler config is post-rotation, 438 * so swap the dimensions here. However, pixel extension will 439 * need pre-rotation settings. 440 */ 441 if (inline_rotation) 442 swap(src_w, src_h); 443 444 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 445 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 446 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 447 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 448 449 450 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 451 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 452 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 453 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 454 455 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 456 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 458 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 459 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 461 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 462 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 463 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 464 465 for (i = 0; i < DPU_MAX_PLANES; i++) { 466 scale_cfg->src_width[i] = src_w; 467 scale_cfg->src_height[i] = src_h; 468 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 469 scale_cfg->src_width[i] /= chroma_subsmpl_h; 470 scale_cfg->src_height[i] /= chroma_subsmpl_v; 471 } 472 473 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) { 474 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 475 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 476 } else { 477 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 478 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 479 } 480 } 481 if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 482 && (src_w == dst_w)) 483 return; 484 485 scale_cfg->dst_width = dst_w; 486 scale_cfg->dst_height = dst_h; 487 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 488 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 489 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 490 scale_cfg->lut_flag = 0; 491 scale_cfg->blend_cfg = 1; 492 scale_cfg->enable = 1; 493 } 494 495 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 496 struct dpu_hw_pixel_ext *pixel_ext, 497 uint32_t src_w, uint32_t src_h, 498 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 499 { 500 int i; 501 502 for (i = 0; i < DPU_MAX_PLANES; i++) { 503 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 504 src_w /= chroma_subsmpl_h; 505 src_h /= chroma_subsmpl_v; 506 } 507 508 pixel_ext->num_ext_pxls_top[i] = src_h; 509 pixel_ext->num_ext_pxls_left[i] = src_w; 510 } 511 } 512 513 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 514 const struct msm_format *fmt) 515 { 516 const struct dpu_csc_cfg *csc_ptr; 517 518 if (!MSM_FORMAT_IS_YUV(fmt)) 519 return NULL; 520 521 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 522 csc_ptr = &dpu_csc10_YUV2RGB_601L; 523 else 524 csc_ptr = &dpu_csc_YUV2RGB_601L; 525 526 return csc_ptr; 527 } 528 529 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 530 const struct msm_format *fmt, bool color_fill, 531 struct dpu_sw_pipe_cfg *pipe_cfg) 532 { 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 534 const struct drm_format_info *info = drm_format_info(fmt->pixel_format); 535 struct dpu_hw_scaler3_cfg scaler3_cfg; 536 struct dpu_hw_pixel_ext pixel_ext; 537 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 538 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 539 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 540 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 541 542 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 543 memset(&pixel_ext, 0, sizeof(pixel_ext)); 544 545 /* don't chroma subsample if decimating */ 546 /* update scaler. calculate default config for QSEED3 */ 547 _dpu_plane_setup_scaler3(pipe_hw, 548 src_width, 549 src_height, 550 dst_width, 551 dst_height, 552 &scaler3_cfg, fmt, 553 info->hsub, info->vsub, 554 pipe_cfg->rotation); 555 556 /* configure pixel extension based on scalar config */ 557 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 558 src_width, src_height, info->hsub, info->vsub); 559 560 if (pipe_hw->ops.setup_pe) 561 pipe_hw->ops.setup_pe(pipe_hw, 562 &pixel_ext); 563 564 /** 565 * when programmed in multirect mode, scalar block will be 566 * bypassed. Still we need to update alpha and bitwidth 567 * ONLY for RECT0 568 */ 569 if (pipe_hw->ops.setup_scaler && 570 pipe->multirect_index != DPU_SSPP_RECT_1) 571 pipe_hw->ops.setup_scaler(pipe_hw, 572 &scaler3_cfg, 573 fmt); 574 } 575 576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 577 struct dpu_sw_pipe *pipe, 578 struct drm_rect *dst_rect, 579 u32 fill_color, 580 const struct msm_format *fmt) 581 { 582 struct dpu_sw_pipe_cfg pipe_cfg; 583 584 /* update sspp */ 585 if (!pipe->sspp->ops.setup_solidfill) 586 return; 587 588 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 589 590 /* override scaler/decimation if solid fill */ 591 pipe_cfg.dst_rect = *dst_rect; 592 593 pipe_cfg.src_rect.x1 = 0; 594 pipe_cfg.src_rect.y1 = 0; 595 pipe_cfg.src_rect.x2 = 596 drm_rect_width(&pipe_cfg.dst_rect); 597 pipe_cfg.src_rect.y2 = 598 drm_rect_height(&pipe_cfg.dst_rect); 599 600 if (pipe->sspp->ops.setup_format) 601 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 602 603 if (pipe->sspp->ops.setup_rects) 604 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); 607 } 608 609 /** 610 * _dpu_plane_color_fill - enables color fill on plane 611 * @pdpu: Pointer to DPU plane object 612 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 613 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 614 */ 615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 616 uint32_t color, uint32_t alpha) 617 { 618 const struct msm_format *fmt; 619 const struct drm_plane *plane = &pdpu->base; 620 struct msm_drm_private *priv = plane->dev->dev_private; 621 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 622 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 623 624 DPU_DEBUG_PLANE(pdpu, "\n"); 625 626 /* 627 * select fill format to match user property expectation, 628 * h/w only supports RGB variants 629 */ 630 fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0); 631 /* should not happen ever */ 632 if (!fmt) 633 return; 634 635 /* update sspp */ 636 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 637 fill_color, fmt); 638 639 if (pstate->r_pipe.sspp) 640 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 641 fill_color, fmt); 642 } 643 644 static int dpu_plane_prepare_fb(struct drm_plane *plane, 645 struct drm_plane_state *new_state) 646 { 647 struct drm_framebuffer *fb = new_state->fb; 648 struct dpu_plane *pdpu = to_dpu_plane(plane); 649 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 650 int ret; 651 652 if (!new_state->fb) 653 return 0; 654 655 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 656 657 /* 658 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 659 * we can use msm_atomic_prepare_fb() instead of doing the 660 * implicit fence and fb prepare by hand here. 661 */ 662 drm_gem_plane_helper_prepare_fb(plane, new_state); 663 664 ret = msm_framebuffer_prepare(new_state->fb, pstate->needs_dirtyfb); 665 if (ret) { 666 DPU_ERROR("failed to prepare framebuffer\n"); 667 return ret; 668 } 669 670 return 0; 671 } 672 673 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 674 struct drm_plane_state *old_state) 675 { 676 struct dpu_plane *pdpu = to_dpu_plane(plane); 677 struct dpu_plane_state *old_pstate; 678 679 if (!old_state || !old_state->fb) 680 return; 681 682 old_pstate = to_dpu_plane_state(old_state); 683 684 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 685 686 msm_framebuffer_cleanup(old_state->fb, old_pstate->needs_dirtyfb); 687 } 688 689 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 690 struct dpu_sw_pipe *pipe, 691 struct drm_rect src, 692 const struct msm_format *fmt) 693 { 694 const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; 695 size_t num_formats; 696 const u32 *supported_formats; 697 698 if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) 699 return -EINVAL; 700 701 if (!sblk->rotation_cfg) { 702 DPU_ERROR("invalid rotation cfg\n"); 703 return -EINVAL; 704 } 705 706 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 707 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 708 src.y2, sblk->rotation_cfg->rot_maxheight); 709 return -EINVAL; 710 } 711 712 supported_formats = sblk->rotation_cfg->rot_format_list; 713 num_formats = sblk->rotation_cfg->rot_num_formats; 714 715 if (!MSM_FORMAT_IS_UBWC(fmt) || 716 !dpu_find_format(fmt->pixel_format, supported_formats, num_formats)) 717 return -EINVAL; 718 719 return 0; 720 } 721 722 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 723 struct dpu_sw_pipe *pipe, 724 struct dpu_sw_pipe_cfg *pipe_cfg, 725 const struct drm_display_mode *mode, 726 struct drm_plane_state *new_plane_state) 727 { 728 uint32_t min_src_size; 729 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 730 int ret; 731 const struct msm_format *fmt; 732 uint32_t supported_rotations; 733 const struct dpu_sspp_cfg *pipe_hw_caps; 734 const struct dpu_sspp_sub_blks *sblk; 735 736 pipe_hw_caps = pipe->sspp->cap; 737 sblk = pipe->sspp->cap->sblk; 738 739 /* 740 * We already have verified scaling against platform limitations. 741 * Now check if the SSPP supports scaling at all. 742 */ 743 if (!sblk->scaler_blk.len && 744 ((drm_rect_width(&new_plane_state->src) >> 16 != 745 drm_rect_width(&new_plane_state->dst)) || 746 (drm_rect_height(&new_plane_state->src) >> 16 != 747 drm_rect_height(&new_plane_state->dst)))) 748 return -ERANGE; 749 750 fmt = msm_framebuffer_format(new_plane_state->fb); 751 752 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 753 754 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 755 supported_rotations |= DRM_MODE_ROTATE_90; 756 757 pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, 758 supported_rotations); 759 760 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; 761 762 if (MSM_FORMAT_IS_YUV(fmt) && 763 !pipe->sspp->cap->sblk->csc_blk.len) { 764 DPU_DEBUG_PLANE(pdpu, 765 "plane doesn't have csc for yuv\n"); 766 return -EINVAL; 767 } 768 769 /* check src bounds */ 770 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 771 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 772 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 773 DRM_RECT_ARG(&pipe_cfg->src_rect)); 774 return -E2BIG; 775 } 776 777 /* valid yuv image */ 778 if (MSM_FORMAT_IS_YUV(fmt) && 779 (pipe_cfg->src_rect.x1 & 0x1 || 780 pipe_cfg->src_rect.y1 & 0x1 || 781 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 782 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 783 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 784 DRM_RECT_ARG(&pipe_cfg->src_rect)); 785 return -EINVAL; 786 } 787 788 /* min dst support */ 789 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 790 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 791 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 792 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 793 return -EINVAL; 794 } 795 796 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { 797 ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); 798 if (ret) 799 return ret; 800 } 801 802 /* max clk check */ 803 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 804 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 805 return -E2BIG; 806 } 807 808 return 0; 809 } 810 811 #define MAX_UPSCALE_RATIO 20 812 #define MAX_DOWNSCALE_RATIO 4 813 814 static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, 815 struct drm_plane_state *new_plane_state, 816 const struct drm_crtc_state *crtc_state) 817 { 818 int i, ret = 0, min_scale, max_scale; 819 struct dpu_plane *pdpu = to_dpu_plane(plane); 820 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 821 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 822 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 823 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 824 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 825 struct drm_rect fb_rect = { 0 }; 826 uint32_t max_linewidth; 827 828 min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); 829 max_scale = MAX_DOWNSCALE_RATIO << 16; 830 831 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 832 min_scale, 833 max_scale, 834 true, true); 835 if (ret) { 836 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 837 return ret; 838 } 839 if (!new_plane_state->visible) 840 return 0; 841 842 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 843 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 844 DPU_ERROR("> %d plane stages assigned\n", 845 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 846 return -EINVAL; 847 } 848 849 /* state->src is 16.16, src_rect is not */ 850 drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); 851 852 pipe_cfg->dst_rect = new_plane_state->dst; 853 854 fb_rect.x2 = new_plane_state->fb->width; 855 fb_rect.y2 = new_plane_state->fb->height; 856 857 /* Ensure fb size is supported */ 858 if (drm_rect_width(&fb_rect) > DPU_MAX_IMG_WIDTH || 859 drm_rect_height(&fb_rect) > DPU_MAX_IMG_HEIGHT) { 860 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 861 DRM_RECT_ARG(&fb_rect)); 862 return -E2BIG; 863 } 864 865 ret = dpu_format_populate_plane_sizes(new_plane_state->fb, &pstate->layout); 866 if (ret) { 867 DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); 868 return ret; 869 } 870 871 for (i = 0; i < pstate->layout.num_planes; i++) 872 if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) 873 return -E2BIG; 874 875 max_linewidth = pdpu->catalog->caps->max_linewidth; 876 877 drm_rect_rotate(&pipe_cfg->src_rect, 878 new_plane_state->fb->width, new_plane_state->fb->height, 879 new_plane_state->rotation); 880 881 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 882 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 883 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 884 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 885 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 886 return -E2BIG; 887 } 888 889 *r_pipe_cfg = *pipe_cfg; 890 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 891 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 892 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 893 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 894 } else { 895 memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); 896 } 897 898 drm_rect_rotate_inv(&pipe_cfg->src_rect, 899 new_plane_state->fb->width, new_plane_state->fb->height, 900 new_plane_state->rotation); 901 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) 902 drm_rect_rotate_inv(&r_pipe_cfg->src_rect, 903 new_plane_state->fb->width, new_plane_state->fb->height, 904 new_plane_state->rotation); 905 906 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 907 908 return 0; 909 } 910 911 static int dpu_plane_is_multirect_capable(struct dpu_hw_sspp *sspp, 912 struct dpu_sw_pipe_cfg *pipe_cfg, 913 const struct msm_format *fmt) 914 { 915 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 916 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect)) 917 return false; 918 919 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) 920 return false; 921 922 if (MSM_FORMAT_IS_YUV(fmt)) 923 return false; 924 925 if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) && 926 !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features)) 927 return false; 928 929 return true; 930 } 931 932 static int dpu_plane_is_parallel_capable(struct dpu_sw_pipe_cfg *pipe_cfg, 933 const struct msm_format *fmt, 934 uint32_t max_linewidth) 935 { 936 if (MSM_FORMAT_IS_UBWC(fmt) && 937 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) 938 return false; 939 940 return true; 941 } 942 943 static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *sspp, 944 struct dpu_sw_pipe_cfg *pipe_cfg, 945 const struct msm_format *fmt, 946 uint32_t max_linewidth) 947 { 948 return dpu_plane_is_multirect_capable(sspp, pipe_cfg, fmt) && 949 dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); 950 } 951 952 953 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, 954 struct drm_atomic_state *state, 955 const struct drm_crtc_state *crtc_state) 956 { 957 struct drm_plane_state *new_plane_state = 958 drm_atomic_get_new_plane_state(state, plane); 959 struct dpu_plane *pdpu = to_dpu_plane(plane); 960 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 961 struct dpu_sw_pipe *pipe = &pstate->pipe; 962 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 963 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 964 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 965 int ret = 0; 966 967 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, 968 &crtc_state->adjusted_mode, 969 new_plane_state); 970 if (ret) 971 return ret; 972 973 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { 974 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, 975 &crtc_state->adjusted_mode, 976 new_plane_state); 977 if (ret) 978 return ret; 979 } 980 981 return 0; 982 } 983 984 static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, 985 struct dpu_sw_pipe *r_pipe, struct dpu_sw_pipe_cfg *r_pipe_cfg, 986 struct dpu_hw_sspp *sspp, const struct msm_format *fmt, 987 uint32_t max_linewidth) 988 { 989 r_pipe->sspp = NULL; 990 991 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 992 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 993 994 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 995 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 996 997 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { 998 if (!dpu_plane_is_multirect_parallel_capable(pipe->sspp, pipe_cfg, fmt, max_linewidth) || 999 !dpu_plane_is_multirect_parallel_capable(pipe->sspp, r_pipe_cfg, fmt, max_linewidth)) 1000 return false; 1001 1002 r_pipe->sspp = pipe->sspp; 1003 1004 pipe->multirect_index = DPU_SSPP_RECT_0; 1005 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1006 1007 r_pipe->multirect_index = DPU_SSPP_RECT_1; 1008 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1009 } 1010 1011 return true; 1012 } 1013 1014 static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, 1015 struct dpu_plane_state *prev_adjacent_pstate, 1016 const struct msm_format *fmt, 1017 uint32_t max_linewidth) 1018 { 1019 struct dpu_sw_pipe *pipe = &pstate->pipe; 1020 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1021 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1022 struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe; 1023 struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg; 1024 const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb); 1025 u16 max_tile_height = 1; 1026 1027 if (prev_adjacent_pstate->r_pipe.sspp != NULL || 1028 prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE) 1029 return false; 1030 1031 if (!dpu_plane_is_multirect_capable(pipe->sspp, pipe_cfg, fmt) || 1032 !dpu_plane_is_multirect_capable(prev_pipe->sspp, prev_pipe_cfg, prev_fmt)) 1033 return false; 1034 1035 if (MSM_FORMAT_IS_UBWC(fmt)) 1036 max_tile_height = max(max_tile_height, fmt->tile_height); 1037 1038 if (MSM_FORMAT_IS_UBWC(prev_fmt)) 1039 max_tile_height = max(max_tile_height, prev_fmt->tile_height); 1040 1041 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1042 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1043 1044 r_pipe->sspp = NULL; 1045 1046 if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && 1047 dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) && 1048 (pipe_cfg->dst_rect.x1 >= prev_pipe_cfg->dst_rect.x2 || 1049 prev_pipe_cfg->dst_rect.x1 >= pipe_cfg->dst_rect.x2)) { 1050 pipe->sspp = prev_pipe->sspp; 1051 1052 pipe->multirect_index = DPU_SSPP_RECT_1; 1053 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1054 1055 prev_pipe->multirect_index = DPU_SSPP_RECT_0; 1056 prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 1057 1058 return true; 1059 } 1060 1061 if (pipe_cfg->dst_rect.y1 >= prev_pipe_cfg->dst_rect.y2 + 2 * max_tile_height || 1062 prev_pipe_cfg->dst_rect.y1 >= pipe_cfg->dst_rect.y2 + 2 * max_tile_height) { 1063 pipe->sspp = prev_pipe->sspp; 1064 1065 pipe->multirect_index = DPU_SSPP_RECT_1; 1066 pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 1067 1068 prev_pipe->multirect_index = DPU_SSPP_RECT_0; 1069 prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 1070 1071 return true; 1072 } 1073 1074 return false; 1075 } 1076 1077 static int dpu_plane_atomic_check(struct drm_plane *plane, 1078 struct drm_atomic_state *state) 1079 { 1080 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1081 plane); 1082 int ret = 0; 1083 struct dpu_plane *pdpu = to_dpu_plane(plane); 1084 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 1085 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1086 struct dpu_sw_pipe *pipe = &pstate->pipe; 1087 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1088 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1089 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1090 const struct drm_crtc_state *crtc_state = NULL; 1091 uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; 1092 1093 if (new_plane_state->crtc) 1094 crtc_state = drm_atomic_get_new_crtc_state(state, 1095 new_plane_state->crtc); 1096 1097 pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1098 1099 if (!pipe->sspp) 1100 return -EINVAL; 1101 1102 ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); 1103 if (ret) 1104 return ret; 1105 1106 if (!new_plane_state->visible) 1107 return 0; 1108 1109 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1110 pipe->sspp, 1111 msm_framebuffer_format(new_plane_state->fb), 1112 max_linewidth)) { 1113 DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT 1114 " max_line:%u, can't use split source\n", 1115 DRM_RECT_ARG(&pipe_cfg->src_rect), 1116 DRM_RECT_ARG(&r_pipe_cfg->src_rect), 1117 max_linewidth); 1118 return -E2BIG; 1119 } 1120 1121 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1122 } 1123 1124 static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, 1125 struct drm_atomic_state *state) 1126 { 1127 struct drm_plane_state *plane_state = 1128 drm_atomic_get_plane_state(state, plane); 1129 struct drm_plane_state *old_plane_state = 1130 drm_atomic_get_old_plane_state(state, plane); 1131 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1132 struct drm_crtc_state *crtc_state; 1133 int ret; 1134 1135 if (IS_ERR(plane_state)) 1136 return PTR_ERR(plane_state); 1137 1138 if (plane_state->crtc) 1139 crtc_state = drm_atomic_get_new_crtc_state(state, 1140 plane_state->crtc); 1141 1142 ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state); 1143 if (ret) 1144 return ret; 1145 1146 if (!plane_state->visible) { 1147 /* 1148 * resources are freed by dpu_crtc_assign_plane_resources(), 1149 * but clean them here. 1150 */ 1151 pstate->pipe.sspp = NULL; 1152 pstate->r_pipe.sspp = NULL; 1153 1154 return 0; 1155 } 1156 1157 /* 1158 * Force resource reallocation if the format of FB or src/dst have 1159 * changed. We might need to allocate different SSPP or SSPPs for this 1160 * plane than the one used previously. 1161 */ 1162 if (!old_plane_state || !old_plane_state->fb || 1163 old_plane_state->src_w != plane_state->src_w || 1164 old_plane_state->src_h != plane_state->src_h || 1165 old_plane_state->src_w != plane_state->src_w || 1166 old_plane_state->crtc_h != plane_state->crtc_h || 1167 msm_framebuffer_format(old_plane_state->fb) != 1168 msm_framebuffer_format(plane_state->fb)) 1169 crtc_state->planes_changed = true; 1170 1171 return 0; 1172 } 1173 1174 static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, 1175 struct dpu_global_state *global_state, 1176 struct drm_atomic_state *state, 1177 struct drm_plane_state *plane_state, 1178 struct drm_plane_state *prev_adjacent_plane_state) 1179 { 1180 const struct drm_crtc_state *crtc_state = NULL; 1181 struct drm_plane *plane = plane_state->plane; 1182 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1183 struct dpu_rm_sspp_requirements reqs; 1184 struct dpu_plane_state *pstate, *prev_adjacent_pstate; 1185 struct dpu_sw_pipe *pipe; 1186 struct dpu_sw_pipe *r_pipe; 1187 struct dpu_sw_pipe_cfg *pipe_cfg; 1188 struct dpu_sw_pipe_cfg *r_pipe_cfg; 1189 const struct msm_format *fmt; 1190 1191 if (plane_state->crtc) 1192 crtc_state = drm_atomic_get_new_crtc_state(state, 1193 plane_state->crtc); 1194 1195 pstate = to_dpu_plane_state(plane_state); 1196 prev_adjacent_pstate = prev_adjacent_plane_state ? 1197 to_dpu_plane_state(prev_adjacent_plane_state) : NULL; 1198 pipe = &pstate->pipe; 1199 r_pipe = &pstate->r_pipe; 1200 pipe_cfg = &pstate->pipe_cfg; 1201 r_pipe_cfg = &pstate->r_pipe_cfg; 1202 1203 pipe->sspp = NULL; 1204 r_pipe->sspp = NULL; 1205 1206 if (!plane_state->fb) 1207 return -EINVAL; 1208 1209 fmt = msm_framebuffer_format(plane_state->fb); 1210 reqs.yuv = MSM_FORMAT_IS_YUV(fmt); 1211 reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) || 1212 (plane_state->src_h >> 16 != plane_state->crtc_h); 1213 1214 reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); 1215 1216 if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { 1217 if (!prev_adjacent_pstate || 1218 !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, 1219 dpu_kms->catalog->caps->max_linewidth)) { 1220 pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1221 if (!pipe->sspp) 1222 return -ENODEV; 1223 1224 r_pipe->sspp = NULL; 1225 1226 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1227 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1228 1229 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1230 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1231 } 1232 } else { 1233 pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1234 if (!pipe->sspp) 1235 return -ENODEV; 1236 1237 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, 1238 pipe->sspp, 1239 msm_framebuffer_format(plane_state->fb), 1240 dpu_kms->catalog->caps->max_linewidth)) { 1241 /* multirect is not possible, use two SSPP blocks */ 1242 r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); 1243 if (!r_pipe->sspp) 1244 return -ENODEV; 1245 1246 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1247 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1248 1249 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1250 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1251 } 1252 } 1253 1254 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1255 } 1256 1257 int dpu_assign_plane_resources(struct dpu_global_state *global_state, 1258 struct drm_atomic_state *state, 1259 struct drm_crtc *crtc, 1260 struct drm_plane_state **states, 1261 unsigned int num_planes) 1262 { 1263 unsigned int i; 1264 struct drm_plane_state *prev_adjacent_plane_state = NULL; 1265 1266 for (i = 0; i < num_planes; i++) { 1267 struct drm_plane_state *plane_state = states[i]; 1268 1269 if (!plane_state || 1270 !plane_state->visible) 1271 continue; 1272 1273 int ret = dpu_plane_virtual_assign_resources(crtc, global_state, 1274 state, plane_state, 1275 prev_adjacent_plane_state); 1276 if (ret) 1277 break; 1278 1279 prev_adjacent_plane_state = plane_state; 1280 } 1281 1282 return 0; 1283 } 1284 1285 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 1286 { 1287 const struct msm_format *format = 1288 msm_framebuffer_format(pdpu->base.state->fb); 1289 const struct dpu_csc_cfg *csc_ptr; 1290 1291 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 1292 return; 1293 1294 csc_ptr = _dpu_plane_get_csc(pipe, format); 1295 if (!csc_ptr) 1296 return; 1297 1298 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 1299 csc_ptr->csc_mv[0], 1300 csc_ptr->csc_mv[1], 1301 csc_ptr->csc_mv[2]); 1302 1303 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 1304 1305 } 1306 1307 /** 1308 * dpu_plane_flush - final plane operations before commit flush 1309 * @plane: Pointer to drm plane structure 1310 */ 1311 void dpu_plane_flush(struct drm_plane *plane) 1312 { 1313 struct dpu_plane *pdpu; 1314 struct dpu_plane_state *pstate; 1315 1316 if (!plane || !plane->state) { 1317 DPU_ERROR("invalid plane\n"); 1318 return; 1319 } 1320 1321 pdpu = to_dpu_plane(plane); 1322 pstate = to_dpu_plane_state(plane->state); 1323 1324 /* 1325 * These updates have to be done immediately before the plane flush 1326 * timing, and may not be moved to the atomic_update/mode_set functions. 1327 */ 1328 if (pdpu->is_error) 1329 /* force white frame with 100% alpha pipe output on error */ 1330 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1331 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1332 /* force 100% alpha */ 1333 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1334 else { 1335 dpu_plane_flush_csc(pdpu, &pstate->pipe); 1336 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 1337 } 1338 1339 /* flag h/w flush complete */ 1340 if (plane->state) 1341 pstate->pending = false; 1342 } 1343 1344 /** 1345 * dpu_plane_set_error: enable/disable error condition 1346 * @plane: pointer to drm_plane structure 1347 * @error: error value to set 1348 */ 1349 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1350 { 1351 struct dpu_plane *pdpu; 1352 1353 if (!plane) 1354 return; 1355 1356 pdpu = to_dpu_plane(plane); 1357 pdpu->is_error = error; 1358 } 1359 1360 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1361 struct dpu_sw_pipe *pipe, 1362 struct dpu_sw_pipe_cfg *pipe_cfg, 1363 const struct msm_format *fmt, 1364 int frame_rate, 1365 struct dpu_hw_fmt_layout *layout) 1366 { 1367 uint32_t src_flags; 1368 struct dpu_plane *pdpu = to_dpu_plane(plane); 1369 struct drm_plane_state *state = plane->state; 1370 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1371 1372 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1373 trace_dpu_plane_set_scanout(pipe, layout); 1374 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1375 } 1376 1377 /* override for color fill */ 1378 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1379 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1380 1381 /* skip remaining processing on color fill */ 1382 return; 1383 } 1384 1385 if (pipe->sspp->ops.setup_rects) { 1386 pipe->sspp->ops.setup_rects(pipe, 1387 pipe_cfg); 1388 } 1389 1390 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); 1391 1392 if (pipe->sspp->ops.setup_multirect) 1393 pipe->sspp->ops.setup_multirect( 1394 pipe); 1395 1396 if (pipe->sspp->ops.setup_format) { 1397 unsigned int rotation = pipe_cfg->rotation; 1398 1399 src_flags = 0x0; 1400 1401 if (rotation & DRM_MODE_REFLECT_X) 1402 src_flags |= DPU_SSPP_FLIP_LR; 1403 1404 if (rotation & DRM_MODE_REFLECT_Y) 1405 src_flags |= DPU_SSPP_FLIP_UD; 1406 1407 if (rotation & DRM_MODE_ROTATE_90) 1408 src_flags |= DPU_SSPP_ROT_90; 1409 1410 /* update format */ 1411 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1412 1413 if (pipe->sspp->ops.setup_cdp) { 1414 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1415 1416 pipe->sspp->ops.setup_cdp(pipe, fmt, 1417 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1418 } 1419 } 1420 1421 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1422 1423 if (pipe->sspp->idx != SSPP_CURSOR0 && 1424 pipe->sspp->idx != SSPP_CURSOR1) 1425 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1426 1427 if (pstate->needs_qos_remap) 1428 _dpu_plane_set_qos_remap(plane, pipe); 1429 } 1430 1431 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, 1432 struct drm_plane_state *new_state) 1433 { 1434 struct dpu_plane *pdpu = to_dpu_plane(plane); 1435 struct drm_plane_state *state = plane->state; 1436 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1437 struct dpu_sw_pipe *pipe = &pstate->pipe; 1438 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1439 struct drm_crtc *crtc = state->crtc; 1440 struct drm_framebuffer *fb = state->fb; 1441 bool is_rt_pipe; 1442 const struct msm_format *fmt = 1443 msm_framebuffer_format(fb); 1444 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1445 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1446 1447 pstate->pending = true; 1448 1449 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1450 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1451 pdpu->is_rt_pipe = is_rt_pipe; 1452 1453 dpu_format_populate_addrs(new_state->fb, &pstate->layout); 1454 1455 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1456 ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1457 crtc->base.id, DRM_RECT_ARG(&state->dst), 1458 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); 1459 1460 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1461 drm_mode_vrefresh(&crtc->mode), 1462 &pstate->layout); 1463 1464 if (r_pipe->sspp) { 1465 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1466 drm_mode_vrefresh(&crtc->mode), 1467 &pstate->layout); 1468 } 1469 1470 if (pstate->needs_qos_remap) 1471 pstate->needs_qos_remap = false; 1472 1473 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1474 &crtc->mode, pipe_cfg); 1475 1476 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1477 1478 if (r_pipe->sspp) { 1479 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1480 1481 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1482 } 1483 } 1484 1485 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1486 { 1487 struct drm_plane_state *state = plane->state; 1488 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1489 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1490 1491 trace_dpu_plane_disable(DRMID(plane), false, 1492 pstate->pipe.multirect_mode); 1493 1494 if (r_pipe->sspp) { 1495 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1496 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1497 1498 if (r_pipe->sspp->ops.setup_multirect) 1499 r_pipe->sspp->ops.setup_multirect(r_pipe); 1500 } 1501 1502 pstate->pending = true; 1503 } 1504 1505 static void dpu_plane_atomic_update(struct drm_plane *plane, 1506 struct drm_atomic_state *state) 1507 { 1508 struct dpu_plane *pdpu = to_dpu_plane(plane); 1509 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1510 plane); 1511 1512 pdpu->is_error = false; 1513 1514 DPU_DEBUG_PLANE(pdpu, "\n"); 1515 1516 if (!new_state->visible) { 1517 _dpu_plane_atomic_disable(plane); 1518 } else { 1519 dpu_plane_sspp_atomic_update(plane, new_state); 1520 } 1521 } 1522 1523 static void dpu_plane_destroy_state(struct drm_plane *plane, 1524 struct drm_plane_state *state) 1525 { 1526 __drm_atomic_helper_plane_destroy_state(state); 1527 kfree(to_dpu_plane_state(state)); 1528 } 1529 1530 static struct drm_plane_state * 1531 dpu_plane_duplicate_state(struct drm_plane *plane) 1532 { 1533 struct dpu_plane *pdpu; 1534 struct dpu_plane_state *pstate; 1535 struct dpu_plane_state *old_state; 1536 1537 if (!plane) { 1538 DPU_ERROR("invalid plane\n"); 1539 return NULL; 1540 } else if (!plane->state) { 1541 DPU_ERROR("invalid plane state\n"); 1542 return NULL; 1543 } 1544 1545 old_state = to_dpu_plane_state(plane->state); 1546 pdpu = to_dpu_plane(plane); 1547 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1548 if (!pstate) { 1549 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1550 return NULL; 1551 } 1552 1553 DPU_DEBUG_PLANE(pdpu, "\n"); 1554 1555 pstate->pending = false; 1556 1557 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1558 1559 return &pstate->base; 1560 } 1561 1562 static const char * const multirect_mode_name[] = { 1563 [DPU_SSPP_MULTIRECT_NONE] = "none", 1564 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1565 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1566 }; 1567 1568 static const char * const multirect_index_name[] = { 1569 [DPU_SSPP_RECT_SOLO] = "solo", 1570 [DPU_SSPP_RECT_0] = "rect_0", 1571 [DPU_SSPP_RECT_1] = "rect_1", 1572 }; 1573 1574 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1575 { 1576 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1577 return "unknown"; 1578 1579 return multirect_mode_name[mode]; 1580 } 1581 1582 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1583 { 1584 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1585 return "unknown"; 1586 1587 return multirect_index_name[index]; 1588 } 1589 1590 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1591 const struct drm_plane_state *state) 1592 { 1593 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1594 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1595 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1596 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1597 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1598 1599 drm_printf(p, "\tstage=%d\n", pstate->stage); 1600 1601 if (pipe->sspp) { 1602 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1603 drm_printf(p, "\tmultirect_mode[0]=%s\n", 1604 dpu_get_multirect_mode(pipe->multirect_mode)); 1605 drm_printf(p, "\tmultirect_index[0]=%s\n", 1606 dpu_get_multirect_index(pipe->multirect_index)); 1607 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1608 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1609 } 1610 1611 if (r_pipe->sspp) { 1612 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1613 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1614 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1615 drm_printf(p, "\tmultirect_index[1]=%s\n", 1616 dpu_get_multirect_index(r_pipe->multirect_index)); 1617 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1618 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1619 } 1620 } 1621 1622 static void dpu_plane_reset(struct drm_plane *plane) 1623 { 1624 struct dpu_plane *pdpu; 1625 struct dpu_plane_state *pstate; 1626 1627 if (!plane) { 1628 DPU_ERROR("invalid plane\n"); 1629 return; 1630 } 1631 1632 pdpu = to_dpu_plane(plane); 1633 DPU_DEBUG_PLANE(pdpu, "\n"); 1634 1635 /* remove previous state, if present */ 1636 if (plane->state) { 1637 dpu_plane_destroy_state(plane, plane->state); 1638 plane->state = NULL; 1639 } 1640 1641 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1642 if (!pstate) { 1643 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1644 return; 1645 } 1646 1647 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1648 } 1649 1650 #ifdef CONFIG_DEBUG_FS 1651 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1652 { 1653 struct dpu_plane *pdpu = to_dpu_plane(plane); 1654 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1655 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1656 1657 if (!pdpu->is_rt_pipe) 1658 return; 1659 1660 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1661 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1662 if (pstate->r_pipe.sspp) 1663 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1664 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1665 } 1666 #endif 1667 1668 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1669 uint32_t format, uint64_t modifier) 1670 { 1671 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1672 bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0) && 1673 (dpu_kms->mdss->ubwc_dec_version == 0); 1674 1675 if (modifier == DRM_FORMAT_MOD_LINEAR) 1676 return true; 1677 1678 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc) 1679 return dpu_find_format(format, qcom_compressed_supported_formats, 1680 ARRAY_SIZE(qcom_compressed_supported_formats)); 1681 1682 return false; 1683 } 1684 1685 static const struct drm_plane_funcs dpu_plane_funcs = { 1686 .update_plane = drm_atomic_helper_update_plane, 1687 .disable_plane = drm_atomic_helper_disable_plane, 1688 .reset = dpu_plane_reset, 1689 .atomic_duplicate_state = dpu_plane_duplicate_state, 1690 .atomic_destroy_state = dpu_plane_destroy_state, 1691 .atomic_print_state = dpu_plane_atomic_print_state, 1692 .format_mod_supported = dpu_plane_format_mod_supported, 1693 }; 1694 1695 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1696 .prepare_fb = dpu_plane_prepare_fb, 1697 .cleanup_fb = dpu_plane_cleanup_fb, 1698 .atomic_check = dpu_plane_atomic_check, 1699 .atomic_update = dpu_plane_atomic_update, 1700 }; 1701 1702 static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { 1703 .prepare_fb = dpu_plane_prepare_fb, 1704 .cleanup_fb = dpu_plane_cleanup_fb, 1705 .atomic_check = dpu_plane_virtual_atomic_check, 1706 .atomic_update = dpu_plane_atomic_update, 1707 }; 1708 1709 /* initialize plane */ 1710 static struct drm_plane *dpu_plane_init_common(struct drm_device *dev, 1711 enum drm_plane_type type, 1712 unsigned long possible_crtcs, 1713 bool inline_rotation, 1714 const uint32_t *format_list, 1715 uint32_t num_formats, 1716 enum dpu_sspp pipe) 1717 { 1718 struct drm_plane *plane = NULL; 1719 struct dpu_plane *pdpu; 1720 struct msm_drm_private *priv = dev->dev_private; 1721 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1722 uint32_t supported_rotations; 1723 int ret; 1724 1725 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 1726 0xff, &dpu_plane_funcs, 1727 format_list, num_formats, 1728 supported_format_modifiers, type, NULL); 1729 if (IS_ERR(pdpu)) 1730 return ERR_CAST(pdpu); 1731 1732 /* cache local stuff for later */ 1733 plane = &pdpu->base; 1734 pdpu->pipe = pipe; 1735 1736 pdpu->catalog = kms->catalog; 1737 1738 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1739 if (ret) 1740 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1741 1742 drm_plane_create_alpha_property(plane); 1743 drm_plane_create_blend_mode_property(plane, 1744 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1745 BIT(DRM_MODE_BLEND_PREMULTI) | 1746 BIT(DRM_MODE_BLEND_COVERAGE)); 1747 1748 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1749 1750 if (inline_rotation) 1751 supported_rotations |= DRM_MODE_ROTATE_MASK; 1752 1753 drm_plane_create_rotation_property(plane, 1754 DRM_MODE_ROTATE_0, supported_rotations); 1755 1756 drm_plane_enable_fb_damage_clips(plane); 1757 1758 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1759 pipe, plane->base.id); 1760 return plane; 1761 } 1762 1763 /** 1764 * dpu_plane_init - create new dpu plane for the given pipe 1765 * @dev: Pointer to DRM device 1766 * @pipe: dpu hardware pipe identifier 1767 * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1768 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1769 * 1770 * Initialize the plane. 1771 */ 1772 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1773 uint32_t pipe, enum drm_plane_type type, 1774 unsigned long possible_crtcs) 1775 { 1776 struct drm_plane *plane = NULL; 1777 struct msm_drm_private *priv = dev->dev_private; 1778 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1779 struct dpu_hw_sspp *pipe_hw; 1780 1781 /* initialize underlying h/w driver */ 1782 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1783 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1784 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1785 return ERR_PTR(-EINVAL); 1786 } 1787 1788 1789 plane = dpu_plane_init_common(dev, type, possible_crtcs, 1790 pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION), 1791 pipe_hw->cap->sblk->format_list, 1792 pipe_hw->cap->sblk->num_formats, 1793 pipe); 1794 if (IS_ERR(plane)) 1795 return plane; 1796 1797 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1798 1799 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1800 pipe, plane->base.id); 1801 1802 return plane; 1803 } 1804 1805 /** 1806 * dpu_plane_init_virtual - create new virtualized DPU plane 1807 * @dev: Pointer to DRM device 1808 * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1809 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1810 * 1811 * Initialize the virtual plane with no backing SSPP / pipe. 1812 */ 1813 struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, 1814 enum drm_plane_type type, 1815 unsigned long possible_crtcs) 1816 { 1817 struct drm_plane *plane = NULL; 1818 struct msm_drm_private *priv = dev->dev_private; 1819 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1820 bool has_inline_rotation = false; 1821 const u32 *format_list = NULL; 1822 u32 num_formats = 0; 1823 int i; 1824 1825 /* Determine the largest configuration that we can implement */ 1826 for (i = 0; i < kms->catalog->sspp_count; i++) { 1827 const struct dpu_sspp_cfg *cfg = &kms->catalog->sspp[i]; 1828 1829 if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features)) 1830 has_inline_rotation = true; 1831 1832 if (!format_list || 1833 cfg->sblk->csc_blk.len) { 1834 format_list = cfg->sblk->format_list; 1835 num_formats = cfg->sblk->num_formats; 1836 } 1837 } 1838 1839 plane = dpu_plane_init_common(dev, type, possible_crtcs, 1840 has_inline_rotation, 1841 format_list, 1842 num_formats, 1843 SSPP_NONE); 1844 if (IS_ERR(plane)) 1845 return plane; 1846 1847 drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs); 1848 1849 DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id); 1850 1851 return plane; 1852 } 1853