1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 12 #include <linux/debugfs.h> 13 #include <linux/dma-buf.h> 14 #include <linux/of_irq.h> 15 #include <linux/pm_opp.h> 16 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_vblank.h> 21 #include <drm/drm_writeback.h> 22 23 #include <linux/soc/qcom/ubwc.h> 24 25 #include "msm_drv.h" 26 #include "msm_mmu.h" 27 #include "msm_gem.h" 28 #include "disp/msm_disp_snapshot.h" 29 30 #include "dpu_core_irq.h" 31 #include "dpu_crtc.h" 32 #include "dpu_encoder.h" 33 #include "dpu_formats.h" 34 #include "dpu_hw_vbif.h" 35 #include "dpu_kms.h" 36 #include "dpu_plane.h" 37 #include "dpu_vbif.h" 38 #include "dpu_writeback.h" 39 40 #define CREATE_TRACE_POINTS 41 #include "dpu_trace.h" 42 43 /* 44 * To enable overall DRM driver logging 45 * # echo 0x2 > /sys/module/drm/parameters/debug 46 * 47 * To enable DRM driver h/w logging 48 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask 49 * 50 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_) 51 */ 52 #define DPU_DEBUGFS_DIR "msm_dpu" 53 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 54 55 bool dpu_use_virtual_planes; 56 module_param(dpu_use_virtual_planes, bool, 0); 57 58 static int dpu_kms_hw_init(struct msm_kms *kms); 59 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 60 61 #ifdef CONFIG_DEBUG_FS 62 static int _dpu_danger_signal_status(struct seq_file *s, 63 bool danger_status) 64 { 65 struct dpu_danger_safe_status status; 66 struct dpu_kms *kms = s->private; 67 int i; 68 69 if (!kms->hw_mdp) { 70 DPU_ERROR("invalid arg(s)\n"); 71 return 0; 72 } 73 74 memset(&status, 0, sizeof(struct dpu_danger_safe_status)); 75 76 pm_runtime_get_sync(&kms->pdev->dev); 77 if (danger_status) { 78 seq_puts(s, "\nDanger signal status:\n"); 79 if (kms->hw_mdp->ops.get_danger_status) 80 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, 81 &status); 82 } else { 83 seq_puts(s, "\nSafe signal status:\n"); 84 if (kms->hw_mdp->ops.get_safe_status) 85 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, 86 &status); 87 } 88 pm_runtime_put_sync(&kms->pdev->dev); 89 90 seq_printf(s, "MDP : 0x%x\n", status.mdp); 91 92 for (i = SSPP_VIG0; i < SSPP_MAX; i++) 93 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, 94 status.sspp[i]); 95 seq_puts(s, "\n"); 96 97 return 0; 98 } 99 100 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v) 101 { 102 return _dpu_danger_signal_status(s, true); 103 } 104 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats); 105 106 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) 107 { 108 return _dpu_danger_signal_status(s, false); 109 } 110 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); 111 112 static ssize_t _dpu_plane_danger_read(struct file *file, 113 char __user *buff, size_t count, loff_t *ppos) 114 { 115 struct dpu_kms *kms = file->private_data; 116 int len; 117 char buf[40]; 118 119 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 120 121 return simple_read_from_buffer(buff, count, ppos, buf, len); 122 } 123 124 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 125 { 126 struct drm_plane *plane; 127 128 drm_for_each_plane(plane, kms->dev) { 129 if (plane->fb && plane->state) { 130 dpu_plane_danger_signal_ctrl(plane, enable); 131 DPU_DEBUG("plane:%d img:%dx%d ", 132 plane->base.id, plane->fb->width, 133 plane->fb->height); 134 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 135 plane->state->src_x >> 16, 136 plane->state->src_y >> 16, 137 plane->state->src_w >> 16, 138 plane->state->src_h >> 16, 139 plane->state->crtc_x, plane->state->crtc_y, 140 plane->state->crtc_w, plane->state->crtc_h); 141 } else { 142 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 143 } 144 } 145 } 146 147 static ssize_t _dpu_plane_danger_write(struct file *file, 148 const char __user *user_buf, size_t count, loff_t *ppos) 149 { 150 struct dpu_kms *kms = file->private_data; 151 int disable_panic; 152 int ret; 153 154 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 155 if (ret) 156 return ret; 157 158 if (disable_panic) { 159 /* Disable panic signal for all active pipes */ 160 DPU_DEBUG("Disabling danger:\n"); 161 _dpu_plane_set_danger_state(kms, false); 162 kms->has_danger_ctrl = false; 163 } else { 164 /* Enable panic signal for all active pipes */ 165 DPU_DEBUG("Enabling danger:\n"); 166 kms->has_danger_ctrl = true; 167 _dpu_plane_set_danger_state(kms, true); 168 } 169 170 return count; 171 } 172 173 static const struct file_operations dpu_plane_danger_enable = { 174 .open = simple_open, 175 .read = _dpu_plane_danger_read, 176 .write = _dpu_plane_danger_write, 177 }; 178 179 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, 180 struct dentry *parent) 181 { 182 struct dentry *entry = debugfs_create_dir("danger", parent); 183 184 debugfs_create_file("danger_status", 0600, entry, 185 dpu_kms, &dpu_debugfs_danger_stats_fops); 186 debugfs_create_file("safe_status", 0600, entry, 187 dpu_kms, &dpu_debugfs_safe_stats_fops); 188 debugfs_create_file("disable_danger", 0600, entry, 189 dpu_kms, &dpu_plane_danger_enable); 190 191 } 192 193 /* 194 * Companion structure for dpu_debugfs_create_regset32. 195 */ 196 struct dpu_debugfs_regset32 { 197 uint32_t offset; 198 uint32_t blk_len; 199 struct dpu_kms *dpu_kms; 200 }; 201 202 static int dpu_regset32_show(struct seq_file *s, void *data) 203 { 204 struct dpu_debugfs_regset32 *regset = s->private; 205 struct dpu_kms *dpu_kms = regset->dpu_kms; 206 void __iomem *base; 207 uint32_t i, addr; 208 209 if (!dpu_kms->mmio) 210 return 0; 211 212 base = dpu_kms->mmio + regset->offset; 213 214 /* insert padding spaces, if needed */ 215 if (regset->offset & 0xF) { 216 seq_printf(s, "[%x]", regset->offset & ~0xF); 217 for (i = 0; i < (regset->offset & 0xF); i += 4) 218 seq_puts(s, " "); 219 } 220 221 pm_runtime_get_sync(&dpu_kms->pdev->dev); 222 223 /* main register output */ 224 for (i = 0; i < regset->blk_len; i += 4) { 225 addr = regset->offset + i; 226 if ((addr & 0xF) == 0x0) 227 seq_printf(s, i ? "\n[%x]" : "[%x]", addr); 228 seq_printf(s, " %08x", readl_relaxed(base + i)); 229 } 230 seq_puts(s, "\n"); 231 pm_runtime_put_sync(&dpu_kms->pdev->dev); 232 233 return 0; 234 } 235 DEFINE_SHOW_ATTRIBUTE(dpu_regset32); 236 237 /** 238 * dpu_debugfs_create_regset32 - Create register read back file for debugfs 239 * 240 * This function is almost identical to the standard debugfs_create_regset32() 241 * function, with the main difference being that a list of register 242 * names/offsets do not need to be provided. The 'read' function simply outputs 243 * sequential register values over a specified range. 244 * 245 * @name: File name within debugfs 246 * @mode: File mode within debugfs 247 * @parent: Parent directory entry within debugfs, can be NULL 248 * @offset: sub-block offset 249 * @length: sub-block length, in bytes 250 * @dpu_kms: pointer to dpu kms structure 251 */ 252 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 253 void *parent, 254 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) 255 { 256 struct dpu_debugfs_regset32 *regset; 257 258 if (WARN_ON(!name || !dpu_kms || !length)) 259 return; 260 261 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); 262 if (!regset) 263 return; 264 265 /* make sure offset is a multiple of 4 */ 266 regset->offset = round_down(offset, 4); 267 regset->blk_len = length; 268 regset->dpu_kms = dpu_kms; 269 270 debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops); 271 } 272 273 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) 274 { 275 struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); 276 int i; 277 278 if (IS_ERR(entry)) 279 return; 280 281 for (i = SSPP_NONE; i < SSPP_MAX; i++) { 282 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); 283 284 if (!hw) 285 continue; 286 287 _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry); 288 } 289 } 290 291 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 292 { 293 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 294 void *p = dpu_hw_util_get_log_mask_ptr(); 295 struct dentry *entry; 296 297 if (!p) 298 return -EINVAL; 299 300 /* Only create a set of debugfs for the primary node, ignore render nodes */ 301 if (minor->type != DRM_MINOR_PRIMARY) 302 return 0; 303 304 entry = debugfs_create_dir("debug", minor->debugfs_root); 305 306 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p); 307 308 dpu_debugfs_danger_init(dpu_kms, entry); 309 dpu_debugfs_vbif_init(dpu_kms, entry); 310 dpu_debugfs_core_irq_init(dpu_kms, entry); 311 dpu_debugfs_sspp_init(dpu_kms, entry); 312 313 return dpu_core_perf_debugfs_init(dpu_kms, entry); 314 } 315 #endif 316 317 /* Global/shared object state funcs */ 318 319 /* 320 * This is a helper that returns the private state currently in operation. 321 * Note that this would return the "old_state" if called in the atomic check 322 * path, and the "new_state" after the atomic swap has been done. 323 */ 324 struct dpu_global_state * 325 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms) 326 { 327 return to_dpu_global_state(dpu_kms->global_state.state); 328 } 329 330 /* 331 * This acquires the modeset lock set aside for global state, creates 332 * a new duplicated private object state. 333 */ 334 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) 335 { 336 struct msm_drm_private *priv = s->dev->dev_private; 337 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 338 struct drm_private_state *priv_state; 339 340 priv_state = drm_atomic_get_private_obj_state(s, 341 &dpu_kms->global_state); 342 if (IS_ERR(priv_state)) 343 return ERR_CAST(priv_state); 344 345 return to_dpu_global_state(priv_state); 346 } 347 348 static struct drm_private_state * 349 dpu_kms_global_duplicate_state(struct drm_private_obj *obj) 350 { 351 struct dpu_global_state *state; 352 353 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 354 if (!state) 355 return NULL; 356 357 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 358 359 return &state->base; 360 } 361 362 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, 363 struct drm_private_state *state) 364 { 365 struct dpu_global_state *dpu_state = to_dpu_global_state(state); 366 367 kfree(dpu_state); 368 } 369 370 static void dpu_kms_global_print_state(struct drm_printer *p, 371 const struct drm_private_state *state) 372 { 373 const struct dpu_global_state *global_state = to_dpu_global_state(state); 374 375 dpu_rm_print_state(p, global_state); 376 } 377 378 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { 379 .atomic_duplicate_state = dpu_kms_global_duplicate_state, 380 .atomic_destroy_state = dpu_kms_global_destroy_state, 381 .atomic_print_state = dpu_kms_global_print_state, 382 }; 383 384 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) 385 { 386 struct dpu_global_state *state; 387 388 state = kzalloc(sizeof(*state), GFP_KERNEL); 389 if (!state) 390 return -ENOMEM; 391 392 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, 393 &state->base, 394 &dpu_kms_global_state_funcs); 395 396 state->rm = &dpu_kms->rm; 397 398 return 0; 399 } 400 401 static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms) 402 { 403 drm_atomic_private_obj_fini(&dpu_kms->global_state); 404 } 405 406 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) 407 { 408 struct icc_path *path0; 409 struct icc_path *path1; 410 struct device *dpu_dev = &dpu_kms->pdev->dev; 411 412 path0 = msm_icc_get(dpu_dev, "mdp0-mem"); 413 path1 = msm_icc_get(dpu_dev, "mdp1-mem"); 414 415 if (IS_ERR_OR_NULL(path0)) 416 return PTR_ERR_OR_ZERO(path0); 417 418 dpu_kms->path[0] = path0; 419 dpu_kms->num_paths = 1; 420 421 if (!IS_ERR_OR_NULL(path1)) { 422 dpu_kms->path[1] = path1; 423 dpu_kms->num_paths++; 424 } 425 return 0; 426 } 427 428 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 429 { 430 return dpu_crtc_vblank(crtc, true); 431 } 432 433 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) 434 { 435 dpu_crtc_vblank(crtc, false); 436 } 437 438 static void dpu_kms_enable_commit(struct msm_kms *kms) 439 { 440 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 441 pm_runtime_get_sync(&dpu_kms->pdev->dev); 442 } 443 444 static void dpu_kms_disable_commit(struct msm_kms *kms) 445 { 446 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 447 pm_runtime_put_sync(&dpu_kms->pdev->dev); 448 } 449 450 static int dpu_kms_check_mode_changed(struct msm_kms *kms, struct drm_atomic_state *state) 451 { 452 struct drm_crtc_state *new_crtc_state; 453 struct drm_crtc_state *old_crtc_state; 454 struct drm_crtc *crtc; 455 int i; 456 457 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) 458 dpu_crtc_check_mode_changed(old_crtc_state, new_crtc_state); 459 460 return 0; 461 } 462 463 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 464 { 465 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 466 struct drm_crtc *crtc; 467 468 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { 469 if (!crtc->state->active) 470 continue; 471 472 trace_dpu_kms_commit(DRMID(crtc)); 473 dpu_crtc_commit_kickoff(crtc); 474 } 475 } 476 477 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 478 { 479 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 480 struct drm_crtc *crtc; 481 482 DPU_ATRACE_BEGIN("kms_complete_commit"); 483 484 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 485 dpu_crtc_complete_commit(crtc); 486 487 DPU_ATRACE_END("kms_complete_commit"); 488 } 489 490 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, 491 struct drm_crtc *crtc) 492 { 493 struct drm_encoder *encoder; 494 struct drm_device *dev; 495 int ret; 496 497 if (!kms || !crtc || !crtc->state) { 498 DPU_ERROR("invalid params\n"); 499 return; 500 } 501 502 dev = crtc->dev; 503 504 if (!crtc->state->enable) { 505 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); 506 return; 507 } 508 509 if (!drm_atomic_crtc_effectively_active(crtc->state)) { 510 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); 511 return; 512 } 513 514 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 515 if (encoder->crtc != crtc) 516 continue; 517 /* 518 * Wait for post-flush if necessary to delay before 519 * plane_cleanup. For example, wait for vsync in case of video 520 * mode panels. This may be a no-op for command mode panels. 521 */ 522 trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); 523 ret = dpu_encoder_wait_for_commit_done(encoder); 524 if (ret && ret != -EWOULDBLOCK) { 525 DPU_ERROR("wait for commit done returned %d\n", ret); 526 break; 527 } 528 } 529 } 530 531 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 532 { 533 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 534 struct drm_crtc *crtc; 535 536 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) 537 dpu_kms_wait_for_commit_done(kms, crtc); 538 } 539 540 static const char *dpu_vsync_sources[] = { 541 [DPU_VSYNC_SOURCE_GPIO_0] = "mdp_vsync_p", 542 [DPU_VSYNC_SOURCE_GPIO_1] = "mdp_vsync_s", 543 [DPU_VSYNC_SOURCE_GPIO_2] = "mdp_vsync_e", 544 [DPU_VSYNC_SOURCE_INTF_0] = "mdp_intf0", 545 [DPU_VSYNC_SOURCE_INTF_1] = "mdp_intf1", 546 [DPU_VSYNC_SOURCE_INTF_2] = "mdp_intf2", 547 [DPU_VSYNC_SOURCE_INTF_3] = "mdp_intf3", 548 [DPU_VSYNC_SOURCE_WD_TIMER_0] = "timer0", 549 [DPU_VSYNC_SOURCE_WD_TIMER_1] = "timer1", 550 [DPU_VSYNC_SOURCE_WD_TIMER_2] = "timer2", 551 [DPU_VSYNC_SOURCE_WD_TIMER_3] = "timer3", 552 [DPU_VSYNC_SOURCE_WD_TIMER_4] = "timer4", 553 }; 554 555 static int dpu_kms_dsi_set_te_source(struct msm_display_info *info, 556 struct msm_dsi *dsi) 557 { 558 const char *te_source = msm_dsi_get_te_source(dsi); 559 int i; 560 561 if (!te_source) { 562 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; 563 return 0; 564 } 565 566 /* we can not use match_string since dpu_vsync_sources is a sparse array */ 567 for (i = 0; i < ARRAY_SIZE(dpu_vsync_sources); i++) { 568 if (dpu_vsync_sources[i] && 569 !strcmp(dpu_vsync_sources[i], te_source)) { 570 info->vsync_source = i; 571 return 0; 572 } 573 } 574 575 return -EINVAL; 576 } 577 578 static int _dpu_kms_initialize_dsi(struct drm_device *dev, 579 struct msm_drm_private *priv, 580 struct dpu_kms *dpu_kms) 581 { 582 struct drm_encoder *encoder = NULL; 583 struct msm_display_info info; 584 int i, rc = 0; 585 586 if (!(priv->kms->dsi[0] || priv->kms->dsi[1])) 587 return rc; 588 589 /* 590 * We support following confiurations: 591 * - Single DSI host (dsi0 or dsi1) 592 * - Two independent DSI hosts 593 * - Bonded DSI0 and DSI1 hosts 594 * 595 * TODO: Support swapping DSI0 and DSI1 in the bonded setup. 596 */ 597 for (i = 0; i < ARRAY_SIZE(priv->kms->dsi); i++) { 598 int other = (i + 1) % 2; 599 600 if (!priv->kms->dsi[i]) 601 continue; 602 603 if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && 604 !msm_dsi_is_master_dsi(priv->kms->dsi[i])) 605 continue; 606 607 memset(&info, 0, sizeof(info)); 608 info.intf_type = INTF_DSI; 609 610 info.h_tile_instance[info.num_of_h_tiles++] = i; 611 if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i])) 612 info.h_tile_instance[info.num_of_h_tiles++] = other; 613 614 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->kms->dsi[i]); 615 616 rc = dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); 617 if (rc) { 618 DPU_ERROR("failed to identify TE source for dsi display\n"); 619 return rc; 620 } 621 622 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info); 623 if (IS_ERR(encoder)) { 624 DPU_ERROR("encoder init failed for dsi display\n"); 625 return PTR_ERR(encoder); 626 } 627 628 rc = msm_dsi_modeset_init(priv->kms->dsi[i], dev, encoder); 629 if (rc) { 630 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 631 i, rc); 632 break; 633 } 634 635 if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && priv->kms->dsi[other]) { 636 rc = msm_dsi_modeset_init(priv->kms->dsi[other], dev, encoder); 637 if (rc) { 638 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n", 639 other, rc); 640 break; 641 } 642 } 643 } 644 645 return rc; 646 } 647 648 static int _dpu_kms_initialize_displayport(struct drm_device *dev, 649 struct msm_drm_private *priv, 650 struct dpu_kms *dpu_kms) 651 { 652 struct drm_encoder *encoder = NULL; 653 struct msm_display_info info; 654 bool yuv_supported; 655 int rc; 656 int i; 657 658 for (i = 0; i < ARRAY_SIZE(priv->kms->dp); i++) { 659 if (!priv->kms->dp[i]) 660 continue; 661 662 memset(&info, 0, sizeof(info)); 663 info.num_of_h_tiles = 1; 664 info.h_tile_instance[0] = i; 665 info.intf_type = INTF_DP; 666 667 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); 668 if (IS_ERR(encoder)) { 669 DPU_ERROR("encoder init failed for dsi display\n"); 670 return PTR_ERR(encoder); 671 } 672 673 yuv_supported = !!dpu_kms->catalog->cdm; 674 rc = msm_dp_modeset_init(priv->kms->dp[i], dev, encoder, yuv_supported); 675 if (rc) { 676 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 677 return rc; 678 } 679 } 680 681 return 0; 682 } 683 684 static int _dpu_kms_initialize_hdmi(struct drm_device *dev, 685 struct msm_drm_private *priv, 686 struct dpu_kms *dpu_kms) 687 { 688 struct drm_encoder *encoder = NULL; 689 struct msm_display_info info; 690 int rc; 691 692 if (!priv->kms->hdmi) 693 return 0; 694 695 memset(&info, 0, sizeof(info)); 696 info.num_of_h_tiles = 1; 697 info.h_tile_instance[0] = 0; 698 info.intf_type = INTF_HDMI; 699 700 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info); 701 if (IS_ERR(encoder)) { 702 DPU_ERROR("encoder init failed for HDMI display\n"); 703 return PTR_ERR(encoder); 704 } 705 706 rc = msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); 707 if (rc) { 708 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); 709 return rc; 710 } 711 712 return 0; 713 } 714 715 static int _dpu_kms_initialize_writeback(struct drm_device *dev, 716 struct msm_drm_private *priv, struct dpu_kms *dpu_kms, 717 const u32 *wb_formats, int n_formats) 718 { 719 struct drm_encoder *encoder = NULL; 720 struct msm_display_info info; 721 const enum dpu_wb wb_idx = WB_2; 722 u32 maxlinewidth; 723 int rc; 724 725 memset(&info, 0, sizeof(info)); 726 727 info.num_of_h_tiles = 1; 728 /* use only WB idx 2 instance for DPU */ 729 info.h_tile_instance[0] = wb_idx; 730 info.intf_type = INTF_WB; 731 732 maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; 733 734 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info); 735 if (IS_ERR(encoder)) { 736 DPU_ERROR("encoder init failed for dsi display\n"); 737 return PTR_ERR(encoder); 738 } 739 740 rc = dpu_writeback_init(dev, encoder, wb_formats, n_formats, maxlinewidth); 741 if (rc) { 742 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc); 743 return rc; 744 } 745 746 return 0; 747 } 748 749 /** 750 * _dpu_kms_setup_displays - create encoders, bridges and connectors 751 * for underlying displays 752 * @dev: Pointer to drm device structure 753 * @priv: Pointer to private drm device data 754 * @dpu_kms: Pointer to dpu kms structure 755 * Returns: Zero on success 756 */ 757 static int _dpu_kms_setup_displays(struct drm_device *dev, 758 struct msm_drm_private *priv, 759 struct dpu_kms *dpu_kms) 760 { 761 int rc = 0; 762 int i; 763 764 rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); 765 if (rc) { 766 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); 767 return rc; 768 } 769 770 rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); 771 if (rc) { 772 DPU_ERROR("initialize_DP failed, rc = %d\n", rc); 773 return rc; 774 } 775 776 rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms); 777 if (rc) { 778 DPU_ERROR("initialize HDMI failed, rc = %d\n", rc); 779 return rc; 780 } 781 782 /* Since WB isn't a driver check the catalog before initializing */ 783 if (dpu_kms->catalog->wb_count) { 784 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { 785 if (dpu_kms->catalog->wb[i].id == WB_2) { 786 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms, 787 dpu_kms->catalog->wb[i].format_list, 788 dpu_kms->catalog->wb[i].num_formats); 789 if (rc) { 790 DPU_ERROR("initialize_WB failed, rc = %d\n", rc); 791 return rc; 792 } 793 } 794 } 795 } 796 797 return rc; 798 } 799 800 #define MAX_PLANES 20 801 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) 802 { 803 struct drm_device *dev; 804 struct drm_plane *primary_planes[MAX_PLANES], *plane; 805 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL }; 806 struct drm_crtc *crtc; 807 struct drm_encoder *encoder; 808 unsigned int num_encoders; 809 810 struct msm_drm_private *priv; 811 const struct dpu_mdss_cfg *catalog; 812 813 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; 814 int max_crtc_count; 815 dev = dpu_kms->dev; 816 priv = dev->dev_private; 817 catalog = dpu_kms->catalog; 818 819 /* 820 * Create encoder and query display drivers to create 821 * bridges and connectors 822 */ 823 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms); 824 if (ret) 825 return ret; 826 827 num_encoders = 0; 828 drm_for_each_encoder(encoder, dev) { 829 num_encoders++; 830 if (catalog->cwb_count > 0) 831 encoder->possible_clones = dpu_encoder_get_clones(encoder); 832 } 833 834 max_crtc_count = min(catalog->mixer_count, num_encoders); 835 836 /* Create the planes, keeping track of one primary/cursor per crtc */ 837 for (i = 0; i < catalog->sspp_count; i++) { 838 enum drm_plane_type type; 839 840 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) 841 && cursor_planes_idx < max_crtc_count) 842 type = DRM_PLANE_TYPE_CURSOR; 843 else if (primary_planes_idx < max_crtc_count) 844 type = DRM_PLANE_TYPE_PRIMARY; 845 else 846 type = DRM_PLANE_TYPE_OVERLAY; 847 848 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n", 849 type, catalog->sspp[i].features, 850 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); 851 852 if (dpu_use_virtual_planes) 853 plane = dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1); 854 else 855 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, 856 (1UL << max_crtc_count) - 1); 857 if (IS_ERR(plane)) { 858 DPU_ERROR("dpu_plane_init failed\n"); 859 ret = PTR_ERR(plane); 860 return ret; 861 } 862 863 if (type == DRM_PLANE_TYPE_CURSOR) 864 cursor_planes[cursor_planes_idx++] = plane; 865 else if (type == DRM_PLANE_TYPE_PRIMARY) 866 primary_planes[primary_planes_idx++] = plane; 867 } 868 869 max_crtc_count = min(max_crtc_count, primary_planes_idx); 870 871 /* Create one CRTC per encoder */ 872 for (i = 0; i < max_crtc_count; i++) { 873 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); 874 if (IS_ERR(crtc)) { 875 ret = PTR_ERR(crtc); 876 return ret; 877 } 878 } 879 880 /* All CRTCs are compatible with all encoders */ 881 drm_for_each_encoder(encoder, dev) 882 encoder->possible_crtcs = (1 << dev->mode_config.num_crtc) - 1; 883 884 return 0; 885 } 886 887 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) 888 { 889 int i; 890 891 dpu_kms->hw_intr = NULL; 892 893 /* safe to call these more than once during shutdown */ 894 _dpu_kms_mmu_destroy(dpu_kms); 895 896 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { 897 dpu_kms->hw_vbif[i] = NULL; 898 } 899 900 dpu_kms_global_obj_fini(dpu_kms); 901 902 dpu_kms->catalog = NULL; 903 904 dpu_kms->hw_mdp = NULL; 905 } 906 907 static void dpu_kms_destroy(struct msm_kms *kms) 908 { 909 struct dpu_kms *dpu_kms; 910 911 if (!kms) { 912 DPU_ERROR("invalid kms\n"); 913 return; 914 } 915 916 dpu_kms = to_dpu_kms(kms); 917 918 _dpu_kms_hw_destroy(dpu_kms); 919 920 msm_kms_destroy(&dpu_kms->base); 921 922 if (dpu_kms->rpm_enabled) 923 pm_runtime_disable(&dpu_kms->pdev->dev); 924 } 925 926 static int dpu_irq_postinstall(struct msm_kms *kms) 927 { 928 struct msm_drm_private *priv; 929 struct dpu_kms *dpu_kms = to_dpu_kms(kms); 930 931 if (!dpu_kms || !dpu_kms->dev) 932 return -EINVAL; 933 934 priv = dpu_kms->dev->dev_private; 935 if (!priv) 936 return -EINVAL; 937 938 return 0; 939 } 940 941 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) 942 { 943 int i; 944 struct dpu_kms *dpu_kms; 945 const struct dpu_mdss_cfg *cat; 946 void __iomem *base; 947 948 dpu_kms = to_dpu_kms(kms); 949 950 cat = dpu_kms->catalog; 951 952 pm_runtime_get_sync(&dpu_kms->pdev->dev); 953 954 /* dump CTL sub-blocks HW regs info */ 955 for (i = 0; i < cat->ctl_count; i++) 956 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, 957 dpu_kms->mmio + cat->ctl[i].base, "%s", 958 cat->ctl[i].name); 959 960 /* dump DSPP sub-blocks HW regs info */ 961 for (i = 0; i < cat->dspp_count; i++) { 962 base = dpu_kms->mmio + cat->dspp[i].base; 963 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, 964 "%s", cat->dspp[i].name); 965 966 if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) 967 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, 968 base + cat->dspp[i].sblk->pcc.base, "%s_%s", 969 cat->dspp[i].name, 970 cat->dspp[i].sblk->pcc.name); 971 } 972 973 /* dump INTF sub-blocks HW regs info */ 974 for (i = 0; i < cat->intf_count; i++) 975 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, 976 dpu_kms->mmio + cat->intf[i].base, "%s", 977 cat->intf[i].name); 978 979 /* dump PP sub-blocks HW regs info */ 980 for (i = 0; i < cat->pingpong_count; i++) { 981 base = dpu_kms->mmio + cat->pingpong[i].base; 982 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base, 983 "%s", cat->pingpong[i].name); 984 985 /* TE2 sub-block has length of 0, so will not print it */ 986 987 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) 988 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, 989 base + cat->pingpong[i].sblk->dither.base, 990 "%s_%s", cat->pingpong[i].name, 991 cat->pingpong[i].sblk->dither.name); 992 } 993 994 /* dump SSPP sub-blocks HW regs info */ 995 for (i = 0; i < cat->sspp_count; i++) { 996 base = dpu_kms->mmio + cat->sspp[i].base; 997 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, 998 "%s", cat->sspp[i].name); 999 1000 if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) 1001 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, 1002 base + cat->sspp[i].sblk->scaler_blk.base, 1003 "%s_%s", cat->sspp[i].name, 1004 cat->sspp[i].sblk->scaler_blk.name); 1005 1006 if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) 1007 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, 1008 base + cat->sspp[i].sblk->csc_blk.base, 1009 "%s_%s", cat->sspp[i].name, 1010 cat->sspp[i].sblk->csc_blk.name); 1011 } 1012 1013 /* dump LM sub-blocks HW regs info */ 1014 for (i = 0; i < cat->mixer_count; i++) 1015 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, 1016 dpu_kms->mmio + cat->mixer[i].base, 1017 "%s", cat->mixer[i].name); 1018 1019 /* dump WB sub-blocks HW regs info */ 1020 for (i = 0; i < cat->wb_count; i++) 1021 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, 1022 dpu_kms->mmio + cat->wb[i].base, "%s", 1023 cat->wb[i].name); 1024 1025 if (dpu_kms->catalog->mdss_ver->core_major_ver >= 8) { 1026 msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, 1027 dpu_kms->mmio + cat->mdp[0].base, "top"); 1028 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, 1029 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); 1030 } else { 1031 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, 1032 dpu_kms->mmio + cat->mdp[0].base, "top"); 1033 } 1034 1035 /* dump CWB sub-blocks HW regs info */ 1036 for (i = 0; i < cat->cwb_count; i++) 1037 msm_disp_snapshot_add_block(disp_state, cat->cwb[i].len, 1038 dpu_kms->mmio + cat->cwb[i].base, cat->cwb[i].name); 1039 1040 /* dump DSC sub-blocks HW regs info */ 1041 for (i = 0; i < cat->dsc_count; i++) { 1042 base = dpu_kms->mmio + cat->dsc[i].base; 1043 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, 1044 "%s", cat->dsc[i].name); 1045 1046 if (cat->mdss_ver->core_major_ver >= 7) { 1047 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; 1048 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; 1049 1050 msm_disp_snapshot_add_block(disp_state, enc.len, base + enc.base, "%s_%s", 1051 cat->dsc[i].name, enc.name); 1052 msm_disp_snapshot_add_block(disp_state, ctl.len, base + ctl.base, "%s_%s", 1053 cat->dsc[i].name, ctl.name); 1054 } 1055 } 1056 1057 if (cat->cdm) 1058 msm_disp_snapshot_add_block(disp_state, cat->cdm->len, 1059 dpu_kms->mmio + cat->cdm->base, 1060 "%s", cat->cdm->name); 1061 1062 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1063 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; 1064 1065 msm_disp_snapshot_add_block(disp_state, vbif->len, 1066 dpu_kms->vbif[vbif->id] + vbif->base, 1067 "%s", vbif->name); 1068 } 1069 1070 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1071 } 1072 1073 static const struct msm_kms_funcs kms_funcs = { 1074 .hw_init = dpu_kms_hw_init, 1075 .irq_preinstall = dpu_core_irq_preinstall, 1076 .irq_postinstall = dpu_irq_postinstall, 1077 .irq_uninstall = dpu_core_irq_uninstall, 1078 .irq = dpu_core_irq, 1079 .enable_commit = dpu_kms_enable_commit, 1080 .disable_commit = dpu_kms_disable_commit, 1081 .check_mode_changed = dpu_kms_check_mode_changed, 1082 .flush_commit = dpu_kms_flush_commit, 1083 .wait_flush = dpu_kms_wait_flush, 1084 .complete_commit = dpu_kms_complete_commit, 1085 .enable_vblank = dpu_kms_enable_vblank, 1086 .disable_vblank = dpu_kms_disable_vblank, 1087 .destroy = dpu_kms_destroy, 1088 .snapshot = dpu_kms_mdp_snapshot, 1089 #ifdef CONFIG_DEBUG_FS 1090 .debugfs_init = dpu_kms_debugfs_init, 1091 #endif 1092 }; 1093 1094 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms) 1095 { 1096 struct msm_mmu *mmu; 1097 1098 if (!dpu_kms->base.vm) 1099 return; 1100 1101 mmu = to_msm_vm(dpu_kms->base.vm)->mmu; 1102 1103 mmu->funcs->detach(mmu); 1104 drm_gpuvm_put(dpu_kms->base.vm); 1105 1106 dpu_kms->base.vm = NULL; 1107 } 1108 1109 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms) 1110 { 1111 struct drm_gpuvm *vm; 1112 1113 vm = msm_kms_init_vm(dpu_kms->dev); 1114 if (IS_ERR(vm)) 1115 return PTR_ERR(vm); 1116 1117 dpu_kms->base.vm = vm; 1118 1119 return 0; 1120 } 1121 1122 /** 1123 * dpu_kms_get_clk_rate() - get the clock rate 1124 * @dpu_kms: pointer to dpu_kms structure 1125 * @clock_name: clock name to get the rate 1126 * 1127 * Return: current clock rate 1128 */ 1129 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1130 { 1131 struct clk *clk; 1132 1133 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); 1134 if (!clk) 1135 return 0; 1136 1137 return clk_get_rate(clk); 1138 } 1139 1140 #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 1141 1142 static int dpu_kms_hw_init(struct msm_kms *kms) 1143 { 1144 struct dpu_kms *dpu_kms; 1145 struct drm_device *dev; 1146 int i, rc = -EINVAL; 1147 unsigned long max_core_clk_rate; 1148 u32 core_rev; 1149 1150 if (!kms) { 1151 DPU_ERROR("invalid kms\n"); 1152 return rc; 1153 } 1154 1155 dpu_kms = to_dpu_kms(kms); 1156 dev = dpu_kms->dev; 1157 1158 dev->mode_config.cursor_width = 512; 1159 dev->mode_config.cursor_height = 512; 1160 1161 rc = dpu_kms_global_obj_init(dpu_kms); 1162 if (rc) 1163 return rc; 1164 1165 atomic_set(&dpu_kms->bandwidth_ref, 0); 1166 1167 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); 1168 if (rc < 0) 1169 goto error; 1170 1171 core_rev = readl_relaxed(dpu_kms->mmio + 0x0); 1172 1173 pr_info("dpu hardware revision:0x%x\n", core_rev); 1174 1175 dpu_kms->catalog = of_device_get_match_data(dev->dev); 1176 if (!dpu_kms->catalog) { 1177 DPU_ERROR("device config not known!\n"); 1178 rc = -EINVAL; 1179 goto err_pm_put; 1180 } 1181 1182 /* 1183 * Now we need to read the HW catalog and initialize resources such as 1184 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc 1185 */ 1186 rc = _dpu_kms_mmu_init(dpu_kms); 1187 if (rc) { 1188 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc); 1189 goto err_pm_put; 1190 } 1191 1192 dpu_kms->mdss = qcom_ubwc_config_get_data(); 1193 if (IS_ERR(dpu_kms->mdss)) { 1194 rc = PTR_ERR(dpu_kms->mdss); 1195 DPU_ERROR("failed to get UBWC config data: %d\n", rc); 1196 goto err_pm_put; 1197 } 1198 1199 if (!dpu_kms->mdss) { 1200 rc = -EINVAL; 1201 DPU_ERROR("NULL MDSS data\n"); 1202 goto err_pm_put; 1203 } 1204 1205 rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio); 1206 if (rc) { 1207 DPU_ERROR("rm init failed: %d\n", rc); 1208 goto err_pm_put; 1209 } 1210 1211 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev, 1212 dpu_kms->catalog->mdp, 1213 dpu_kms->mmio, 1214 dpu_kms->catalog->mdss_ver); 1215 if (IS_ERR(dpu_kms->hw_mdp)) { 1216 rc = PTR_ERR(dpu_kms->hw_mdp); 1217 DPU_ERROR("failed to get hw_mdp: %d\n", rc); 1218 dpu_kms->hw_mdp = NULL; 1219 goto err_pm_put; 1220 } 1221 1222 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { 1223 struct dpu_hw_vbif *hw; 1224 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; 1225 1226 hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]); 1227 if (IS_ERR(hw)) { 1228 rc = PTR_ERR(hw); 1229 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc); 1230 goto err_pm_put; 1231 } 1232 1233 dpu_kms->hw_vbif[vbif->id] = hw; 1234 } 1235 1236 /* TODO: use the same max_freq as in dpu_kms_hw_init */ 1237 max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core"); 1238 if (!max_core_clk_rate) { 1239 DPU_DEBUG("max core clk rate not determined, using default\n"); 1240 max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE; 1241 } 1242 1243 rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate); 1244 if (rc) { 1245 DPU_ERROR("failed to init perf %d\n", rc); 1246 goto err_pm_put; 1247 } 1248 1249 /* 1250 * We need to program DP <-> PHY relationship only for SC8180X since it 1251 * has fewer DP controllers than DP PHYs. 1252 * If any other platform requires the same kind of programming, or if 1253 * the INTF <->DP relationship isn't static anymore, this needs to be 1254 * configured through the DT. 1255 */ 1256 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu")) 1257 dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, }); 1258 1259 dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog); 1260 if (IS_ERR(dpu_kms->hw_intr)) { 1261 rc = PTR_ERR(dpu_kms->hw_intr); 1262 DPU_ERROR("hw_intr init failed: %d\n", rc); 1263 dpu_kms->hw_intr = NULL; 1264 goto err_pm_put; 1265 } 1266 1267 dev->mode_config.min_width = 0; 1268 dev->mode_config.min_height = 0; 1269 1270 dev->mode_config.max_width = DPU_MAX_IMG_WIDTH; 1271 dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT; 1272 1273 dev->max_vblank_count = 0xffffffff; 1274 /* Disable vblank irqs aggressively for power-saving */ 1275 dev->vblank_disable_immediate = true; 1276 1277 /* 1278 * _dpu_kms_drm_obj_init should create the DRM related objects 1279 * i.e. CRTCs, planes, encoders, connectors and so forth 1280 */ 1281 rc = _dpu_kms_drm_obj_init(dpu_kms); 1282 if (rc) { 1283 DPU_ERROR("modeset init failed: %d\n", rc); 1284 goto err_pm_put; 1285 } 1286 1287 dpu_vbif_init_memtypes(dpu_kms); 1288 1289 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1290 1291 return 0; 1292 1293 err_pm_put: 1294 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1295 error: 1296 _dpu_kms_hw_destroy(dpu_kms); 1297 1298 return rc; 1299 } 1300 1301 static int dpu_kms_init(struct drm_device *ddev) 1302 { 1303 struct msm_drm_private *priv = ddev->dev_private; 1304 struct device *dev = ddev->dev; 1305 struct platform_device *pdev = to_platform_device(dev); 1306 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1307 struct dev_pm_opp *opp; 1308 int ret = 0; 1309 unsigned long max_freq = ULONG_MAX; 1310 1311 opp = dev_pm_opp_find_freq_floor(dev, &max_freq); 1312 if (!IS_ERR(opp)) 1313 dev_pm_opp_put(opp); 1314 1315 dev_pm_opp_set_rate(dev, max_freq); 1316 1317 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); 1318 if (ret) { 1319 DPU_ERROR("failed to init kms, ret=%d\n", ret); 1320 return ret; 1321 } 1322 dpu_kms->dev = ddev; 1323 1324 pm_runtime_enable(&pdev->dev); 1325 dpu_kms->rpm_enabled = true; 1326 1327 return 0; 1328 } 1329 1330 static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms) 1331 { 1332 struct platform_device *pdev = dpu_kms->pdev; 1333 struct platform_device *mdss_dev; 1334 int ret; 1335 1336 if (!dev_is_platform(dpu_kms->pdev->dev.parent)) 1337 return -EINVAL; 1338 1339 mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent); 1340 1341 dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys"); 1342 if (IS_ERR(dpu_kms->mmio)) { 1343 ret = PTR_ERR(dpu_kms->mmio); 1344 DPU_ERROR("mdp register memory map failed: %d\n", ret); 1345 dpu_kms->mmio = NULL; 1346 return ret; 1347 } 1348 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1349 1350 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, 1351 dpu_kms->pdev, 1352 "vbif_phys"); 1353 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1354 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1355 DPU_ERROR("vbif register memory map failed: %d\n", ret); 1356 dpu_kms->vbif[VBIF_RT] = NULL; 1357 return ret; 1358 } 1359 1360 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev, 1361 dpu_kms->pdev, 1362 "vbif_nrt_phys"); 1363 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1364 dpu_kms->vbif[VBIF_NRT] = NULL; 1365 DPU_DEBUG("VBIF NRT is not defined"); 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms) 1372 { 1373 struct platform_device *pdev = dpu_kms->pdev; 1374 int ret; 1375 1376 dpu_kms->mmio = msm_ioremap(pdev, "mdp"); 1377 if (IS_ERR(dpu_kms->mmio)) { 1378 ret = PTR_ERR(dpu_kms->mmio); 1379 DPU_ERROR("mdp register memory map failed: %d\n", ret); 1380 dpu_kms->mmio = NULL; 1381 return ret; 1382 } 1383 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1384 1385 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); 1386 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { 1387 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); 1388 DPU_ERROR("vbif register memory map failed: %d\n", ret); 1389 dpu_kms->vbif[VBIF_RT] = NULL; 1390 return ret; 1391 } 1392 1393 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); 1394 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { 1395 dpu_kms->vbif[VBIF_NRT] = NULL; 1396 DPU_DEBUG("VBIF NRT is not defined"); 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int dpu_dev_probe(struct platform_device *pdev) 1403 { 1404 struct device *dev = &pdev->dev; 1405 struct dpu_kms *dpu_kms; 1406 int irq; 1407 int ret = 0; 1408 1409 if (!msm_disp_drv_should_bind(&pdev->dev, true)) 1410 return -ENODEV; 1411 1412 dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL); 1413 if (!dpu_kms) 1414 return -ENOMEM; 1415 1416 dpu_kms->pdev = pdev; 1417 1418 ret = devm_pm_opp_set_clkname(dev, "core"); 1419 if (ret) 1420 return ret; 1421 /* OPP table is optional */ 1422 ret = devm_pm_opp_of_add_table(dev); 1423 if (ret && ret != -ENODEV) 1424 return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); 1425 1426 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); 1427 if (ret < 0) 1428 return dev_err_probe(dev, ret, "failed to parse clocks\n"); 1429 1430 dpu_kms->num_clocks = ret; 1431 1432 irq = platform_get_irq(pdev, 0); 1433 if (irq < 0) 1434 return dev_err_probe(dev, irq, "failed to get irq\n"); 1435 1436 dpu_kms->base.irq = irq; 1437 1438 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5")) 1439 ret = dpu_kms_mmap_mdp5(dpu_kms); 1440 else 1441 ret = dpu_kms_mmap_dpu(dpu_kms); 1442 if (ret) 1443 return ret; 1444 1445 ret = dpu_kms_parse_data_bus_icc_path(dpu_kms); 1446 if (ret) 1447 return ret; 1448 1449 return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base); 1450 } 1451 1452 static void dpu_dev_remove(struct platform_device *pdev) 1453 { 1454 component_master_del(&pdev->dev, &msm_drm_ops); 1455 } 1456 1457 static int __maybe_unused dpu_runtime_suspend(struct device *dev) 1458 { 1459 int i; 1460 struct platform_device *pdev = to_platform_device(dev); 1461 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1462 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1463 1464 /* Drop the performance state vote */ 1465 dev_pm_opp_set_rate(dev, 0); 1466 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); 1467 1468 for (i = 0; i < dpu_kms->num_paths; i++) 1469 icc_set_bw(dpu_kms->path[i], 0, 0); 1470 1471 return 0; 1472 } 1473 1474 static int __maybe_unused dpu_runtime_resume(struct device *dev) 1475 { 1476 int rc = -1; 1477 struct platform_device *pdev = to_platform_device(dev); 1478 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1479 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1480 struct drm_encoder *encoder; 1481 struct drm_device *ddev; 1482 1483 ddev = dpu_kms->dev; 1484 1485 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); 1486 if (rc) { 1487 DPU_ERROR("clock enable failed rc:%d\n", rc); 1488 return rc; 1489 } 1490 1491 dpu_vbif_init_memtypes(dpu_kms); 1492 1493 drm_for_each_encoder(encoder, ddev) 1494 dpu_encoder_virt_runtime_resume(encoder); 1495 1496 return rc; 1497 } 1498 1499 static const struct dev_pm_ops dpu_pm_ops = { 1500 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL) 1501 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1502 pm_runtime_force_resume) 1503 .prepare = msm_kms_pm_prepare, 1504 .complete = msm_kms_pm_complete, 1505 }; 1506 1507 static const struct of_device_id dpu_dt_match[] = { 1508 { .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, }, 1509 { .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, }, 1510 { .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, }, 1511 { .compatible = "qcom,msm8996-mdp5", .data = &dpu_msm8996_cfg, }, 1512 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, 1513 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, 1514 { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, }, 1515 { .compatible = "qcom,sar2130p-dpu", .data = &dpu_sar2130p_cfg, }, 1516 { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, }, 1517 { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, }, 1518 { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, 1519 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, 1520 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, 1521 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, 1522 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, 1523 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, 1524 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, 1525 { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, }, 1526 { .compatible = "qcom,sm6150-dpu", .data = &dpu_sm6150_cfg, }, 1527 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, }, 1528 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, }, 1529 { .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, }, 1530 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, 1531 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, }, 1532 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, }, 1533 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, }, 1534 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, }, 1535 { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, }, 1536 { .compatible = "qcom,sm8750-dpu", .data = &dpu_sm8750_cfg, }, 1537 { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, }, 1538 {} 1539 }; 1540 MODULE_DEVICE_TABLE(of, dpu_dt_match); 1541 1542 static struct platform_driver dpu_driver = { 1543 .probe = dpu_dev_probe, 1544 .remove = dpu_dev_remove, 1545 .shutdown = msm_kms_shutdown, 1546 .driver = { 1547 .name = "msm_dpu", 1548 .of_match_table = dpu_dt_match, 1549 .pm = &dpu_pm_ops, 1550 }, 1551 }; 1552 1553 void __init msm_dpu_register(void) 1554 { 1555 platform_driver_register(&dpu_driver); 1556 } 1557 1558 void __exit msm_dpu_unregister(void) 1559 { 1560 platform_driver_unregister(&dpu_driver); 1561 } 1562