1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DPU_HW_UTIL_H 7 #define _DPU_HW_UTIL_H 8 9 #include <linux/io.h> 10 #include <linux/slab.h> 11 #include "dpu_hw_mdss.h" 12 13 #define REG_MASK(n) ((BIT(n)) - 1) 14 15 /* 16 * This is the common struct maintained by each sub block 17 * for mapping the register offsets in this block to the 18 * absoulute IO address 19 * @base_off: mdp register mapped offset 20 * @blk_off: pipe offset relative to mdss offset 21 * @length length of register block offset 22 * @xin_id xin id 23 * @hwversion mdss hw version number 24 */ 25 struct dpu_hw_blk_reg_map { 26 void __iomem *base_off; 27 u32 blk_off; 28 u32 length; 29 u32 xin_id; 30 u32 hwversion; 31 u32 log_mask; 32 }; 33 34 /** 35 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration 36 * @enable: detail enhancer enable/disable 37 * @sharpen_level1: sharpening strength for noise 38 * @sharpen_level2: sharpening strength for signal 39 * @ clip: clip shift 40 * @ limit: limit value 41 * @ thr_quiet: quiet threshold 42 * @ thr_dieout: dieout threshold 43 * @ thr_high: low threshold 44 * @ thr_high: high threshold 45 * @ prec_shift: precision shift 46 * @ adjust_a: A-coefficients for mapping curve 47 * @ adjust_b: B-coefficients for mapping curve 48 * @ adjust_c: C-coefficients for mapping curve 49 */ 50 struct dpu_hw_scaler3_de_cfg { 51 u32 enable; 52 int16_t sharpen_level1; 53 int16_t sharpen_level2; 54 uint16_t clip; 55 uint16_t limit; 56 uint16_t thr_quiet; 57 uint16_t thr_dieout; 58 uint16_t thr_low; 59 uint16_t thr_high; 60 uint16_t prec_shift; 61 int16_t adjust_a[DPU_MAX_DE_CURVES]; 62 int16_t adjust_b[DPU_MAX_DE_CURVES]; 63 int16_t adjust_c[DPU_MAX_DE_CURVES]; 64 }; 65 66 67 /** 68 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration 69 * @enable: scaler enable 70 * @dir_en: direction detection block enable 71 * @ init_phase_x: horizontal initial phase 72 * @ phase_step_x: horizontal phase step 73 * @ init_phase_y: vertical initial phase 74 * @ phase_step_y: vertical phase step 75 * @ preload_x: horizontal preload value 76 * @ preload_y: vertical preload value 77 * @ src_width: source width 78 * @ src_height: source height 79 * @ dst_width: destination width 80 * @ dst_height: destination height 81 * @ y_rgb_filter_cfg: y/rgb plane filter configuration 82 * @ uv_filter_cfg: uv plane filter configuration 83 * @ alpha_filter_cfg: alpha filter configuration 84 * @ blend_cfg: blend coefficients configuration 85 * @ lut_flag: scaler LUT update flags 86 * 0x1 swap LUT bank 87 * 0x2 update 2D filter LUT 88 * 0x4 update y circular filter LUT 89 * 0x8 update uv circular filter LUT 90 * 0x10 update y separable filter LUT 91 * 0x20 update uv separable filter LUT 92 * @ dir_lut_idx: 2D filter LUT index 93 * @ y_rgb_cir_lut_idx: y circular filter LUT index 94 * @ uv_cir_lut_idx: uv circular filter LUT index 95 * @ y_rgb_sep_lut_idx: y circular filter LUT index 96 * @ uv_sep_lut_idx: uv separable filter LUT index 97 * @ dir_lut: pointer to 2D LUT 98 * @ cir_lut: pointer to circular filter LUT 99 * @ sep_lut: pointer to separable filter LUT 100 * @ de: detail enhancer configuration 101 * @ dir_weight: Directional weight 102 */ 103 struct dpu_hw_scaler3_cfg { 104 u32 enable; 105 u32 dir_en; 106 int32_t init_phase_x[DPU_MAX_PLANES]; 107 int32_t phase_step_x[DPU_MAX_PLANES]; 108 int32_t init_phase_y[DPU_MAX_PLANES]; 109 int32_t phase_step_y[DPU_MAX_PLANES]; 110 111 u32 preload_x[DPU_MAX_PLANES]; 112 u32 preload_y[DPU_MAX_PLANES]; 113 u32 src_width[DPU_MAX_PLANES]; 114 u32 src_height[DPU_MAX_PLANES]; 115 116 u32 dst_width; 117 u32 dst_height; 118 119 u32 y_rgb_filter_cfg; 120 u32 uv_filter_cfg; 121 u32 alpha_filter_cfg; 122 u32 blend_cfg; 123 124 u32 lut_flag; 125 u32 dir_lut_idx; 126 127 u32 y_rgb_cir_lut_idx; 128 u32 uv_cir_lut_idx; 129 u32 y_rgb_sep_lut_idx; 130 u32 uv_sep_lut_idx; 131 u32 *dir_lut; 132 size_t dir_len; 133 u32 *cir_lut; 134 size_t cir_len; 135 u32 *sep_lut; 136 size_t sep_len; 137 138 /* 139 * Detail enhancer settings 140 */ 141 struct dpu_hw_scaler3_de_cfg de; 142 143 u32 dir_weight; 144 }; 145 146 /** 147 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure 148 * @num_ext_pxls_lr: Number of total horizontal pixels 149 * @num_ext_pxls_tb: Number of total vertical lines 150 * @left_ftch: Number of extra pixels to overfetch from left 151 * @right_ftch: Number of extra pixels to overfetch from right 152 * @top_ftch: Number of extra lines to overfetch from top 153 * @btm_ftch: Number of extra lines to overfetch from bottom 154 * @left_rpt: Number of extra pixels to repeat from left 155 * @right_rpt: Number of extra pixels to repeat from right 156 * @top_rpt: Number of extra lines to repeat from top 157 * @btm_rpt: Number of extra lines to repeat from bottom 158 */ 159 struct dpu_drm_pix_ext_v1 { 160 /* 161 * Number of pixels ext in left, right, top and bottom direction 162 * for all color components. 163 */ 164 int32_t num_ext_pxls_lr[DPU_MAX_PLANES]; 165 int32_t num_ext_pxls_tb[DPU_MAX_PLANES]; 166 167 /* 168 * Number of pixels needs to be overfetched in left, right, top 169 * and bottom directions from source image for scaling. 170 */ 171 int32_t left_ftch[DPU_MAX_PLANES]; 172 int32_t right_ftch[DPU_MAX_PLANES]; 173 int32_t top_ftch[DPU_MAX_PLANES]; 174 int32_t btm_ftch[DPU_MAX_PLANES]; 175 /* 176 * Number of pixels needs to be repeated in left, right, top and 177 * bottom directions for scaling. 178 */ 179 int32_t left_rpt[DPU_MAX_PLANES]; 180 int32_t right_rpt[DPU_MAX_PLANES]; 181 int32_t top_rpt[DPU_MAX_PLANES]; 182 int32_t btm_rpt[DPU_MAX_PLANES]; 183 184 }; 185 186 /** 187 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure 188 * @enable: Enables/disables detail enhancer 189 * @sharpen_level1: Sharpening strength for noise 190 * @sharpen_level2: Sharpening strength for context 191 * @clip: Clip coefficient 192 * @limit: Detail enhancer limit factor 193 * @thr_quiet: Quite zone threshold 194 * @thr_dieout: Die-out zone threshold 195 * @thr_low: Linear zone left threshold 196 * @thr_high: Linear zone right threshold 197 * @prec_shift: Detail enhancer precision 198 * @adjust_a: Mapping curves A coefficients 199 * @adjust_b: Mapping curves B coefficients 200 * @adjust_c: Mapping curves C coefficients 201 */ 202 struct dpu_drm_de_v1 { 203 uint32_t enable; 204 int16_t sharpen_level1; 205 int16_t sharpen_level2; 206 uint16_t clip; 207 uint16_t limit; 208 uint16_t thr_quiet; 209 uint16_t thr_dieout; 210 uint16_t thr_low; 211 uint16_t thr_high; 212 uint16_t prec_shift; 213 int16_t adjust_a[DPU_MAX_DE_CURVES]; 214 int16_t adjust_b[DPU_MAX_DE_CURVES]; 215 int16_t adjust_c[DPU_MAX_DE_CURVES]; 216 }; 217 218 /** 219 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler 220 * @enable: Scaler enable 221 * @dir_en: Detail enhancer enable 222 * @pe: Pixel extension settings 223 * @horz_decimate: Horizontal decimation factor 224 * @vert_decimate: Vertical decimation factor 225 * @init_phase_x: Initial scaler phase values for x 226 * @phase_step_x: Phase step values for x 227 * @init_phase_y: Initial scaler phase values for y 228 * @phase_step_y: Phase step values for y 229 * @preload_x: Horizontal preload value 230 * @preload_y: Vertical preload value 231 * @src_width: Source width 232 * @src_height: Source height 233 * @dst_width: Destination width 234 * @dst_height: Destination height 235 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 236 * @uv_filter_cfg: UV plane filter configuration 237 * @alpha_filter_cfg: Alpha filter configuration 238 * @blend_cfg: Selection of blend coefficients 239 * @lut_flag: LUT configuration flags 240 * @dir_lut_idx: 2d 4x4 LUT index 241 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 242 * @uv_cir_lut_idx: UV circular LUT index 243 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 244 * @uv_sep_lut_idx: UV separable LUT index 245 * @de: Detail enhancer settings 246 */ 247 struct dpu_drm_scaler_v2 { 248 /* 249 * General definitions 250 */ 251 uint32_t enable; 252 uint32_t dir_en; 253 254 /* 255 * Pix ext settings 256 */ 257 struct dpu_drm_pix_ext_v1 pe; 258 259 /* 260 * Decimation settings 261 */ 262 uint32_t horz_decimate; 263 uint32_t vert_decimate; 264 265 /* 266 * Phase settings 267 */ 268 int32_t init_phase_x[DPU_MAX_PLANES]; 269 int32_t phase_step_x[DPU_MAX_PLANES]; 270 int32_t init_phase_y[DPU_MAX_PLANES]; 271 int32_t phase_step_y[DPU_MAX_PLANES]; 272 273 uint32_t preload_x[DPU_MAX_PLANES]; 274 uint32_t preload_y[DPU_MAX_PLANES]; 275 uint32_t src_width[DPU_MAX_PLANES]; 276 uint32_t src_height[DPU_MAX_PLANES]; 277 278 uint32_t dst_width; 279 uint32_t dst_height; 280 281 uint32_t y_rgb_filter_cfg; 282 uint32_t uv_filter_cfg; 283 uint32_t alpha_filter_cfg; 284 uint32_t blend_cfg; 285 286 uint32_t lut_flag; 287 uint32_t dir_lut_idx; 288 289 /* for Y(RGB) and UV planes*/ 290 uint32_t y_rgb_cir_lut_idx; 291 uint32_t uv_cir_lut_idx; 292 uint32_t y_rgb_sep_lut_idx; 293 uint32_t uv_sep_lut_idx; 294 295 /* 296 * Detail enhancer settings 297 */ 298 struct dpu_drm_de_v1 de; 299 }; 300 301 302 u32 *dpu_hw_util_get_log_mask_ptr(void); 303 304 void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 305 u32 reg_off, 306 u32 val, 307 const char *name); 308 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); 309 310 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) 311 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) 312 313 void *dpu_hw_util_get_dir(void); 314 315 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 316 struct dpu_hw_scaler3_cfg *scaler3_cfg, 317 u32 scaler_offset, u32 scaler_version, 318 const struct dpu_format *format); 319 320 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 321 u32 scaler_offset); 322 323 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 324 u32 csc_reg_off, 325 const struct dpu_csc_cfg *data, bool csc10); 326 327 #endif /* _DPU_HW_UTIL_H */ 328