1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_SSPP_H 6 #define _DPU_HW_SSPP_H 7 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_formats.h" 12 13 struct dpu_hw_sspp; 14 15 #define DPU_SSPP_MAX_PITCH_SIZE 0xffff 16 17 /** 18 * Flags 19 */ 20 #define DPU_SSPP_FLIP_LR BIT(0) 21 #define DPU_SSPP_FLIP_UD BIT(1) 22 #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) 23 #define DPU_SSPP_ROT_90 BIT(3) 24 #define DPU_SSPP_SOLID_FILL BIT(4) 25 26 /** 27 * Component indices 28 */ 29 enum { 30 DPU_SSPP_COMP_0, 31 DPU_SSPP_COMP_1_2, 32 DPU_SSPP_COMP_2, 33 DPU_SSPP_COMP_3, 34 35 DPU_SSPP_COMP_MAX 36 }; 37 38 /** 39 * DPU_SSPP_RECT_SOLO - multirect disabled 40 * DPU_SSPP_RECT_0 - rect0 of a multirect pipe 41 * DPU_SSPP_RECT_1 - rect1 of a multirect pipe 42 * 43 * Note: HW supports multirect with either RECT0 or 44 * RECT1. Considering no benefit of such configs over 45 * SOLO mode and to keep the plane management simple, 46 * we dont support single rect multirect configs. 47 */ 48 enum dpu_sspp_multirect_index { 49 DPU_SSPP_RECT_SOLO = 0, 50 DPU_SSPP_RECT_0, 51 DPU_SSPP_RECT_1, 52 }; 53 54 enum dpu_sspp_multirect_mode { 55 DPU_SSPP_MULTIRECT_NONE = 0, 56 DPU_SSPP_MULTIRECT_PARALLEL, 57 DPU_SSPP_MULTIRECT_TIME_MX, 58 }; 59 60 enum { 61 DPU_FRAME_LINEAR, 62 DPU_FRAME_TILE_A4X, 63 DPU_FRAME_TILE_A5X, 64 }; 65 66 enum dpu_hw_filter { 67 DPU_SCALE_FILTER_NEAREST = 0, 68 DPU_SCALE_FILTER_BIL, 69 DPU_SCALE_FILTER_PCMN, 70 DPU_SCALE_FILTER_CA, 71 DPU_SCALE_FILTER_MAX 72 }; 73 74 enum dpu_hw_filter_alpa { 75 DPU_SCALE_ALPHA_PIXEL_REP, 76 DPU_SCALE_ALPHA_BIL 77 }; 78 79 enum dpu_hw_filter_yuv { 80 DPU_SCALE_2D_4X4, 81 DPU_SCALE_2D_CIR, 82 DPU_SCALE_1D_SEP, 83 DPU_SCALE_BIL 84 }; 85 86 struct dpu_hw_sharp_cfg { 87 u32 strength; 88 u32 edge_thr; 89 u32 smooth_thr; 90 u32 noise_thr; 91 }; 92 93 struct dpu_hw_pixel_ext { 94 /* scaling factors are enabled for this input layer */ 95 uint8_t enable_pxl_ext; 96 97 int init_phase_x[DPU_MAX_PLANES]; 98 int phase_step_x[DPU_MAX_PLANES]; 99 int init_phase_y[DPU_MAX_PLANES]; 100 int phase_step_y[DPU_MAX_PLANES]; 101 102 /* 103 * Number of pixels extension in left, right, top and bottom direction 104 * for all color components. This pixel value for each color component 105 * should be sum of fetch + repeat pixels. 106 */ 107 int num_ext_pxls_left[DPU_MAX_PLANES]; 108 int num_ext_pxls_right[DPU_MAX_PLANES]; 109 int num_ext_pxls_top[DPU_MAX_PLANES]; 110 int num_ext_pxls_btm[DPU_MAX_PLANES]; 111 112 /* 113 * Number of pixels needs to be overfetched in left, right, top and 114 * bottom directions from source image for scaling. 115 */ 116 int left_ftch[DPU_MAX_PLANES]; 117 int right_ftch[DPU_MAX_PLANES]; 118 int top_ftch[DPU_MAX_PLANES]; 119 int btm_ftch[DPU_MAX_PLANES]; 120 121 /* 122 * Number of pixels needs to be repeated in left, right, top and 123 * bottom directions for scaling. 124 */ 125 int left_rpt[DPU_MAX_PLANES]; 126 int right_rpt[DPU_MAX_PLANES]; 127 int top_rpt[DPU_MAX_PLANES]; 128 int btm_rpt[DPU_MAX_PLANES]; 129 130 uint32_t roi_w[DPU_MAX_PLANES]; 131 uint32_t roi_h[DPU_MAX_PLANES]; 132 133 /* 134 * Filter type to be used for scaling in horizontal and vertical 135 * directions 136 */ 137 enum dpu_hw_filter horz_filter[DPU_MAX_PLANES]; 138 enum dpu_hw_filter vert_filter[DPU_MAX_PLANES]; 139 140 }; 141 142 /** 143 * struct dpu_sw_pipe_cfg : software pipe configuration 144 * @src_rect: src ROI, caller takes into account the different operations 145 * such as decimation, flip etc to program this field 146 * @dest_rect: destination ROI. 147 * @rotation: simplified drm rotation hint 148 */ 149 struct dpu_sw_pipe_cfg { 150 struct drm_rect src_rect; 151 struct drm_rect dst_rect; 152 unsigned int rotation; 153 }; 154 155 /** 156 * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration 157 * @size: size to prefill in bytes, or zero to disable 158 * @time: time to prefill in usec, or zero to disable 159 */ 160 struct dpu_hw_pipe_ts_cfg { 161 u64 size; 162 u64 time; 163 }; 164 165 /** 166 * struct dpu_sw_pipe - software pipe description 167 * @sspp: backing SSPP pipe 168 * @index: index of the rectangle of SSPP 169 * @mode: parallel or time multiplex multirect mode 170 */ 171 struct dpu_sw_pipe { 172 struct dpu_hw_sspp *sspp; 173 enum dpu_sspp_multirect_index multirect_index; 174 enum dpu_sspp_multirect_mode multirect_mode; 175 }; 176 177 /** 178 * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions 179 * Caller must call the init function to get the pipe context for each pipe 180 * Assumption is these functions will be called after clocks are enabled 181 */ 182 struct dpu_hw_sspp_ops { 183 /** 184 * setup_format - setup pixel format cropping rectangle, flip 185 * @pipe: Pointer to software pipe context 186 * @cfg: Pointer to pipe config structure 187 * @flags: Extra flags for format config 188 */ 189 void (*setup_format)(struct dpu_sw_pipe *pipe, 190 const struct msm_format *fmt, u32 flags); 191 192 /** 193 * setup_rects - setup pipe ROI rectangles 194 * @pipe: Pointer to software pipe context 195 * @cfg: Pointer to pipe config structure 196 */ 197 void (*setup_rects)(struct dpu_sw_pipe *pipe, 198 struct dpu_sw_pipe_cfg *cfg); 199 200 /** 201 * setup_pe - setup pipe pixel extension 202 * @ctx: Pointer to pipe context 203 * @pe_ext: Pointer to pixel ext settings 204 */ 205 void (*setup_pe)(struct dpu_hw_sspp *ctx, 206 struct dpu_hw_pixel_ext *pe_ext); 207 208 /** 209 * setup_sourceaddress - setup pipe source addresses 210 * @pipe: Pointer to software pipe context 211 * @layout: format layout information for programming buffer to hardware 212 */ 213 void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, 214 struct dpu_hw_fmt_layout *layout); 215 216 /** 217 * setup_csc - setup color space coversion 218 * @ctx: Pointer to pipe context 219 * @data: Pointer to config structure 220 */ 221 void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data); 222 223 /** 224 * setup_solidfill - enable/disable colorfill 225 * @pipe: Pointer to software pipe context 226 * @const_color: Fill color value 227 * @flags: Pipe flags 228 */ 229 void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color); 230 231 /** 232 * setup_multirect - setup multirect configuration 233 * @pipe: Pointer to software pipe context 234 */ 235 236 void (*setup_multirect)(struct dpu_sw_pipe *pipe); 237 238 /** 239 * setup_sharpening - setup sharpening 240 * @ctx: Pointer to pipe context 241 * @cfg: Pointer to config structure 242 */ 243 void (*setup_sharpening)(struct dpu_hw_sspp *ctx, 244 struct dpu_hw_sharp_cfg *cfg); 245 246 247 /** 248 * setup_qos_lut - setup QoS LUTs 249 * @ctx: Pointer to pipe context 250 * @cfg: LUT configuration 251 */ 252 void (*setup_qos_lut)(struct dpu_hw_sspp *ctx, 253 struct dpu_hw_qos_cfg *cfg); 254 255 /** 256 * setup_qos_ctrl - setup QoS control 257 * @ctx: Pointer to pipe context 258 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT 259 */ 260 void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, 261 bool danger_safe_en); 262 263 /** 264 * setup_clk_force_ctrl - setup clock force control 265 * @ctx: Pointer to pipe context 266 * @enable: enable clock force if true 267 */ 268 bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx, 269 bool enable); 270 271 /** 272 * setup_histogram - setup histograms 273 * @ctx: Pointer to pipe context 274 * @cfg: Pointer to histogram configuration 275 */ 276 void (*setup_histogram)(struct dpu_hw_sspp *ctx, 277 void *cfg); 278 279 /** 280 * setup_scaler - setup scaler 281 * @scaler3_cfg: Pointer to scaler configuration 282 * @format: pixel format parameters 283 */ 284 void (*setup_scaler)(struct dpu_hw_sspp *ctx, 285 struct dpu_hw_scaler3_cfg *scaler3_cfg, 286 const struct msm_format *format); 287 288 /** 289 * setup_cdp - setup client driven prefetch 290 * @pipe: Pointer to software pipe context 291 * @fmt: format used by the sw pipe 292 * @enable: whether the CDP should be enabled for this pipe 293 */ 294 void (*setup_cdp)(struct dpu_sw_pipe *pipe, 295 const struct msm_format *fmt, 296 bool enable); 297 }; 298 299 /** 300 * struct dpu_hw_sspp - pipe description 301 * @base: hardware block base structure 302 * @hw: block hardware details 303 * @ubwc: UBWC configuration data 304 * @idx: pipe index 305 * @cap: pointer to layer_cfg 306 * @ops: pointer to operations possible for this pipe 307 */ 308 struct dpu_hw_sspp { 309 struct dpu_hw_blk base; 310 struct dpu_hw_blk_reg_map hw; 311 const struct msm_mdss_data *ubwc; 312 313 /* Pipe */ 314 enum dpu_sspp idx; 315 const struct dpu_sspp_cfg *cap; 316 317 /* Ops */ 318 struct dpu_hw_sspp_ops ops; 319 }; 320 321 struct dpu_kms; 322 323 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, 324 const struct dpu_sspp_cfg *cfg, 325 void __iomem *addr, 326 const struct msm_mdss_data *mdss_data, 327 const struct dpu_mdss_version *mdss_rev); 328 329 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 330 struct dentry *entry); 331 332 #endif /*_DPU_HW_SSPP_H */ 333 334