1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include "dpu_hwio.h" 6 #include "dpu_hw_catalog.h" 7 #include "dpu_hw_lm.h" 8 #include "dpu_hw_sspp.h" 9 #include "dpu_kms.h" 10 11 #include "msm_mdss.h" 12 13 #include <drm/drm_file.h> 14 15 #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 16 17 /* SSPP registers */ 18 #define SSPP_SRC_SIZE 0x00 19 #define SSPP_SRC_XY 0x08 20 #define SSPP_OUT_SIZE 0x0c 21 #define SSPP_OUT_XY 0x10 22 #define SSPP_SRC0_ADDR 0x14 23 #define SSPP_SRC1_ADDR 0x18 24 #define SSPP_SRC2_ADDR 0x1C 25 #define SSPP_SRC3_ADDR 0x20 26 #define SSPP_SRC_YSTRIDE0 0x24 27 #define SSPP_SRC_YSTRIDE1 0x28 28 #define SSPP_SRC_FORMAT 0x30 29 #define SSPP_SRC_UNPACK_PATTERN 0x34 30 #define SSPP_SRC_OP_MODE 0x38 31 #define SSPP_SRC_CONSTANT_COLOR 0x3c 32 #define SSPP_EXCL_REC_CTL 0x40 33 #define SSPP_UBWC_STATIC_CTRL 0x44 34 #define SSPP_FETCH_CONFIG 0x48 35 #define SSPP_DANGER_LUT 0x60 36 #define SSPP_SAFE_LUT 0x64 37 #define SSPP_CREQ_LUT 0x68 38 #define SSPP_QOS_CTRL 0x6C 39 #define SSPP_SRC_ADDR_SW_STATUS 0x70 40 #define SSPP_CREQ_LUT_0 0x74 41 #define SSPP_CREQ_LUT_1 0x78 42 #define SSPP_DECIMATION_CONFIG 0xB4 43 #define SSPP_SW_PIX_EXT_C0_LR 0x100 44 #define SSPP_SW_PIX_EXT_C0_TB 0x104 45 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 46 #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 47 #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 48 #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 49 #define SSPP_SW_PIX_EXT_C3_LR 0x120 50 #define SSPP_SW_PIX_EXT_C3_TB 0x124 51 #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 52 #define SSPP_TRAFFIC_SHAPER 0x130 53 #define SSPP_CDP_CNTL 0x134 54 #define SSPP_UBWC_ERROR_STATUS 0x138 55 #define SSPP_CDP_CNTL_REC1 0x13c 56 #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 57 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 58 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 59 #define SSPP_OUT_SIZE_REC1 0x160 60 #define SSPP_OUT_XY_REC1 0x164 61 #define SSPP_SRC_XY_REC1 0x168 62 #define SSPP_SRC_SIZE_REC1 0x16C 63 #define SSPP_MULTIRECT_OPMODE 0x170 64 #define SSPP_SRC_FORMAT_REC1 0x174 65 #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 66 #define SSPP_SRC_OP_MODE_REC1 0x17C 67 #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 68 #define SSPP_EXCL_REC_SIZE_REC1 0x184 69 #define SSPP_EXCL_REC_XY_REC1 0x188 70 #define SSPP_EXCL_REC_SIZE 0x1B4 71 #define SSPP_EXCL_REC_XY 0x1B8 72 73 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ 74 #define MDSS_MDP_OP_DEINTERLACE BIT(22) 75 #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) 76 #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) 77 #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) 78 #define MDSS_MDP_OP_IGC_EN BIT(16) 79 #define MDSS_MDP_OP_FLIP_UD BIT(14) 80 #define MDSS_MDP_OP_FLIP_LR BIT(13) 81 #define MDSS_MDP_OP_BWC_EN BIT(0) 82 #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) 83 #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) 84 #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) 85 #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) 86 87 /* SSPP_QOS_CTRL */ 88 #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) 89 #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) 90 #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 91 #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 92 #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 93 #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 94 95 /* DPU_SSPP_SCALER_QSEED2 */ 96 #define SSPP_VIG_OP_MODE 0x0 97 #define SCALE_CONFIG 0x04 98 #define COMP0_3_PHASE_STEP_X 0x10 99 #define COMP0_3_PHASE_STEP_Y 0x14 100 #define COMP1_2_PHASE_STEP_X 0x18 101 #define COMP1_2_PHASE_STEP_Y 0x1c 102 #define COMP0_3_INIT_PHASE_X 0x20 103 #define COMP0_3_INIT_PHASE_Y 0x24 104 #define COMP1_2_INIT_PHASE_X 0x28 105 #define COMP1_2_INIT_PHASE_Y 0x2C 106 #define VIG_0_QSEED2_SHARP 0x30 107 108 /* SSPP_TRAFFIC_SHAPER and _REC1 */ 109 #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF 110 111 /* 112 * Definitions for ViG op modes 113 */ 114 #define VIG_OP_CSC_DST_DATAFMT BIT(19) 115 #define VIG_OP_CSC_SRC_DATAFMT BIT(18) 116 #define VIG_OP_CSC_EN BIT(17) 117 #define VIG_OP_MEM_PROT_CONT BIT(15) 118 #define VIG_OP_MEM_PROT_VAL BIT(14) 119 #define VIG_OP_MEM_PROT_SAT BIT(13) 120 #define VIG_OP_MEM_PROT_HUE BIT(12) 121 #define VIG_OP_HIST BIT(8) 122 #define VIG_OP_SKY_COL BIT(7) 123 #define VIG_OP_FOIL BIT(6) 124 #define VIG_OP_SKIN_COL BIT(5) 125 #define VIG_OP_PA_EN BIT(4) 126 #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) 127 #define VIG_OP_MEM_PROT_BLEND BIT(1) 128 129 /* 130 * Definitions for CSC 10 op modes 131 */ 132 #define SSPP_VIG_CSC_10_OP_MODE 0x0 133 #define VIG_CSC_10_SRC_DATAFMT BIT(1) 134 #define VIG_CSC_10_EN BIT(0) 135 #define CSC_10BIT_OFFSET 4 136 137 /* traffic shaper clock in Hz */ 138 #define TS_CLK 19200000 139 140 141 static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) 142 { 143 struct dpu_hw_sspp *ctx = pipe->sspp; 144 u32 mode_mask; 145 146 if (!ctx) 147 return; 148 149 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { 150 /** 151 * if rect index is RECT_SOLO, we cannot expect a 152 * virtual plane sharing the same SSPP id. So we go 153 * and disable multirect 154 */ 155 mode_mask = 0; 156 } else { 157 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); 158 mode_mask |= pipe->multirect_index; 159 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX) 160 mode_mask |= BIT(2); 161 else 162 mode_mask &= ~BIT(2); 163 } 164 165 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); 166 } 167 168 static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, 169 u32 mask, u8 en) 170 { 171 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; 172 u32 opmode; 173 174 if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || 175 !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 176 return; 177 178 opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE); 179 180 if (en) 181 opmode |= mask; 182 else 183 opmode &= ~mask; 184 185 DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); 186 } 187 188 static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, 189 u32 mask, u8 en) 190 { 191 const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; 192 u32 opmode; 193 194 opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE); 195 if (en) 196 opmode |= mask; 197 else 198 opmode &= ~mask; 199 200 DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode); 201 } 202 203 /* 204 * Setup source pixel format, flip, 205 */ 206 static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, 207 const struct dpu_format *fmt, u32 flags) 208 { 209 struct dpu_hw_sspp *ctx = pipe->sspp; 210 struct dpu_hw_blk_reg_map *c; 211 u32 chroma_samp, unpack, src_format; 212 u32 opmode = 0; 213 u32 fast_clear = 0; 214 u32 op_mode_off, unpack_pat_off, format_off; 215 216 if (!ctx || !fmt) 217 return; 218 219 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || 220 pipe->multirect_index == DPU_SSPP_RECT_0) { 221 op_mode_off = SSPP_SRC_OP_MODE; 222 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; 223 format_off = SSPP_SRC_FORMAT; 224 } else { 225 op_mode_off = SSPP_SRC_OP_MODE_REC1; 226 unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; 227 format_off = SSPP_SRC_FORMAT_REC1; 228 } 229 230 c = &ctx->hw; 231 opmode = DPU_REG_READ(c, op_mode_off); 232 opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | 233 MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); 234 235 if (flags & DPU_SSPP_FLIP_LR) 236 opmode |= MDSS_MDP_OP_FLIP_LR; 237 if (flags & DPU_SSPP_FLIP_UD) 238 opmode |= MDSS_MDP_OP_FLIP_UD; 239 240 chroma_samp = fmt->chroma_sample; 241 if (flags & DPU_SSPP_SOURCE_ROTATED_90) { 242 if (chroma_samp == DPU_CHROMA_H2V1) 243 chroma_samp = DPU_CHROMA_H1V2; 244 else if (chroma_samp == DPU_CHROMA_H1V2) 245 chroma_samp = DPU_CHROMA_H2V1; 246 } 247 248 src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | 249 (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | 250 (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); 251 252 if (flags & DPU_SSPP_ROT_90) 253 src_format |= BIT(11); /* ROT90 */ 254 255 if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) 256 src_format |= BIT(8); /* SRCC3_EN */ 257 258 if (flags & DPU_SSPP_SOLID_FILL) 259 src_format |= BIT(22); 260 261 unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | 262 (fmt->element[1] << 8) | (fmt->element[0] << 0); 263 src_format |= ((fmt->unpack_count - 1) << 12) | 264 (fmt->unpack_tight << 17) | 265 (fmt->unpack_align_msb << 18) | 266 ((fmt->bpp - 1) << 9); 267 268 if (fmt->fetch_mode != DPU_FETCH_LINEAR) { 269 if (DPU_FORMAT_IS_UBWC(fmt)) 270 opmode |= MDSS_MDP_OP_BWC_EN; 271 src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 272 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 273 DPU_FETCH_CONFIG_RESET_VALUE | 274 ctx->ubwc->highest_bank_bit << 18); 275 switch (ctx->ubwc->ubwc_enc_version) { 276 case UBWC_1_0: 277 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 278 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 279 fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | 280 BIT(8) | 281 (ctx->ubwc->highest_bank_bit << 4)); 282 break; 283 case UBWC_2_0: 284 fast_clear = fmt->alpha_enable ? BIT(31) : 0; 285 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 286 fast_clear | (ctx->ubwc->ubwc_swizzle) | 287 (ctx->ubwc->highest_bank_bit << 4)); 288 break; 289 case UBWC_3_0: 290 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 291 BIT(30) | (ctx->ubwc->ubwc_swizzle) | 292 (ctx->ubwc->highest_bank_bit << 4)); 293 break; 294 case UBWC_4_0: 295 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, 296 DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); 297 break; 298 } 299 } 300 301 opmode |= MDSS_MDP_OP_PE_OVERRIDE; 302 303 /* if this is YUV pixel format, enable CSC */ 304 if (DPU_FORMAT_IS_YUV(fmt)) 305 src_format |= BIT(15); 306 307 if (DPU_FORMAT_IS_DX(fmt)) 308 src_format |= BIT(14); 309 310 /* update scaler opmode, if appropriate */ 311 if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) 312 _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, 313 DPU_FORMAT_IS_YUV(fmt)); 314 else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) 315 _sspp_setup_csc10_opmode(ctx, 316 VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, 317 DPU_FORMAT_IS_YUV(fmt)); 318 319 DPU_REG_WRITE(c, format_off, src_format); 320 DPU_REG_WRITE(c, unpack_pat_off, unpack); 321 DPU_REG_WRITE(c, op_mode_off, opmode); 322 323 /* clear previous UBWC error */ 324 DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); 325 } 326 327 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, 328 struct dpu_hw_pixel_ext *pe_ext) 329 { 330 struct dpu_hw_blk_reg_map *c; 331 u8 color; 332 u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; 333 const u32 bytemask = 0xff; 334 const u32 shortmask = 0xffff; 335 336 if (!ctx || !pe_ext) 337 return; 338 339 c = &ctx->hw; 340 341 /* program SW pixel extension override for all pipes*/ 342 for (color = 0; color < DPU_MAX_PLANES; color++) { 343 /* color 2 has the same set of registers as color 1 */ 344 if (color == 2) 345 continue; 346 347 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| 348 ((pe_ext->right_rpt[color] & bytemask) << 16)| 349 ((pe_ext->left_ftch[color] & bytemask) << 8)| 350 (pe_ext->left_rpt[color] & bytemask); 351 352 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| 353 ((pe_ext->btm_rpt[color] & bytemask) << 16)| 354 ((pe_ext->top_ftch[color] & bytemask) << 8)| 355 (pe_ext->top_rpt[color] & bytemask); 356 357 tot_req_pixels[color] = (((pe_ext->roi_h[color] + 358 pe_ext->num_ext_pxls_top[color] + 359 pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | 360 ((pe_ext->roi_w[color] + 361 pe_ext->num_ext_pxls_left[color] + 362 pe_ext->num_ext_pxls_right[color]) & shortmask); 363 } 364 365 /* color 0 */ 366 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR, lr_pe[0]); 367 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB, tb_pe[0]); 368 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS, 369 tot_req_pixels[0]); 370 371 /* color 1 and color 2 */ 372 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR, lr_pe[1]); 373 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB, tb_pe[1]); 374 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS, 375 tot_req_pixels[1]); 376 377 /* color 3 */ 378 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR, lr_pe[3]); 379 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB, lr_pe[3]); 380 DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS, 381 tot_req_pixels[3]); 382 } 383 384 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, 385 struct dpu_hw_scaler3_cfg *scaler3_cfg, 386 const struct dpu_format *format) 387 { 388 if (!ctx || !scaler3_cfg) 389 return; 390 391 dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, 392 ctx->cap->sblk->scaler_blk.base, 393 ctx->cap->sblk->scaler_blk.version, 394 format); 395 } 396 397 static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) 398 { 399 if (!ctx) 400 return 0; 401 402 return dpu_hw_get_scaler3_ver(&ctx->hw, 403 ctx->cap->sblk->scaler_blk.base); 404 } 405 406 /* 407 * dpu_hw_sspp_setup_rects() 408 */ 409 static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, 410 struct dpu_sw_pipe_cfg *cfg) 411 { 412 struct dpu_hw_sspp *ctx = pipe->sspp; 413 struct dpu_hw_blk_reg_map *c; 414 u32 src_size, src_xy, dst_size, dst_xy; 415 u32 src_size_off, src_xy_off, out_size_off, out_xy_off; 416 417 if (!ctx || !cfg) 418 return; 419 420 c = &ctx->hw; 421 422 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || 423 pipe->multirect_index == DPU_SSPP_RECT_0) { 424 src_size_off = SSPP_SRC_SIZE; 425 src_xy_off = SSPP_SRC_XY; 426 out_size_off = SSPP_OUT_SIZE; 427 out_xy_off = SSPP_OUT_XY; 428 } else { 429 src_size_off = SSPP_SRC_SIZE_REC1; 430 src_xy_off = SSPP_SRC_XY_REC1; 431 out_size_off = SSPP_OUT_SIZE_REC1; 432 out_xy_off = SSPP_OUT_XY_REC1; 433 } 434 435 436 /* src and dest rect programming */ 437 src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; 438 src_size = (drm_rect_height(&cfg->src_rect) << 16) | 439 drm_rect_width(&cfg->src_rect); 440 dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; 441 dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | 442 drm_rect_width(&cfg->dst_rect); 443 444 /* rectangle register programming */ 445 DPU_REG_WRITE(c, src_size_off, src_size); 446 DPU_REG_WRITE(c, src_xy_off, src_xy); 447 DPU_REG_WRITE(c, out_size_off, dst_size); 448 DPU_REG_WRITE(c, out_xy_off, dst_xy); 449 } 450 451 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, 452 struct dpu_hw_fmt_layout *layout) 453 { 454 struct dpu_hw_sspp *ctx = pipe->sspp; 455 u32 ystride0, ystride1; 456 int i; 457 458 if (!ctx) 459 return; 460 461 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { 462 for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++) 463 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + i * 0x4, 464 layout->plane_addr[i]); 465 } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { 466 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR, 467 layout->plane_addr[0]); 468 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR, 469 layout->plane_addr[2]); 470 } else { 471 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR, 472 layout->plane_addr[0]); 473 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR, 474 layout->plane_addr[2]); 475 } 476 477 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { 478 ystride0 = (layout->plane_pitch[0]) | 479 (layout->plane_pitch[1] << 16); 480 ystride1 = (layout->plane_pitch[2]) | 481 (layout->plane_pitch[3] << 16); 482 } else { 483 ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0); 484 ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1); 485 486 if (pipe->multirect_index == DPU_SSPP_RECT_0) { 487 ystride0 = (ystride0 & 0xFFFF0000) | 488 (layout->plane_pitch[0] & 0x0000FFFF); 489 ystride1 = (ystride1 & 0xFFFF0000)| 490 (layout->plane_pitch[2] & 0x0000FFFF); 491 } else { 492 ystride0 = (ystride0 & 0x0000FFFF) | 493 ((layout->plane_pitch[0] << 16) & 494 0xFFFF0000); 495 ystride1 = (ystride1 & 0x0000FFFF) | 496 ((layout->plane_pitch[2] << 16) & 497 0xFFFF0000); 498 } 499 } 500 501 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0, ystride0); 502 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); 503 } 504 505 static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, 506 const struct dpu_csc_cfg *data) 507 { 508 u32 offset; 509 bool csc10 = false; 510 511 if (!ctx || !data) 512 return; 513 514 offset = ctx->cap->sblk->csc_blk.base; 515 516 if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { 517 offset += CSC_10BIT_OFFSET; 518 csc10 = true; 519 } 520 521 dpu_hw_csc_setup(&ctx->hw, offset, data, csc10); 522 } 523 524 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) 525 { 526 struct dpu_hw_sspp *ctx = pipe->sspp; 527 struct dpu_hw_fmt_layout cfg; 528 529 if (!ctx) 530 return; 531 532 /* cleanup source addresses */ 533 memset(&cfg, 0, sizeof(cfg)); 534 ctx->ops.setup_sourceaddress(pipe, &cfg); 535 536 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || 537 pipe->multirect_index == DPU_SSPP_RECT_0) 538 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); 539 else 540 DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, 541 color); 542 } 543 544 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, 545 struct dpu_hw_qos_cfg *cfg) 546 { 547 if (!ctx || !cfg) 548 return; 549 550 _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT, 551 test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features), 552 cfg); 553 } 554 555 static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, 556 bool danger_safe_en) 557 { 558 if (!ctx) 559 return; 560 561 DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, 562 danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); 563 } 564 565 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, 566 const struct dpu_format *fmt, 567 bool enable) 568 { 569 struct dpu_hw_sspp *ctx = pipe->sspp; 570 u32 cdp_cntl_offset = 0; 571 572 if (!ctx) 573 return; 574 575 if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || 576 pipe->multirect_index == DPU_SSPP_RECT_0) 577 cdp_cntl_offset = SSPP_CDP_CNTL; 578 else 579 cdp_cntl_offset = SSPP_CDP_CNTL_REC1; 580 581 dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable); 582 } 583 584 static void _setup_layer_ops(struct dpu_hw_sspp *c, 585 unsigned long features) 586 { 587 c->ops.setup_format = dpu_hw_sspp_setup_format; 588 c->ops.setup_rects = dpu_hw_sspp_setup_rects; 589 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; 590 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; 591 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; 592 593 if (test_bit(DPU_SSPP_QOS, &features)) { 594 c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut; 595 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; 596 } 597 598 if (test_bit(DPU_SSPP_CSC, &features) || 599 test_bit(DPU_SSPP_CSC_10BIT, &features)) 600 c->ops.setup_csc = dpu_hw_sspp_setup_csc; 601 602 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || 603 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) 604 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 605 606 if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || 607 test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) || 608 test_bit(DPU_SSPP_SCALER_QSEED4, &features)) { 609 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 610 c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; 611 } 612 613 if (test_bit(DPU_SSPP_CDP, &features)) 614 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; 615 } 616 617 #ifdef CONFIG_DEBUG_FS 618 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 619 struct dentry *entry) 620 { 621 const struct dpu_sspp_cfg *cfg = hw_pipe->cap; 622 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 623 struct dentry *debugfs_root; 624 char sspp_name[32]; 625 626 snprintf(sspp_name, sizeof(sspp_name), "%d", hw_pipe->idx); 627 628 /* create overall sub-directory for the pipe */ 629 debugfs_root = 630 debugfs_create_dir(sspp_name, entry); 631 632 /* don't error check these */ 633 debugfs_create_xul("features", 0600, 634 debugfs_root, (unsigned long *)&hw_pipe->cap->features); 635 636 /* add register dump support */ 637 dpu_debugfs_create_regset32("src_blk", 0400, 638 debugfs_root, 639 cfg->base, 640 cfg->len, 641 kms); 642 643 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 644 cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || 645 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || 646 cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) 647 dpu_debugfs_create_regset32("scaler_blk", 0400, 648 debugfs_root, 649 sblk->scaler_blk.base + cfg->base, 650 sblk->scaler_blk.len, 651 kms); 652 653 if (cfg->features & BIT(DPU_SSPP_CSC) || 654 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) 655 dpu_debugfs_create_regset32("csc_blk", 0400, 656 debugfs_root, 657 sblk->csc_blk.base + cfg->base, 658 sblk->csc_blk.len, 659 kms); 660 661 debugfs_create_u32("xin_id", 662 0400, 663 debugfs_root, 664 (u32 *) &cfg->xin_id); 665 debugfs_create_u32("clk_ctrl", 666 0400, 667 debugfs_root, 668 (u32 *) &cfg->clk_ctrl); 669 670 return 0; 671 } 672 #endif 673 674 struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, 675 void __iomem *addr, const struct msm_mdss_data *mdss_data) 676 { 677 struct dpu_hw_sspp *hw_pipe; 678 679 if (!addr) 680 return ERR_PTR(-EINVAL); 681 682 hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); 683 if (!hw_pipe) 684 return ERR_PTR(-ENOMEM); 685 686 hw_pipe->hw.blk_addr = addr + cfg->base; 687 hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP; 688 689 /* Assign ops */ 690 hw_pipe->ubwc = mdss_data; 691 hw_pipe->idx = cfg->id; 692 hw_pipe->cap = cfg; 693 _setup_layer_ops(hw_pipe, hw_pipe->cap->features); 694 695 return hw_pipe; 696 } 697 698 void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx) 699 { 700 kfree(ctx); 701 } 702 703