1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #define DPU_DBG_NAME "dpu" 14 15 #define DPU_NONE 0 16 17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 18 #define DPU_CSC_MATRIX_COEFF_SIZE 9 19 #endif 20 21 #ifndef DPU_CSC_CLAMP_SIZE 22 #define DPU_CSC_CLAMP_SIZE 6 23 #endif 24 25 #ifndef DPU_CSC_BIAS_SIZE 26 #define DPU_CSC_BIAS_SIZE 3 27 #endif 28 29 #ifndef DPU_MAX_PLANES 30 #define DPU_MAX_PLANES 4 31 #endif 32 33 #define PIPES_PER_STAGE 2 34 #ifndef DPU_MAX_DE_CURVES 35 #define DPU_MAX_DE_CURVES 3 36 #endif 37 38 enum dpu_format_flags { 39 DPU_FORMAT_FLAG_YUV_BIT, 40 DPU_FORMAT_FLAG_DX_BIT, 41 DPU_FORMAT_FLAG_COMPRESSED_BIT, 42 DPU_FORMAT_FLAG_BIT_MAX, 43 }; 44 45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 48 #define DPU_FORMAT_IS_YUV(X) \ 49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 50 #define DPU_FORMAT_IS_DX(X) \ 51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 53 #define DPU_FORMAT_IS_TILE(X) \ 54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 56 #define DPU_FORMAT_IS_UBWC(X) \ 57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 59 60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 76 77 #define DPU_VSYNC0_SOURCE_GPIO 0 78 #define DPU_VSYNC1_SOURCE_GPIO 1 79 #define DPU_VSYNC2_SOURCE_GPIO 2 80 #define DPU_VSYNC_SOURCE_INTF_0 3 81 #define DPU_VSYNC_SOURCE_INTF_1 4 82 #define DPU_VSYNC_SOURCE_INTF_2 5 83 #define DPU_VSYNC_SOURCE_INTF_3 6 84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 89 90 enum dpu_hw_blk_type { 91 DPU_HW_BLK_TOP = 0, 92 DPU_HW_BLK_SSPP, 93 DPU_HW_BLK_LM, 94 DPU_HW_BLK_CTL, 95 DPU_HW_BLK_PINGPONG, 96 DPU_HW_BLK_INTF, 97 DPU_HW_BLK_WB, 98 DPU_HW_BLK_DSPP, 99 DPU_HW_BLK_MERGE_3D, 100 DPU_HW_BLK_DSC, 101 DPU_HW_BLK_CDM, 102 DPU_HW_BLK_MAX, 103 }; 104 105 enum dpu_sspp { 106 SSPP_NONE, 107 SSPP_VIG0, 108 SSPP_VIG1, 109 SSPP_VIG2, 110 SSPP_VIG3, 111 SSPP_RGB0, 112 SSPP_RGB1, 113 SSPP_RGB2, 114 SSPP_RGB3, 115 SSPP_DMA0, 116 SSPP_DMA1, 117 SSPP_DMA2, 118 SSPP_DMA3, 119 SSPP_DMA4, 120 SSPP_DMA5, 121 SSPP_CURSOR0, 122 SSPP_CURSOR1, 123 SSPP_MAX 124 }; 125 126 enum dpu_sspp_type { 127 SSPP_TYPE_VIG, 128 SSPP_TYPE_RGB, 129 SSPP_TYPE_DMA, 130 SSPP_TYPE_CURSOR, 131 SSPP_TYPE_MAX 132 }; 133 134 enum dpu_lm { 135 LM_0 = 1, 136 LM_1, 137 LM_2, 138 LM_3, 139 LM_4, 140 LM_5, 141 LM_6, 142 LM_MAX 143 }; 144 145 enum dpu_stage { 146 DPU_STAGE_BASE = 0, 147 DPU_STAGE_0, 148 DPU_STAGE_1, 149 DPU_STAGE_2, 150 DPU_STAGE_3, 151 DPU_STAGE_4, 152 DPU_STAGE_5, 153 DPU_STAGE_6, 154 DPU_STAGE_7, 155 DPU_STAGE_8, 156 DPU_STAGE_9, 157 DPU_STAGE_10, 158 DPU_STAGE_MAX 159 }; 160 enum dpu_dspp { 161 DSPP_0 = 1, 162 DSPP_1, 163 DSPP_2, 164 DSPP_3, 165 DSPP_MAX 166 }; 167 168 enum dpu_ctl { 169 CTL_0 = 1, 170 CTL_1, 171 CTL_2, 172 CTL_3, 173 CTL_4, 174 CTL_5, 175 CTL_MAX 176 }; 177 178 enum dpu_dsc { 179 DSC_NONE = 0, 180 DSC_0, 181 DSC_1, 182 DSC_2, 183 DSC_3, 184 DSC_4, 185 DSC_5, 186 DSC_MAX 187 }; 188 189 enum dpu_cdm { 190 CDM_0 = 1, 191 CDM_MAX 192 }; 193 194 enum dpu_pingpong { 195 PINGPONG_NONE, 196 PINGPONG_0, 197 PINGPONG_1, 198 PINGPONG_2, 199 PINGPONG_3, 200 PINGPONG_4, 201 PINGPONG_5, 202 PINGPONG_6, 203 PINGPONG_7, 204 PINGPONG_8, 205 PINGPONG_9, 206 PINGPONG_S0, 207 PINGPONG_MAX 208 }; 209 210 enum dpu_merge_3d { 211 MERGE_3D_0 = 1, 212 MERGE_3D_1, 213 MERGE_3D_2, 214 MERGE_3D_3, 215 MERGE_3D_4, 216 MERGE_3D_MAX 217 }; 218 219 enum dpu_intf { 220 INTF_0 = 1, 221 INTF_1, 222 INTF_2, 223 INTF_3, 224 INTF_4, 225 INTF_5, 226 INTF_6, 227 INTF_7, 228 INTF_8, 229 INTF_MAX 230 }; 231 232 /* 233 * Historically these values correspond to the values written to the 234 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 235 * generations this register is NOP, but we keep the values for historical 236 * reasons. 237 */ 238 enum dpu_intf_type { 239 INTF_NONE = 0x0, 240 INTF_DSI = 0x1, 241 INTF_HDMI = 0x3, 242 INTF_LCDC = 0x5, 243 /* old eDP found on 8x74 and 8x84 */ 244 INTF_EDP = 0x9, 245 /* both DP and eDP, handled by the new DP driver */ 246 INTF_DP = 0xa, 247 248 /* virtual interfaces */ 249 INTF_WB = 0x100, 250 }; 251 252 enum dpu_intf_mode { 253 INTF_MODE_NONE = 0, 254 INTF_MODE_CMD, 255 INTF_MODE_VIDEO, 256 INTF_MODE_WB_BLOCK, 257 INTF_MODE_WB_LINE, 258 INTF_MODE_MAX 259 }; 260 261 enum dpu_wb { 262 WB_0 = 1, 263 WB_1, 264 WB_2, 265 WB_3, 266 WB_MAX 267 }; 268 269 enum dpu_cwb { 270 CWB_0 = 0x1, 271 CWB_1, 272 CWB_2, 273 CWB_3, 274 CWB_MAX 275 }; 276 277 enum dpu_wd_timer { 278 WD_TIMER_0 = 0x1, 279 WD_TIMER_1, 280 WD_TIMER_2, 281 WD_TIMER_3, 282 WD_TIMER_4, 283 WD_TIMER_5, 284 WD_TIMER_MAX 285 }; 286 287 enum dpu_vbif { 288 VBIF_RT, 289 VBIF_NRT, 290 VBIF_MAX, 291 }; 292 293 /** 294 * DPU HW,Component order color map 295 */ 296 enum { 297 C0_G_Y = 0, 298 C1_B_Cb = 1, 299 C2_R_Cr = 2, 300 C3_ALPHA = 3 301 }; 302 303 /** 304 * enum dpu_plane_type - defines how the color component pixel packing 305 * @DPU_PLANE_INTERLEAVED : Color components in single plane 306 * @DPU_PLANE_PLANAR : Color component in separate planes 307 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 308 */ 309 enum dpu_plane_type { 310 DPU_PLANE_INTERLEAVED, 311 DPU_PLANE_PLANAR, 312 DPU_PLANE_PSEUDO_PLANAR, 313 }; 314 315 /** 316 * enum dpu_chroma_samp_type - chroma sub-samplng type 317 * @DPU_CHROMA_RGB : No chroma subsampling 318 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 319 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 320 * @DPU_CHROMA_420 : 420 subsampling 321 */ 322 enum dpu_chroma_samp_type { 323 DPU_CHROMA_RGB, 324 DPU_CHROMA_H2V1, 325 DPU_CHROMA_H1V2, 326 DPU_CHROMA_420 327 }; 328 329 /** 330 * dpu_fetch_type - Defines How DPU HW fetches data 331 * @DPU_FETCH_LINEAR : fetch is line by line 332 * @DPU_FETCH_TILE : fetches data in Z order from a tile 333 * @DPU_FETCH_UBWC : fetch and decompress data 334 */ 335 enum dpu_fetch_type { 336 DPU_FETCH_LINEAR, 337 DPU_FETCH_TILE, 338 DPU_FETCH_UBWC 339 }; 340 341 /** 342 * Value of enum chosen to fit the number of bits 343 * expected by the HW programming. 344 */ 345 enum { 346 COLOR_ALPHA_1BIT = 0, 347 COLOR_ALPHA_4BIT = 1, 348 COLOR_4BIT = 0, 349 COLOR_5BIT = 1, /* No 5-bit Alpha */ 350 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 351 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 352 }; 353 354 /** 355 * enum dpu_3d_blend_mode 356 * Desribes how the 3d data is blended 357 * @BLEND_3D_NONE : 3d blending not enabled 358 * @BLEND_3D_FRAME_INT : Frame interleaving 359 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 360 * @BLEND_3D_V_ROW_INT : vertical row interleaving 361 * @BLEND_3D_COL_INT : column interleaving 362 * @BLEND_3D_MAX : 363 */ 364 enum dpu_3d_blend_mode { 365 BLEND_3D_NONE = 0, 366 BLEND_3D_FRAME_INT, 367 BLEND_3D_H_ROW_INT, 368 BLEND_3D_V_ROW_INT, 369 BLEND_3D_COL_INT, 370 BLEND_3D_MAX 371 }; 372 373 /** struct dpu_format - defines the format configuration which 374 * allows DPU HW to correctly fetch and decode the format 375 * @base: base msm_format structure containing fourcc code 376 * @fetch_planes: how the color components are packed in pixel format 377 * @element: element color ordering 378 * @bits: element bit widths 379 * @chroma_sample: chroma sub-samplng type 380 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 381 * @unpack_tight: 0 for loose, 1 for tight 382 * @unpack_count: 0 = 1 component, 1 = 2 component 383 * @bpp: bytes per pixel 384 * @alpha_enable: whether the format has an alpha channel 385 * @num_planes: number of planes (including meta data planes) 386 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 387 * @flag: usage bit flags 388 * @tile_width: format tile width 389 * @tile_height: format tile height 390 */ 391 struct dpu_format { 392 struct msm_format base; 393 enum dpu_plane_type fetch_planes; 394 u8 element[DPU_MAX_PLANES]; 395 u8 bits[DPU_MAX_PLANES]; 396 enum dpu_chroma_samp_type chroma_sample; 397 u8 unpack_align_msb; 398 u8 unpack_tight; 399 u8 unpack_count; 400 u8 bpp; 401 u8 alpha_enable; 402 u8 num_planes; 403 enum dpu_fetch_type fetch_mode; 404 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 405 u16 tile_width; 406 u16 tile_height; 407 }; 408 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 409 410 /** 411 * struct dpu_hw_fmt_layout - format information of the source pixel data 412 * @format: pixel format parameters 413 * @num_planes: number of planes (including meta data planes) 414 * @width: image width 415 * @height: image height 416 * @total_size: total size in bytes 417 * @plane_addr: address of each plane 418 * @plane_size: length of each plane 419 * @plane_pitch: pitch of each plane 420 */ 421 struct dpu_hw_fmt_layout { 422 const struct dpu_format *format; 423 uint32_t num_planes; 424 uint32_t width; 425 uint32_t height; 426 uint32_t total_size; 427 uint32_t plane_addr[DPU_MAX_PLANES]; 428 uint32_t plane_size[DPU_MAX_PLANES]; 429 uint32_t plane_pitch[DPU_MAX_PLANES]; 430 }; 431 432 struct dpu_csc_cfg { 433 /* matrix coefficients in S15.16 format */ 434 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 435 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 436 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 437 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 438 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 439 }; 440 441 /** 442 * struct dpu_mdss_color - mdss color description 443 * color 0 : green 444 * color 1 : blue 445 * color 2 : red 446 * color 3 : alpha 447 */ 448 struct dpu_mdss_color { 449 u32 color_0; 450 u32 color_1; 451 u32 color_2; 452 u32 color_3; 453 }; 454 455 /* 456 * Define bit masks for h/w logging. 457 */ 458 #define DPU_DBG_MASK_NONE (1 << 0) 459 #define DPU_DBG_MASK_INTF (1 << 1) 460 #define DPU_DBG_MASK_LM (1 << 2) 461 #define DPU_DBG_MASK_CTL (1 << 3) 462 #define DPU_DBG_MASK_PINGPONG (1 << 4) 463 #define DPU_DBG_MASK_SSPP (1 << 5) 464 #define DPU_DBG_MASK_WB (1 << 6) 465 #define DPU_DBG_MASK_TOP (1 << 7) 466 #define DPU_DBG_MASK_VBIF (1 << 8) 467 #define DPU_DBG_MASK_ROT (1 << 9) 468 #define DPU_DBG_MASK_DSPP (1 << 10) 469 #define DPU_DBG_MASK_DSC (1 << 11) 470 #define DPU_DBG_MASK_CDM (1 << 12) 471 472 /** 473 * struct dpu_hw_tear_check - Struct contains parameters to configure 474 * tear-effect module. This structure is used to configure tear-check 475 * logic present either in ping-pong or in interface module. 476 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 477 * by no of lines 478 * @sync_cfg_height: Total vertical lines (display height - 1) 479 * @vsync_init_val: Init value to which the read pointer gets loaded at 480 * vsync edge 481 * @sync_threshold_start: Read pointer threshold start ROI for write operation 482 * @sync_threshold_continue: The minimum number of lines the write pointer 483 * needs to be above the read pointer 484 * @start_pos: The position from which the start_threshold value is added 485 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 486 * @hw_vsync_mode: Sync with external frame sync input 487 */ 488 struct dpu_hw_tear_check { 489 /* 490 * This is ratio of MDP VSYNC clk freq(Hz) to 491 * refresh rate divided by no of lines 492 */ 493 u32 vsync_count; 494 u32 sync_cfg_height; 495 u32 vsync_init_val; 496 u32 sync_threshold_start; 497 u32 sync_threshold_continue; 498 u32 start_pos; 499 u32 rd_ptr_irq; 500 u8 hw_vsync_mode; 501 }; 502 503 /** 504 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 505 * read and write pointers for command mode panels 506 * @rd_ptr_init_val: Value of rd pointer at vsync edge 507 * @rd_ptr_frame_count: Num frames sent since enabling interface 508 * @rd_ptr_line_count: Current line on panel (rd ptr) 509 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 510 * @intf_frame_count: Frames read from intf 511 */ 512 struct dpu_hw_pp_vsync_info { 513 u32 rd_ptr_init_val; 514 u32 rd_ptr_frame_count; 515 u32 rd_ptr_line_count; 516 u32 wr_ptr_line_count; 517 u32 intf_frame_count; 518 }; 519 520 #endif /* _DPU_HW_MDSS_H */ 521