1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _DPU_HW_MDSS_H 14 #define _DPU_HW_MDSS_H 15 16 #include <linux/kernel.h> 17 #include <linux/err.h> 18 19 #include "msm_drv.h" 20 21 #define DPU_DBG_NAME "dpu" 22 23 #define DPU_NONE 0 24 25 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 26 #define DPU_CSC_MATRIX_COEFF_SIZE 9 27 #endif 28 29 #ifndef DPU_CSC_CLAMP_SIZE 30 #define DPU_CSC_CLAMP_SIZE 6 31 #endif 32 33 #ifndef DPU_CSC_BIAS_SIZE 34 #define DPU_CSC_BIAS_SIZE 3 35 #endif 36 37 #ifndef DPU_MAX_PLANES 38 #define DPU_MAX_PLANES 4 39 #endif 40 41 #define PIPES_PER_STAGE 2 42 #ifndef DPU_MAX_DE_CURVES 43 #define DPU_MAX_DE_CURVES 3 44 #endif 45 46 enum dpu_format_flags { 47 DPU_FORMAT_FLAG_YUV_BIT, 48 DPU_FORMAT_FLAG_DX_BIT, 49 DPU_FORMAT_FLAG_COMPRESSED_BIT, 50 DPU_FORMAT_FLAG_BIT_MAX, 51 }; 52 53 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 54 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 55 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 56 #define DPU_FORMAT_IS_YUV(X) \ 57 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 58 #define DPU_FORMAT_IS_DX(X) \ 59 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 60 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 61 #define DPU_FORMAT_IS_TILE(X) \ 62 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 63 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 64 #define DPU_FORMAT_IS_UBWC(X) \ 65 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 66 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 67 68 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 69 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 70 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 71 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 72 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 73 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 74 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 75 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 76 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 77 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 78 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 79 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 80 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 81 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 82 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 83 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 84 85 #define DPU_VSYNC0_SOURCE_GPIO 0 86 #define DPU_VSYNC1_SOURCE_GPIO 1 87 #define DPU_VSYNC2_SOURCE_GPIO 2 88 #define DPU_VSYNC_SOURCE_INTF_0 3 89 #define DPU_VSYNC_SOURCE_INTF_1 4 90 #define DPU_VSYNC_SOURCE_INTF_2 5 91 #define DPU_VSYNC_SOURCE_INTF_3 6 92 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 93 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 94 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 95 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 96 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 97 98 enum dpu_hw_blk_type { 99 DPU_HW_BLK_TOP = 0, 100 DPU_HW_BLK_SSPP, 101 DPU_HW_BLK_LM, 102 DPU_HW_BLK_CTL, 103 DPU_HW_BLK_CDM, 104 DPU_HW_BLK_PINGPONG, 105 DPU_HW_BLK_INTF, 106 DPU_HW_BLK_WB, 107 DPU_HW_BLK_MAX, 108 }; 109 110 enum dpu_mdp { 111 MDP_TOP = 0x1, 112 MDP_MAX, 113 }; 114 115 enum dpu_sspp { 116 SSPP_NONE, 117 SSPP_VIG0, 118 SSPP_VIG1, 119 SSPP_VIG2, 120 SSPP_VIG3, 121 SSPP_RGB0, 122 SSPP_RGB1, 123 SSPP_RGB2, 124 SSPP_RGB3, 125 SSPP_DMA0, 126 SSPP_DMA1, 127 SSPP_DMA2, 128 SSPP_DMA3, 129 SSPP_CURSOR0, 130 SSPP_CURSOR1, 131 SSPP_MAX 132 }; 133 134 enum dpu_sspp_type { 135 SSPP_TYPE_VIG, 136 SSPP_TYPE_RGB, 137 SSPP_TYPE_DMA, 138 SSPP_TYPE_CURSOR, 139 SSPP_TYPE_MAX 140 }; 141 142 enum dpu_lm { 143 LM_0 = 1, 144 LM_1, 145 LM_2, 146 LM_3, 147 LM_4, 148 LM_5, 149 LM_6, 150 LM_MAX 151 }; 152 153 enum dpu_stage { 154 DPU_STAGE_BASE = 0, 155 DPU_STAGE_0, 156 DPU_STAGE_1, 157 DPU_STAGE_2, 158 DPU_STAGE_3, 159 DPU_STAGE_4, 160 DPU_STAGE_5, 161 DPU_STAGE_6, 162 DPU_STAGE_7, 163 DPU_STAGE_8, 164 DPU_STAGE_9, 165 DPU_STAGE_10, 166 DPU_STAGE_MAX 167 }; 168 enum dpu_dspp { 169 DSPP_0 = 1, 170 DSPP_1, 171 DSPP_2, 172 DSPP_3, 173 DSPP_MAX 174 }; 175 176 enum dpu_ds { 177 DS_TOP, 178 DS_0, 179 DS_1, 180 DS_MAX 181 }; 182 183 enum dpu_ctl { 184 CTL_0 = 1, 185 CTL_1, 186 CTL_2, 187 CTL_3, 188 CTL_4, 189 CTL_MAX 190 }; 191 192 enum dpu_cdm { 193 CDM_0 = 1, 194 CDM_1, 195 CDM_MAX 196 }; 197 198 enum dpu_pingpong { 199 PINGPONG_0 = 1, 200 PINGPONG_1, 201 PINGPONG_2, 202 PINGPONG_3, 203 PINGPONG_4, 204 PINGPONG_S0, 205 PINGPONG_MAX 206 }; 207 208 enum dpu_intf { 209 INTF_0 = 1, 210 INTF_1, 211 INTF_2, 212 INTF_3, 213 INTF_4, 214 INTF_5, 215 INTF_6, 216 INTF_MAX 217 }; 218 219 enum dpu_intf_type { 220 INTF_NONE = 0x0, 221 INTF_DSI = 0x1, 222 INTF_HDMI = 0x3, 223 INTF_LCDC = 0x5, 224 INTF_EDP = 0x9, 225 INTF_DP = 0xa, 226 INTF_TYPE_MAX, 227 228 /* virtual interfaces */ 229 INTF_WB = 0x100, 230 }; 231 232 enum dpu_intf_mode { 233 INTF_MODE_NONE = 0, 234 INTF_MODE_CMD, 235 INTF_MODE_VIDEO, 236 INTF_MODE_WB_BLOCK, 237 INTF_MODE_WB_LINE, 238 INTF_MODE_MAX 239 }; 240 241 enum dpu_wb { 242 WB_0 = 1, 243 WB_1, 244 WB_2, 245 WB_3, 246 WB_MAX 247 }; 248 249 enum dpu_ad { 250 AD_0 = 0x1, 251 AD_1, 252 AD_MAX 253 }; 254 255 enum dpu_cwb { 256 CWB_0 = 0x1, 257 CWB_1, 258 CWB_2, 259 CWB_3, 260 CWB_MAX 261 }; 262 263 enum dpu_wd_timer { 264 WD_TIMER_0 = 0x1, 265 WD_TIMER_1, 266 WD_TIMER_2, 267 WD_TIMER_3, 268 WD_TIMER_4, 269 WD_TIMER_5, 270 WD_TIMER_MAX 271 }; 272 273 enum dpu_vbif { 274 VBIF_0, 275 VBIF_1, 276 VBIF_MAX, 277 VBIF_RT = VBIF_0, 278 VBIF_NRT = VBIF_1 279 }; 280 281 enum dpu_iommu_domain { 282 DPU_IOMMU_DOMAIN_UNSECURE, 283 DPU_IOMMU_DOMAIN_SECURE, 284 DPU_IOMMU_DOMAIN_MAX 285 }; 286 287 /** 288 * DPU HW,Component order color map 289 */ 290 enum { 291 C0_G_Y = 0, 292 C1_B_Cb = 1, 293 C2_R_Cr = 2, 294 C3_ALPHA = 3 295 }; 296 297 /** 298 * enum dpu_plane_type - defines how the color component pixel packing 299 * @DPU_PLANE_INTERLEAVED : Color components in single plane 300 * @DPU_PLANE_PLANAR : Color component in separate planes 301 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 302 */ 303 enum dpu_plane_type { 304 DPU_PLANE_INTERLEAVED, 305 DPU_PLANE_PLANAR, 306 DPU_PLANE_PSEUDO_PLANAR, 307 }; 308 309 /** 310 * enum dpu_chroma_samp_type - chroma sub-samplng type 311 * @DPU_CHROMA_RGB : No chroma subsampling 312 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 313 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 314 * @DPU_CHROMA_420 : 420 subsampling 315 */ 316 enum dpu_chroma_samp_type { 317 DPU_CHROMA_RGB, 318 DPU_CHROMA_H2V1, 319 DPU_CHROMA_H1V2, 320 DPU_CHROMA_420 321 }; 322 323 /** 324 * dpu_fetch_type - Defines How DPU HW fetches data 325 * @DPU_FETCH_LINEAR : fetch is line by line 326 * @DPU_FETCH_TILE : fetches data in Z order from a tile 327 * @DPU_FETCH_UBWC : fetch and decompress data 328 */ 329 enum dpu_fetch_type { 330 DPU_FETCH_LINEAR, 331 DPU_FETCH_TILE, 332 DPU_FETCH_UBWC 333 }; 334 335 /** 336 * Value of enum chosen to fit the number of bits 337 * expected by the HW programming. 338 */ 339 enum { 340 COLOR_ALPHA_1BIT = 0, 341 COLOR_ALPHA_4BIT = 1, 342 COLOR_4BIT = 0, 343 COLOR_5BIT = 1, /* No 5-bit Alpha */ 344 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 345 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 346 }; 347 348 /** 349 * enum dpu_3d_blend_mode 350 * Desribes how the 3d data is blended 351 * @BLEND_3D_NONE : 3d blending not enabled 352 * @BLEND_3D_FRAME_INT : Frame interleaving 353 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 354 * @BLEND_3D_V_ROW_INT : vertical row interleaving 355 * @BLEND_3D_COL_INT : column interleaving 356 * @BLEND_3D_MAX : 357 */ 358 enum dpu_3d_blend_mode { 359 BLEND_3D_NONE = 0, 360 BLEND_3D_FRAME_INT, 361 BLEND_3D_H_ROW_INT, 362 BLEND_3D_V_ROW_INT, 363 BLEND_3D_COL_INT, 364 BLEND_3D_MAX 365 }; 366 367 /** struct dpu_format - defines the format configuration which 368 * allows DPU HW to correctly fetch and decode the format 369 * @base: base msm_format struture containing fourcc code 370 * @fetch_planes: how the color components are packed in pixel format 371 * @element: element color ordering 372 * @bits: element bit widths 373 * @chroma_sample: chroma sub-samplng type 374 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 375 * @unpack_tight: 0 for loose, 1 for tight 376 * @unpack_count: 0 = 1 component, 1 = 2 component 377 * @bpp: bytes per pixel 378 * @alpha_enable: whether the format has an alpha channel 379 * @num_planes: number of planes (including meta data planes) 380 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 381 * @is_yuv: is format a yuv variant 382 * @flag: usage bit flags 383 * @tile_width: format tile width 384 * @tile_height: format tile height 385 */ 386 struct dpu_format { 387 struct msm_format base; 388 enum dpu_plane_type fetch_planes; 389 u8 element[DPU_MAX_PLANES]; 390 u8 bits[DPU_MAX_PLANES]; 391 enum dpu_chroma_samp_type chroma_sample; 392 u8 unpack_align_msb; 393 u8 unpack_tight; 394 u8 unpack_count; 395 u8 bpp; 396 u8 alpha_enable; 397 u8 num_planes; 398 enum dpu_fetch_type fetch_mode; 399 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 400 u16 tile_width; 401 u16 tile_height; 402 }; 403 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 404 405 /** 406 * struct dpu_hw_fmt_layout - format information of the source pixel data 407 * @format: pixel format parameters 408 * @num_planes: number of planes (including meta data planes) 409 * @width: image width 410 * @height: image height 411 * @total_size: total size in bytes 412 * @plane_addr: address of each plane 413 * @plane_size: length of each plane 414 * @plane_pitch: pitch of each plane 415 */ 416 struct dpu_hw_fmt_layout { 417 const struct dpu_format *format; 418 uint32_t num_planes; 419 uint32_t width; 420 uint32_t height; 421 uint32_t total_size; 422 uint32_t plane_addr[DPU_MAX_PLANES]; 423 uint32_t plane_size[DPU_MAX_PLANES]; 424 uint32_t plane_pitch[DPU_MAX_PLANES]; 425 }; 426 427 struct dpu_csc_cfg { 428 /* matrix coefficients in S15.16 format */ 429 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 430 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 431 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 432 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 433 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 434 }; 435 436 /** 437 * struct dpu_mdss_color - mdss color description 438 * color 0 : green 439 * color 1 : blue 440 * color 2 : red 441 * color 3 : alpha 442 */ 443 struct dpu_mdss_color { 444 u32 color_0; 445 u32 color_1; 446 u32 color_2; 447 u32 color_3; 448 }; 449 450 /* 451 * Define bit masks for h/w logging. 452 */ 453 #define DPU_DBG_MASK_NONE (1 << 0) 454 #define DPU_DBG_MASK_CDM (1 << 1) 455 #define DPU_DBG_MASK_INTF (1 << 2) 456 #define DPU_DBG_MASK_LM (1 << 3) 457 #define DPU_DBG_MASK_CTL (1 << 4) 458 #define DPU_DBG_MASK_PINGPONG (1 << 5) 459 #define DPU_DBG_MASK_SSPP (1 << 6) 460 #define DPU_DBG_MASK_WB (1 << 7) 461 #define DPU_DBG_MASK_TOP (1 << 8) 462 #define DPU_DBG_MASK_VBIF (1 << 9) 463 #define DPU_DBG_MASK_ROT (1 << 10) 464 465 #endif /* _DPU_HW_MDSS_H */ 466