1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_MDSS_H 8 #define _DPU_HW_MDSS_H 9 10 #include <linux/kernel.h> 11 #include <linux/err.h> 12 13 #include "msm_drv.h" 14 15 #include "disp/mdp_format.h" 16 17 #define DPU_DBG_NAME "dpu" 18 19 #define DPU_NONE 0 20 21 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 22 #define DPU_CSC_MATRIX_COEFF_SIZE 9 23 #endif 24 25 #ifndef DPU_CSC_CLAMP_SIZE 26 #define DPU_CSC_CLAMP_SIZE 6 27 #endif 28 29 #ifndef DPU_CSC_BIAS_SIZE 30 #define DPU_CSC_BIAS_SIZE 3 31 #endif 32 33 #ifndef DPU_MAX_PLANES 34 #define DPU_MAX_PLANES 4 35 #endif 36 37 #define PIPES_PER_STAGE 2 38 #ifndef DPU_MAX_DE_CURVES 39 #define DPU_MAX_DE_CURVES 3 40 #endif 41 42 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 43 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 44 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 45 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 46 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 47 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 48 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 49 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 50 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 51 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 52 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 53 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 54 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 55 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 56 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 57 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 58 59 enum dpu_vsync_source { 60 DPU_VSYNC_SOURCE_GPIO_0, 61 DPU_VSYNC_SOURCE_GPIO_1, 62 DPU_VSYNC_SOURCE_GPIO_2, 63 DPU_VSYNC_SOURCE_INTF_0 = 3, 64 DPU_VSYNC_SOURCE_INTF_1, 65 DPU_VSYNC_SOURCE_INTF_2, 66 DPU_VSYNC_SOURCE_INTF_3, 67 DPU_VSYNC_SOURCE_WD_TIMER_4 = 11, 68 DPU_VSYNC_SOURCE_WD_TIMER_3, 69 DPU_VSYNC_SOURCE_WD_TIMER_2, 70 DPU_VSYNC_SOURCE_WD_TIMER_1, 71 DPU_VSYNC_SOURCE_WD_TIMER_0, 72 }; 73 74 enum dpu_hw_blk_type { 75 DPU_HW_BLK_TOP = 0, 76 DPU_HW_BLK_SSPP, 77 DPU_HW_BLK_LM, 78 DPU_HW_BLK_CTL, 79 DPU_HW_BLK_PINGPONG, 80 DPU_HW_BLK_INTF, 81 DPU_HW_BLK_WB, 82 DPU_HW_BLK_DSPP, 83 DPU_HW_BLK_MERGE_3D, 84 DPU_HW_BLK_DSC, 85 DPU_HW_BLK_CDM, 86 DPU_HW_BLK_MAX, 87 }; 88 89 enum dpu_sspp { 90 SSPP_NONE, 91 SSPP_VIG0, 92 SSPP_VIG1, 93 SSPP_VIG2, 94 SSPP_VIG3, 95 SSPP_RGB0, 96 SSPP_RGB1, 97 SSPP_RGB2, 98 SSPP_RGB3, 99 SSPP_DMA0, 100 SSPP_DMA1, 101 SSPP_DMA2, 102 SSPP_DMA3, 103 SSPP_DMA4, 104 SSPP_DMA5, 105 SSPP_CURSOR0, 106 SSPP_CURSOR1, 107 SSPP_MAX 108 }; 109 110 enum dpu_sspp_type { 111 SSPP_TYPE_VIG, 112 SSPP_TYPE_RGB, 113 SSPP_TYPE_DMA, 114 SSPP_TYPE_CURSOR, 115 SSPP_TYPE_MAX 116 }; 117 118 enum dpu_lm { 119 LM_0 = 1, 120 LM_1, 121 LM_2, 122 LM_3, 123 LM_4, 124 LM_5, 125 LM_6, 126 LM_MAX 127 }; 128 129 enum dpu_stage { 130 DPU_STAGE_BASE = 0, 131 DPU_STAGE_0, 132 DPU_STAGE_1, 133 DPU_STAGE_2, 134 DPU_STAGE_3, 135 DPU_STAGE_4, 136 DPU_STAGE_5, 137 DPU_STAGE_6, 138 DPU_STAGE_7, 139 DPU_STAGE_8, 140 DPU_STAGE_9, 141 DPU_STAGE_10, 142 DPU_STAGE_MAX 143 }; 144 enum dpu_dspp { 145 DSPP_0 = 1, 146 DSPP_1, 147 DSPP_2, 148 DSPP_3, 149 DSPP_MAX 150 }; 151 152 enum dpu_ctl { 153 CTL_0 = 1, 154 CTL_1, 155 CTL_2, 156 CTL_3, 157 CTL_4, 158 CTL_5, 159 CTL_MAX 160 }; 161 162 enum dpu_dsc { 163 DSC_NONE = 0, 164 DSC_0, 165 DSC_1, 166 DSC_2, 167 DSC_3, 168 DSC_4, 169 DSC_5, 170 DSC_MAX 171 }; 172 173 enum dpu_cdm { 174 CDM_0 = 1, 175 CDM_MAX 176 }; 177 178 enum dpu_pingpong { 179 PINGPONG_NONE, 180 PINGPONG_0, 181 PINGPONG_1, 182 PINGPONG_2, 183 PINGPONG_3, 184 PINGPONG_4, 185 PINGPONG_5, 186 PINGPONG_CWB_0, 187 PINGPONG_CWB_1, 188 PINGPONG_CWB_2, 189 PINGPONG_CWB_3, 190 PINGPONG_S0, 191 PINGPONG_MAX 192 }; 193 194 enum dpu_merge_3d { 195 MERGE_3D_0 = 1, 196 MERGE_3D_1, 197 MERGE_3D_2, 198 MERGE_3D_3, 199 MERGE_3D_4, 200 MERGE_3D_MAX 201 }; 202 203 enum dpu_intf { 204 INTF_0 = 1, 205 INTF_1, 206 INTF_2, 207 INTF_3, 208 INTF_4, 209 INTF_5, 210 INTF_6, 211 INTF_7, 212 INTF_8, 213 INTF_MAX 214 }; 215 216 /* 217 * Historically these values correspond to the values written to the 218 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 219 * generations this register is NOP, but we keep the values for historical 220 * reasons. 221 */ 222 enum dpu_intf_type { 223 INTF_NONE = 0x0, 224 INTF_DSI = 0x1, 225 INTF_HDMI = 0x3, 226 INTF_LCDC = 0x5, 227 /* old eDP found on 8x74 and 8x84 */ 228 INTF_EDP = 0x9, 229 /* both DP and eDP, handled by the new DP driver */ 230 INTF_DP = 0xa, 231 232 /* virtual interfaces */ 233 INTF_WB = 0x100, 234 }; 235 236 enum dpu_intf_mode { 237 INTF_MODE_NONE = 0, 238 INTF_MODE_CMD, 239 INTF_MODE_VIDEO, 240 INTF_MODE_WB_BLOCK, 241 INTF_MODE_WB_LINE, 242 INTF_MODE_MAX 243 }; 244 245 enum dpu_wb { 246 WB_0 = 1, 247 WB_1, 248 WB_2, 249 WB_3, 250 WB_MAX 251 }; 252 253 enum dpu_cwb { 254 CWB_0 = 0x1, 255 CWB_1, 256 CWB_2, 257 CWB_3, 258 CWB_MAX 259 }; 260 261 enum dpu_wd_timer { 262 WD_TIMER_0 = 0x1, 263 WD_TIMER_1, 264 WD_TIMER_2, 265 WD_TIMER_3, 266 WD_TIMER_4, 267 WD_TIMER_5, 268 WD_TIMER_MAX 269 }; 270 271 enum dpu_vbif { 272 VBIF_RT, 273 VBIF_NRT, 274 VBIF_MAX, 275 }; 276 277 /** 278 * enum dpu_3d_blend_mode 279 * Desribes how the 3d data is blended 280 * @BLEND_3D_NONE : 3d blending not enabled 281 * @BLEND_3D_FRAME_INT : Frame interleaving 282 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 283 * @BLEND_3D_V_ROW_INT : vertical row interleaving 284 * @BLEND_3D_COL_INT : column interleaving 285 * @BLEND_3D_MAX : 286 */ 287 enum dpu_3d_blend_mode { 288 BLEND_3D_NONE = 0, 289 BLEND_3D_FRAME_INT, 290 BLEND_3D_H_ROW_INT, 291 BLEND_3D_V_ROW_INT, 292 BLEND_3D_COL_INT, 293 BLEND_3D_MAX 294 }; 295 296 /** 297 * struct dpu_hw_fmt_layout - format information of the source pixel data 298 * @num_planes: number of planes (including meta data planes) 299 * @width: image width 300 * @height: image height 301 * @total_size: total size in bytes 302 * @plane_addr: address of each plane 303 * @plane_size: length of each plane 304 * @plane_pitch: pitch of each plane 305 */ 306 struct dpu_hw_fmt_layout { 307 uint32_t num_planes; 308 uint32_t width; 309 uint32_t height; 310 uint32_t total_size; 311 uint32_t plane_addr[DPU_MAX_PLANES]; 312 uint32_t plane_size[DPU_MAX_PLANES]; 313 uint32_t plane_pitch[DPU_MAX_PLANES]; 314 }; 315 316 struct dpu_csc_cfg { 317 /* matrix coefficients in S15.16 format */ 318 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 319 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 320 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 321 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 322 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 323 }; 324 325 /** 326 * struct dpu_mdss_color - mdss color description 327 * color 0 : green 328 * color 1 : blue 329 * color 2 : red 330 * color 3 : alpha 331 */ 332 struct dpu_mdss_color { 333 u32 color_0; 334 u32 color_1; 335 u32 color_2; 336 u32 color_3; 337 }; 338 339 /* 340 * Define bit masks for h/w logging. 341 */ 342 #define DPU_DBG_MASK_NONE (1 << 0) 343 #define DPU_DBG_MASK_INTF (1 << 1) 344 #define DPU_DBG_MASK_LM (1 << 2) 345 #define DPU_DBG_MASK_CTL (1 << 3) 346 #define DPU_DBG_MASK_PINGPONG (1 << 4) 347 #define DPU_DBG_MASK_SSPP (1 << 5) 348 #define DPU_DBG_MASK_WB (1 << 6) 349 #define DPU_DBG_MASK_TOP (1 << 7) 350 #define DPU_DBG_MASK_VBIF (1 << 8) 351 #define DPU_DBG_MASK_ROT (1 << 9) 352 #define DPU_DBG_MASK_DSPP (1 << 10) 353 #define DPU_DBG_MASK_DSC (1 << 11) 354 #define DPU_DBG_MASK_CDM (1 << 12) 355 #define DPU_DBG_MASK_CWB (1 << 13) 356 357 /** 358 * struct dpu_hw_tear_check - Struct contains parameters to configure 359 * tear-effect module. This structure is used to configure tear-check 360 * logic present either in ping-pong or in interface module. 361 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 362 * by no of lines 363 * @sync_cfg_height: Total vertical lines (display height - 1) 364 * @vsync_init_val: Init value to which the read pointer gets loaded at 365 * vsync edge 366 * @sync_threshold_start: Read pointer threshold start ROI for write operation 367 * @sync_threshold_continue: The minimum number of lines the write pointer 368 * needs to be above the read pointer 369 * @start_pos: The position from which the start_threshold value is added 370 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 371 * @hw_vsync_mode: Sync with external frame sync input 372 */ 373 struct dpu_hw_tear_check { 374 /* 375 * This is ratio of MDP VSYNC clk freq(Hz) to 376 * refresh rate divided by no of lines 377 */ 378 u32 vsync_count; 379 u32 sync_cfg_height; 380 u32 vsync_init_val; 381 u32 sync_threshold_start; 382 u32 sync_threshold_continue; 383 u32 start_pos; 384 u32 rd_ptr_irq; 385 u8 hw_vsync_mode; 386 }; 387 388 /** 389 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 390 * read and write pointers for command mode panels 391 * @rd_ptr_init_val: Value of rd pointer at vsync edge 392 * @rd_ptr_frame_count: Num frames sent since enabling interface 393 * @rd_ptr_line_count: Current line on panel (rd ptr) 394 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 395 * @intf_frame_count: Frames read from intf 396 */ 397 struct dpu_hw_pp_vsync_info { 398 u32 rd_ptr_init_val; 399 u32 rd_ptr_frame_count; 400 u32 rd_ptr_line_count; 401 u32 wr_ptr_line_count; 402 u32 intf_frame_count; 403 }; 404 405 #endif /* _DPU_HW_MDSS_H */ 406