1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #include "disp/mdp_format.h" 14 15 #define DPU_DBG_NAME "dpu" 16 17 #define DPU_NONE 0 18 19 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 20 #define DPU_CSC_MATRIX_COEFF_SIZE 9 21 #endif 22 23 #ifndef DPU_CSC_CLAMP_SIZE 24 #define DPU_CSC_CLAMP_SIZE 6 25 #endif 26 27 #ifndef DPU_CSC_BIAS_SIZE 28 #define DPU_CSC_BIAS_SIZE 3 29 #endif 30 31 #ifndef DPU_MAX_PLANES 32 #define DPU_MAX_PLANES 4 33 #endif 34 35 #define PIPES_PER_STAGE 2 36 #ifndef DPU_MAX_DE_CURVES 37 #define DPU_MAX_DE_CURVES 3 38 #endif 39 40 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 41 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 42 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 43 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 44 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 45 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 46 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 47 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 48 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 49 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 50 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 51 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 52 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 53 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 54 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 55 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 56 57 #define DPU_VSYNC0_SOURCE_GPIO 0 58 #define DPU_VSYNC1_SOURCE_GPIO 1 59 #define DPU_VSYNC2_SOURCE_GPIO 2 60 #define DPU_VSYNC_SOURCE_INTF_0 3 61 #define DPU_VSYNC_SOURCE_INTF_1 4 62 #define DPU_VSYNC_SOURCE_INTF_2 5 63 #define DPU_VSYNC_SOURCE_INTF_3 6 64 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 65 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 66 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 67 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 68 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 69 70 enum dpu_hw_blk_type { 71 DPU_HW_BLK_TOP = 0, 72 DPU_HW_BLK_SSPP, 73 DPU_HW_BLK_LM, 74 DPU_HW_BLK_CTL, 75 DPU_HW_BLK_PINGPONG, 76 DPU_HW_BLK_INTF, 77 DPU_HW_BLK_WB, 78 DPU_HW_BLK_DSPP, 79 DPU_HW_BLK_MERGE_3D, 80 DPU_HW_BLK_DSC, 81 DPU_HW_BLK_CDM, 82 DPU_HW_BLK_MAX, 83 }; 84 85 enum dpu_sspp { 86 SSPP_NONE, 87 SSPP_VIG0, 88 SSPP_VIG1, 89 SSPP_VIG2, 90 SSPP_VIG3, 91 SSPP_RGB0, 92 SSPP_RGB1, 93 SSPP_RGB2, 94 SSPP_RGB3, 95 SSPP_DMA0, 96 SSPP_DMA1, 97 SSPP_DMA2, 98 SSPP_DMA3, 99 SSPP_DMA4, 100 SSPP_DMA5, 101 SSPP_CURSOR0, 102 SSPP_CURSOR1, 103 SSPP_MAX 104 }; 105 106 enum dpu_sspp_type { 107 SSPP_TYPE_VIG, 108 SSPP_TYPE_RGB, 109 SSPP_TYPE_DMA, 110 SSPP_TYPE_CURSOR, 111 SSPP_TYPE_MAX 112 }; 113 114 enum dpu_lm { 115 LM_0 = 1, 116 LM_1, 117 LM_2, 118 LM_3, 119 LM_4, 120 LM_5, 121 LM_6, 122 LM_MAX 123 }; 124 125 enum dpu_stage { 126 DPU_STAGE_BASE = 0, 127 DPU_STAGE_0, 128 DPU_STAGE_1, 129 DPU_STAGE_2, 130 DPU_STAGE_3, 131 DPU_STAGE_4, 132 DPU_STAGE_5, 133 DPU_STAGE_6, 134 DPU_STAGE_7, 135 DPU_STAGE_8, 136 DPU_STAGE_9, 137 DPU_STAGE_10, 138 DPU_STAGE_MAX 139 }; 140 enum dpu_dspp { 141 DSPP_0 = 1, 142 DSPP_1, 143 DSPP_2, 144 DSPP_3, 145 DSPP_MAX 146 }; 147 148 enum dpu_ctl { 149 CTL_0 = 1, 150 CTL_1, 151 CTL_2, 152 CTL_3, 153 CTL_4, 154 CTL_5, 155 CTL_MAX 156 }; 157 158 enum dpu_dsc { 159 DSC_NONE = 0, 160 DSC_0, 161 DSC_1, 162 DSC_2, 163 DSC_3, 164 DSC_4, 165 DSC_5, 166 DSC_MAX 167 }; 168 169 enum dpu_cdm { 170 CDM_0 = 1, 171 CDM_MAX 172 }; 173 174 enum dpu_pingpong { 175 PINGPONG_NONE, 176 PINGPONG_0, 177 PINGPONG_1, 178 PINGPONG_2, 179 PINGPONG_3, 180 PINGPONG_4, 181 PINGPONG_5, 182 PINGPONG_6, 183 PINGPONG_7, 184 PINGPONG_8, 185 PINGPONG_9, 186 PINGPONG_S0, 187 PINGPONG_MAX 188 }; 189 190 enum dpu_merge_3d { 191 MERGE_3D_0 = 1, 192 MERGE_3D_1, 193 MERGE_3D_2, 194 MERGE_3D_3, 195 MERGE_3D_4, 196 MERGE_3D_MAX 197 }; 198 199 enum dpu_intf { 200 INTF_0 = 1, 201 INTF_1, 202 INTF_2, 203 INTF_3, 204 INTF_4, 205 INTF_5, 206 INTF_6, 207 INTF_7, 208 INTF_8, 209 INTF_MAX 210 }; 211 212 /* 213 * Historically these values correspond to the values written to the 214 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 215 * generations this register is NOP, but we keep the values for historical 216 * reasons. 217 */ 218 enum dpu_intf_type { 219 INTF_NONE = 0x0, 220 INTF_DSI = 0x1, 221 INTF_HDMI = 0x3, 222 INTF_LCDC = 0x5, 223 /* old eDP found on 8x74 and 8x84 */ 224 INTF_EDP = 0x9, 225 /* both DP and eDP, handled by the new DP driver */ 226 INTF_DP = 0xa, 227 228 /* virtual interfaces */ 229 INTF_WB = 0x100, 230 }; 231 232 enum dpu_intf_mode { 233 INTF_MODE_NONE = 0, 234 INTF_MODE_CMD, 235 INTF_MODE_VIDEO, 236 INTF_MODE_WB_BLOCK, 237 INTF_MODE_WB_LINE, 238 INTF_MODE_MAX 239 }; 240 241 enum dpu_wb { 242 WB_0 = 1, 243 WB_1, 244 WB_2, 245 WB_3, 246 WB_MAX 247 }; 248 249 enum dpu_cwb { 250 CWB_0 = 0x1, 251 CWB_1, 252 CWB_2, 253 CWB_3, 254 CWB_MAX 255 }; 256 257 enum dpu_wd_timer { 258 WD_TIMER_0 = 0x1, 259 WD_TIMER_1, 260 WD_TIMER_2, 261 WD_TIMER_3, 262 WD_TIMER_4, 263 WD_TIMER_5, 264 WD_TIMER_MAX 265 }; 266 267 enum dpu_vbif { 268 VBIF_RT, 269 VBIF_NRT, 270 VBIF_MAX, 271 }; 272 273 /** 274 * enum dpu_3d_blend_mode 275 * Desribes how the 3d data is blended 276 * @BLEND_3D_NONE : 3d blending not enabled 277 * @BLEND_3D_FRAME_INT : Frame interleaving 278 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 279 * @BLEND_3D_V_ROW_INT : vertical row interleaving 280 * @BLEND_3D_COL_INT : column interleaving 281 * @BLEND_3D_MAX : 282 */ 283 enum dpu_3d_blend_mode { 284 BLEND_3D_NONE = 0, 285 BLEND_3D_FRAME_INT, 286 BLEND_3D_H_ROW_INT, 287 BLEND_3D_V_ROW_INT, 288 BLEND_3D_COL_INT, 289 BLEND_3D_MAX 290 }; 291 292 /** 293 * struct dpu_hw_fmt_layout - format information of the source pixel data 294 * @format: pixel format parameters 295 * @num_planes: number of planes (including meta data planes) 296 * @width: image width 297 * @height: image height 298 * @total_size: total size in bytes 299 * @plane_addr: address of each plane 300 * @plane_size: length of each plane 301 * @plane_pitch: pitch of each plane 302 */ 303 struct dpu_hw_fmt_layout { 304 const struct msm_format *format; 305 uint32_t num_planes; 306 uint32_t width; 307 uint32_t height; 308 uint32_t total_size; 309 uint32_t plane_addr[DPU_MAX_PLANES]; 310 uint32_t plane_size[DPU_MAX_PLANES]; 311 uint32_t plane_pitch[DPU_MAX_PLANES]; 312 }; 313 314 struct dpu_csc_cfg { 315 /* matrix coefficients in S15.16 format */ 316 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 317 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 318 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 319 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 320 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 321 }; 322 323 /** 324 * struct dpu_mdss_color - mdss color description 325 * color 0 : green 326 * color 1 : blue 327 * color 2 : red 328 * color 3 : alpha 329 */ 330 struct dpu_mdss_color { 331 u32 color_0; 332 u32 color_1; 333 u32 color_2; 334 u32 color_3; 335 }; 336 337 /* 338 * Define bit masks for h/w logging. 339 */ 340 #define DPU_DBG_MASK_NONE (1 << 0) 341 #define DPU_DBG_MASK_INTF (1 << 1) 342 #define DPU_DBG_MASK_LM (1 << 2) 343 #define DPU_DBG_MASK_CTL (1 << 3) 344 #define DPU_DBG_MASK_PINGPONG (1 << 4) 345 #define DPU_DBG_MASK_SSPP (1 << 5) 346 #define DPU_DBG_MASK_WB (1 << 6) 347 #define DPU_DBG_MASK_TOP (1 << 7) 348 #define DPU_DBG_MASK_VBIF (1 << 8) 349 #define DPU_DBG_MASK_ROT (1 << 9) 350 #define DPU_DBG_MASK_DSPP (1 << 10) 351 #define DPU_DBG_MASK_DSC (1 << 11) 352 #define DPU_DBG_MASK_CDM (1 << 12) 353 354 /** 355 * struct dpu_hw_tear_check - Struct contains parameters to configure 356 * tear-effect module. This structure is used to configure tear-check 357 * logic present either in ping-pong or in interface module. 358 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 359 * by no of lines 360 * @sync_cfg_height: Total vertical lines (display height - 1) 361 * @vsync_init_val: Init value to which the read pointer gets loaded at 362 * vsync edge 363 * @sync_threshold_start: Read pointer threshold start ROI for write operation 364 * @sync_threshold_continue: The minimum number of lines the write pointer 365 * needs to be above the read pointer 366 * @start_pos: The position from which the start_threshold value is added 367 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 368 * @hw_vsync_mode: Sync with external frame sync input 369 */ 370 struct dpu_hw_tear_check { 371 /* 372 * This is ratio of MDP VSYNC clk freq(Hz) to 373 * refresh rate divided by no of lines 374 */ 375 u32 vsync_count; 376 u32 sync_cfg_height; 377 u32 vsync_init_val; 378 u32 sync_threshold_start; 379 u32 sync_threshold_continue; 380 u32 start_pos; 381 u32 rd_ptr_irq; 382 u8 hw_vsync_mode; 383 }; 384 385 /** 386 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 387 * read and write pointers for command mode panels 388 * @rd_ptr_init_val: Value of rd pointer at vsync edge 389 * @rd_ptr_frame_count: Num frames sent since enabling interface 390 * @rd_ptr_line_count: Current line on panel (rd ptr) 391 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 392 * @intf_frame_count: Frames read from intf 393 */ 394 struct dpu_hw_pp_vsync_info { 395 u32 rd_ptr_init_val; 396 u32 rd_ptr_frame_count; 397 u32 rd_ptr_line_count; 398 u32 wr_ptr_line_count; 399 u32 intf_frame_count; 400 }; 401 402 #endif /* _DPU_HW_MDSS_H */ 403