1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_LM_H 8 #define _DPU_HW_LM_H 9 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_util.h" 12 13 struct dpu_hw_mixer; 14 struct dpu_hw_stage_cfg; 15 16 struct dpu_hw_mixer_cfg { 17 u32 out_width; 18 u32 out_height; 19 bool right_mixer; 20 int flags; 21 }; 22 23 struct dpu_hw_color3_cfg { 24 u8 keep_fg[DPU_STAGE_MAX]; 25 }; 26 27 /** 28 * 29 * struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions 30 * Assumption is these functions will be called after clocks are enabled 31 */ 32 struct dpu_hw_lm_ops { 33 /* 34 * Sets up mixer output width and height 35 * and border color if enabled 36 */ 37 void (*setup_mixer_out)(struct dpu_hw_mixer *ctx, 38 struct dpu_hw_mixer_cfg *cfg); 39 40 /* 41 * Alpha blending configuration 42 * for the specified stage 43 */ 44 void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage, 45 uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); 46 47 /* 48 * Alpha color component selection from either fg or bg 49 */ 50 void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); 51 52 /** 53 * Clear layer mixer to pipe configuration 54 * @ctx : mixer ctx pointer 55 * Returns: 0 on success or -error 56 */ 57 int (*clear_all_blendstages)(struct dpu_hw_mixer *ctx); 58 59 /** 60 * Configure layer mixer to pipe configuration 61 * @ctx : mixer ctx pointer 62 * @lm : layer mixer enumeration 63 * @stage_cfg : blend stage configuration 64 * Returns: 0 on success or -error 65 */ 66 int (*setup_blendstage)(struct dpu_hw_mixer *ctx, enum dpu_lm lm, 67 struct dpu_hw_stage_cfg *stage_cfg); 68 69 /** 70 * setup_border_color : enable/disable border color 71 */ 72 void (*setup_border_color)(struct dpu_hw_mixer *ctx, 73 struct dpu_mdss_color *color, 74 u8 border_en); 75 76 /** 77 * setup_misr: Enable/disable MISR 78 */ 79 void (*setup_misr)(struct dpu_hw_mixer *ctx); 80 81 /** 82 * collect_misr: Read MISR signature 83 */ 84 int (*collect_misr)(struct dpu_hw_mixer *ctx, u32 *misr_value); 85 }; 86 87 struct dpu_hw_mixer { 88 struct dpu_hw_blk base; 89 struct dpu_hw_blk_reg_map hw; 90 91 /* lm */ 92 enum dpu_lm idx; 93 const struct dpu_lm_cfg *cap; 94 const struct dpu_mdp_cfg *mdp; 95 const struct dpu_ctl_cfg *ctl; 96 97 /* ops */ 98 struct dpu_hw_lm_ops ops; 99 100 /* store mixer info specific to display */ 101 struct dpu_hw_mixer_cfg cfg; 102 }; 103 104 /** 105 * to_dpu_hw_mixer - convert base object dpu_hw_base to container 106 * @hw: Pointer to base hardware block 107 * return: Pointer to hardware block container 108 */ 109 static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) 110 { 111 return container_of(hw, struct dpu_hw_mixer, base); 112 } 113 114 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 115 const struct dpu_lm_cfg *cfg, 116 void __iomem *addr, 117 const struct dpu_mdss_version *mdss_ver); 118 119 #endif /*_DPU_HW_LM_H */ 120