xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_HW_INTF_H
8 #define _DPU_HW_INTF_H
9 
10 #include "dpu_hw_catalog.h"
11 #include "dpu_hw_mdss.h"
12 #include "dpu_hw_util.h"
13 
14 struct dpu_hw_intf;
15 
16 /* intf timing settings */
17 struct dpu_hw_intf_timing_params {
18 	u32 width;		/* active width */
19 	u32 height;		/* active height */
20 	u32 xres;		/* Display panel width */
21 	u32 yres;		/* Display panel height */
22 
23 	u32 h_back_porch;
24 	u32 h_front_porch;
25 	u32 v_back_porch;
26 	u32 v_front_porch;
27 	u32 hsync_pulse_width;
28 	u32 vsync_pulse_width;
29 	u32 hsync_polarity;
30 	u32 vsync_polarity;
31 	u32 border_clr;
32 	u32 underflow_clr;
33 	u32 hsync_skew;
34 
35 	bool wide_bus_en;
36 };
37 
38 struct dpu_hw_intf_prog_fetch {
39 	u8 enable;
40 	/* vsync counter for the front porch pixel line */
41 	u32 fetch_start;
42 };
43 
44 struct dpu_hw_intf_status {
45 	u8 is_en;		/* interface timing engine is enabled or not */
46 	u8 is_prog_fetch_en;	/* interface prog fetch counter is enabled or not */
47 	u32 frame_count;	/* frame count since timing engine enabled */
48 	u32 line_count;		/* current line count including blanking */
49 };
50 
51 struct dpu_hw_intf_cmd_mode_cfg {
52 	u8 data_compress;	/* enable data compress between dpu and dsi */
53 	u8 wide_bus_en;		/* enable databus widen mode */
54 };
55 
56 /**
57  * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
58  *  Assumption is these functions will be called after clocks are enabled
59  * @ setup_timing_gen : programs the timing engine
60  * @ setup_prog_fetch : enables/disables the programmable fetch logic
61  * @ enable_timing: enable/disable timing engine
62  * @ get_status: returns if timing engine is enabled or not
63  * @ get_line_count: reads current vertical line counter
64  * @bind_pingpong_blk: enable/disable the connection with pingpong which will
65  *                     feed pixels to this interface
66  * @setup_misr: enable/disable MISR
67  * @collect_misr: read MISR signature
68  * @enable_tearcheck:           Enables vsync generation and sets up init value of read
69  *                              pointer and programs the tear check configuration
70  * @disable_tearcheck:          Disables tearcheck block
71  * @connect_external_te:        Read, modify, write to either set or clear listening to external TE
72  *                              Return: 1 if TE was originally connected, 0 if not, or -ERROR
73  * @get_vsync_info:             Provides the programmed and current line_count
74  * @setup_autorefresh:          Configure and enable the autorefresh config
75  * @get_autorefresh:            Retrieve autorefresh config from hardware
76  *                              Return: 0 on success, -ETIMEDOUT on timeout
77  * @vsync_sel:                  Select vsync signal for tear-effect configuration
78  * @program_intf_cmd_cfg:       Program the DPU to interface datapath for command mode
79  */
80 struct dpu_hw_intf_ops {
81 	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
82 			const struct dpu_hw_intf_timing_params *p,
83 			const struct dpu_format *fmt);
84 
85 	void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
86 			const struct dpu_hw_intf_prog_fetch *fetch);
87 
88 	void (*enable_timing)(struct dpu_hw_intf *intf,
89 			u8 enable);
90 
91 	void (*get_status)(struct dpu_hw_intf *intf,
92 			struct dpu_hw_intf_status *status);
93 
94 	u32 (*get_line_count)(struct dpu_hw_intf *intf);
95 
96 	void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
97 			const enum dpu_pingpong pp);
98 	void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
99 	int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
100 
101 	// Tearcheck on INTF since DPU 5.0.0
102 
103 	int (*enable_tearcheck)(struct dpu_hw_intf *intf, struct dpu_hw_tear_check *cfg);
104 
105 	int (*disable_tearcheck)(struct dpu_hw_intf *intf);
106 
107 	int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te);
108 
109 	void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
110 
111 	/**
112 	 * Disable autorefresh if enabled
113 	 */
114 	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
115 
116 	void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
117 				     struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg);
118 };
119 
120 struct dpu_hw_intf {
121 	struct dpu_hw_blk_reg_map hw;
122 
123 	/* intf */
124 	enum dpu_intf idx;
125 	const struct dpu_intf_cfg *cap;
126 
127 	/* ops */
128 	struct dpu_hw_intf_ops ops;
129 };
130 
131 /**
132  * dpu_hw_intf_init() - Initializes the INTF driver for the passed
133  * interface catalog entry.
134  * @cfg:  interface catalog entry for which driver object is required
135  * @addr: mapped register io address of MDP
136  * @mdss_rev: dpu core's major and minor versions
137  */
138 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
139 		void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
140 
141 /**
142  * dpu_hw_intf_destroy(): Destroys INTF driver context
143  * @intf:   Pointer to INTF driver context
144  */
145 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);
146 
147 #endif /*_DPU_HW_INTF_H */
148