1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_INTF_H 8 #define _DPU_HW_INTF_H 9 10 #include "dpu_hw_catalog.h" 11 #include "dpu_hw_mdss.h" 12 #include "dpu_hw_util.h" 13 14 struct dpu_hw_intf; 15 16 /* intf timing settings */ 17 struct intf_timing_params { 18 u32 width; /* active width */ 19 u32 height; /* active height */ 20 u32 xres; /* Display panel width */ 21 u32 yres; /* Display panel height */ 22 23 u32 h_back_porch; 24 u32 h_front_porch; 25 u32 v_back_porch; 26 u32 v_front_porch; 27 u32 hsync_pulse_width; 28 u32 vsync_pulse_width; 29 u32 hsync_polarity; 30 u32 vsync_polarity; 31 u32 border_clr; 32 u32 underflow_clr; 33 u32 hsync_skew; 34 35 bool wide_bus_en; 36 }; 37 38 struct intf_prog_fetch { 39 u8 enable; 40 /* vsync counter for the front porch pixel line */ 41 u32 fetch_start; 42 }; 43 44 struct intf_status { 45 u8 is_en; /* interface timing engine is enabled or not */ 46 u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */ 47 u32 frame_count; /* frame count since timing engine enabled */ 48 u32 line_count; /* current line count including blanking */ 49 }; 50 51 /** 52 * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions 53 * Assumption is these functions will be called after clocks are enabled 54 * @ setup_timing_gen : programs the timing engine 55 * @ setup_prog_fetch : enables/disables the programmable fetch logic 56 * @ enable_timing: enable/disable timing engine 57 * @ get_status: returns if timing engine is enabled or not 58 * @ get_line_count: reads current vertical line counter 59 * @bind_pingpong_blk: enable/disable the connection with pingpong which will 60 * feed pixels to this interface 61 * @setup_misr: enable/disable MISR 62 * @collect_misr: read MISR signature 63 */ 64 struct dpu_hw_intf_ops { 65 void (*setup_timing_gen)(struct dpu_hw_intf *intf, 66 const struct intf_timing_params *p, 67 const struct dpu_format *fmt); 68 69 void (*setup_prg_fetch)(struct dpu_hw_intf *intf, 70 const struct intf_prog_fetch *fetch); 71 72 void (*enable_timing)(struct dpu_hw_intf *intf, 73 u8 enable); 74 75 void (*get_status)(struct dpu_hw_intf *intf, 76 struct intf_status *status); 77 78 u32 (*get_line_count)(struct dpu_hw_intf *intf); 79 80 void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, 81 bool enable, 82 const enum dpu_pingpong pp); 83 void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); 84 int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); 85 }; 86 87 struct dpu_hw_intf { 88 struct dpu_hw_blk_reg_map hw; 89 90 /* intf */ 91 enum dpu_intf idx; 92 const struct dpu_intf_cfg *cap; 93 const struct dpu_mdss_cfg *mdss; 94 95 /* ops */ 96 struct dpu_hw_intf_ops ops; 97 }; 98 99 /** 100 * dpu_hw_intf_init(): Initializes the intf driver for the passed 101 * interface idx. 102 * @idx: interface index for which driver object is required 103 * @addr: mapped register io address of MDP 104 * @m : pointer to mdss catalog data 105 */ 106 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, 107 void __iomem *addr, 108 const struct dpu_mdss_cfg *m); 109 110 /** 111 * dpu_hw_intf_destroy(): Destroys INTF driver context 112 * @intf: Pointer to INTF driver context 113 */ 114 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf); 115 116 #endif /*_DPU_HW_INTF_H */ 117