1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_intf.h" 10 #include "dpu_kms.h" 11 #include "dpu_trace.h" 12 13 #include <linux/iopoll.h> 14 15 #include <drm/drm_managed.h> 16 17 #define INTF_TIMING_ENGINE_EN 0x000 18 #define INTF_CONFIG 0x004 19 #define INTF_HSYNC_CTL 0x008 20 #define INTF_VSYNC_PERIOD_F0 0x00C 21 #define INTF_VSYNC_PERIOD_F1 0x010 22 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 23 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 24 #define INTF_DISPLAY_V_START_F0 0x01C 25 #define INTF_DISPLAY_V_START_F1 0x020 26 #define INTF_DISPLAY_V_END_F0 0x024 27 #define INTF_DISPLAY_V_END_F1 0x028 28 #define INTF_ACTIVE_V_START_F0 0x02C 29 #define INTF_ACTIVE_V_START_F1 0x030 30 #define INTF_ACTIVE_V_END_F0 0x034 31 #define INTF_ACTIVE_V_END_F1 0x038 32 #define INTF_DISPLAY_HCTL 0x03C 33 #define INTF_ACTIVE_HCTL 0x040 34 #define INTF_BORDER_COLOR 0x044 35 #define INTF_UNDERFLOW_COLOR 0x048 36 #define INTF_HSYNC_SKEW 0x04C 37 #define INTF_POLARITY_CTL 0x050 38 #define INTF_TEST_CTL 0x054 39 #define INTF_TP_COLOR0 0x058 40 #define INTF_TP_COLOR1 0x05C 41 #define INTF_CONFIG2 0x060 42 #define INTF_DISPLAY_DATA_HCTL 0x064 43 #define INTF_ACTIVE_DATA_HCTL 0x068 44 45 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 46 #define INTF_PANEL_FORMAT 0x090 47 48 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 49 #define INTF_FRAME_COUNT 0x0AC 50 #define INTF_LINE_COUNT 0x0B0 51 52 #define INTF_DEFLICKER_CONFIG 0x0F0 53 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 54 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 55 56 #define INTF_TPG_ENABLE 0x100 57 #define INTF_TPG_MAIN_CONTROL 0x104 58 #define INTF_TPG_VIDEO_CONFIG 0x108 59 #define INTF_TPG_COMPONENT_LIMITS 0x10C 60 #define INTF_TPG_RECTANGLE 0x110 61 #define INTF_TPG_INITIAL_VALUE 0x114 62 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 63 #define INTF_TPG_RGB_MAPPING 0x11C 64 #define INTF_PROG_FETCH_START 0x170 65 #define INTF_PROG_ROT_START 0x174 66 67 #define INTF_MISR_CTRL 0x180 68 #define INTF_MISR_SIGNATURE 0x184 69 70 #define INTF_MUX 0x25C 71 #define INTF_STATUS 0x26C 72 #define INTF_AVR_CONTROL 0x270 73 #define INTF_AVR_MODE 0x274 74 #define INTF_AVR_TRIGGER 0x278 75 #define INTF_AVR_VTOTAL 0x27C 76 #define INTF_TEAR_MDP_VSYNC_SEL 0x280 77 #define INTF_TEAR_TEAR_CHECK_EN 0x284 78 #define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288 79 #define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C 80 #define INTF_TEAR_SYNC_WRCOUNT 0x290 81 #define INTF_TEAR_VSYNC_INIT_VAL 0x294 82 #define INTF_TEAR_INT_COUNT_VAL 0x298 83 #define INTF_TEAR_SYNC_THRESH 0x29C 84 #define INTF_TEAR_START_POS 0x2A0 85 #define INTF_TEAR_RD_PTR_IRQ 0x2A4 86 #define INTF_TEAR_WR_PTR_IRQ 0x2A8 87 #define INTF_TEAR_OUT_LINE_COUNT 0x2AC 88 #define INTF_TEAR_LINE_COUNT 0x2B0 89 #define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4 90 91 #define INTF_CFG_ACTIVE_H_EN BIT(29) 92 #define INTF_CFG_ACTIVE_V_EN BIT(30) 93 94 #define INTF_CFG2_DATABUS_WIDEN BIT(0) 95 #define INTF_CFG2_DATA_HCTL_EN BIT(4) 96 #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) 97 98 99 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 100 const struct dpu_hw_intf_timing_params *p, 101 const struct dpu_format *fmt) 102 { 103 struct dpu_hw_blk_reg_map *c = &ctx->hw; 104 u32 hsync_period, vsync_period; 105 u32 display_v_start, display_v_end; 106 u32 hsync_start_x, hsync_end_x; 107 u32 hsync_data_start_x, hsync_data_end_x; 108 u32 active_h_start, active_h_end; 109 u32 active_v_start, active_v_end; 110 u32 active_hctl, display_hctl, hsync_ctl; 111 u32 polarity_ctl, den_polarity; 112 u32 panel_format; 113 u32 intf_cfg, intf_cfg2 = 0; 114 u32 display_data_hctl = 0, active_data_hctl = 0; 115 u32 data_width; 116 bool dp_intf = false; 117 118 /* read interface_cfg */ 119 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 120 121 if (ctx->cap->type == INTF_DP) 122 dp_intf = true; 123 124 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 125 p->h_front_porch; 126 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 127 p->v_front_porch; 128 129 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 130 hsync_period) + p->hsync_skew; 131 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 132 p->hsync_skew - 1; 133 134 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 135 hsync_end_x = hsync_period - p->h_front_porch - 1; 136 137 if (p->width != p->xres) { /* border fill added */ 138 active_h_start = hsync_start_x; 139 active_h_end = active_h_start + p->xres - 1; 140 } else { 141 active_h_start = 0; 142 active_h_end = 0; 143 } 144 145 if (p->height != p->yres) { /* border fill added */ 146 active_v_start = display_v_start; 147 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 148 } else { 149 active_v_start = 0; 150 active_v_end = 0; 151 } 152 153 if (active_h_end) { 154 active_hctl = (active_h_end << 16) | active_h_start; 155 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 156 } else { 157 active_hctl = 0; 158 } 159 160 if (active_v_end) 161 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 162 163 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 164 display_hctl = (hsync_end_x << 16) | hsync_start_x; 165 166 /* 167 * DATA_HCTL_EN controls data timing which can be different from 168 * video timing. It is recommended to enable it for all cases, except 169 * if compression is enabled in 1 pixel per clock mode 170 */ 171 if (p->wide_bus_en) 172 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; 173 174 data_width = p->width; 175 176 hsync_data_start_x = hsync_start_x; 177 hsync_data_end_x = hsync_start_x + data_width - 1; 178 179 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 180 181 if (dp_intf) { 182 /* DP timing adjustment */ 183 display_v_start += p->hsync_pulse_width + p->h_back_porch; 184 display_v_end -= p->h_front_porch; 185 186 active_h_start = hsync_start_x; 187 active_h_end = active_h_start + p->xres - 1; 188 active_v_start = display_v_start; 189 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 190 191 active_hctl = (active_h_end << 16) | active_h_start; 192 display_hctl = active_hctl; 193 194 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 195 } 196 197 den_polarity = 0; 198 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 199 (p->vsync_polarity << 1) | /* VSYNC Polarity */ 200 (p->hsync_polarity << 0); /* HSYNC Polarity */ 201 202 if (!DPU_FORMAT_IS_YUV(fmt)) 203 panel_format = (fmt->bits[C0_G_Y] | 204 (fmt->bits[C1_B_Cb] << 2) | 205 (fmt->bits[C2_R_Cr] << 4) | 206 (0x21 << 8)); 207 else 208 /* Interface treats all the pixel data in RGB888 format */ 209 panel_format = (COLOR_8BIT | 210 (COLOR_8BIT << 2) | 211 (COLOR_8BIT << 4) | 212 (0x21 << 8)); 213 214 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 215 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 216 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 217 p->vsync_pulse_width * hsync_period); 218 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 219 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 220 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 221 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 222 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 223 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 224 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 225 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 226 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 227 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 228 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 229 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 230 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 231 if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { 232 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 233 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 234 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 235 } 236 } 237 238 static void dpu_hw_intf_enable_timing_engine( 239 struct dpu_hw_intf *intf, 240 u8 enable) 241 { 242 struct dpu_hw_blk_reg_map *c = &intf->hw; 243 /* Note: Display interface select is handled in top block hw layer */ 244 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 245 } 246 247 static void dpu_hw_intf_setup_prg_fetch( 248 struct dpu_hw_intf *intf, 249 const struct dpu_hw_intf_prog_fetch *fetch) 250 { 251 struct dpu_hw_blk_reg_map *c = &intf->hw; 252 int fetch_enable; 253 254 /* 255 * Fetch should always be outside the active lines. If the fetching 256 * is programmed within active region, hardware behavior is unknown. 257 */ 258 259 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 260 if (fetch->enable) { 261 fetch_enable |= BIT(31); 262 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 263 fetch->fetch_start); 264 } else { 265 fetch_enable &= ~BIT(31); 266 } 267 268 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 269 } 270 271 static void dpu_hw_intf_bind_pingpong_blk( 272 struct dpu_hw_intf *intf, 273 const enum dpu_pingpong pp) 274 { 275 struct dpu_hw_blk_reg_map *c = &intf->hw; 276 u32 mux_cfg; 277 278 mux_cfg = DPU_REG_READ(c, INTF_MUX); 279 mux_cfg &= ~0xf; 280 281 if (pp) 282 mux_cfg |= (pp - PINGPONG_0) & 0x7; 283 else 284 mux_cfg |= 0xf; 285 286 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 287 } 288 289 static void dpu_hw_intf_get_status( 290 struct dpu_hw_intf *intf, 291 struct dpu_hw_intf_status *s) 292 { 293 struct dpu_hw_blk_reg_map *c = &intf->hw; 294 unsigned long cap = intf->cap->features; 295 296 if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) 297 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); 298 else 299 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 300 301 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 302 if (s->is_en) { 303 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 304 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 305 } else { 306 s->line_count = 0; 307 s->frame_count = 0; 308 } 309 } 310 311 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 312 { 313 struct dpu_hw_blk_reg_map *c; 314 315 if (!intf) 316 return 0; 317 318 c = &intf->hw; 319 320 return DPU_REG_READ(c, INTF_LINE_COUNT); 321 } 322 323 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf) 324 { 325 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1); 326 } 327 328 static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 329 { 330 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 331 } 332 333 static int dpu_hw_intf_enable_te(struct dpu_hw_intf *intf, 334 struct dpu_hw_tear_check *te) 335 { 336 struct dpu_hw_blk_reg_map *c; 337 int cfg; 338 339 if (!intf) 340 return -EINVAL; 341 342 c = &intf->hw; 343 344 cfg = BIT(19); /* VSYNC_COUNTER_EN */ 345 if (te->hw_vsync_mode) 346 cfg |= BIT(20); 347 348 cfg |= te->vsync_count; 349 350 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 351 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); 352 DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val); 353 DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq); 354 DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos); 355 DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, 356 ((te->sync_threshold_continue << 16) | 357 te->sync_threshold_start)); 358 DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, 359 (te->start_pos + te->sync_threshold_start + 1)); 360 361 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1); 362 363 return 0; 364 } 365 366 static void dpu_hw_intf_setup_autorefresh_config(struct dpu_hw_intf *intf, 367 u32 frame_count, bool enable) 368 { 369 struct dpu_hw_blk_reg_map *c; 370 u32 refresh_cfg; 371 372 c = &intf->hw; 373 refresh_cfg = DPU_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG); 374 if (enable) 375 refresh_cfg = BIT(31) | frame_count; 376 else 377 refresh_cfg &= ~BIT(31); 378 379 DPU_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg); 380 } 381 382 /* 383 * dpu_hw_intf_get_autorefresh_config - Get autorefresh config from HW 384 * @intf: DPU intf structure 385 * @frame_count: Used to return the current frame count from hw 386 * 387 * Returns: True if autorefresh enabled, false if disabled. 388 */ 389 static bool dpu_hw_intf_get_autorefresh_config(struct dpu_hw_intf *intf, 390 u32 *frame_count) 391 { 392 u32 val = DPU_REG_READ(&intf->hw, INTF_TEAR_AUTOREFRESH_CONFIG); 393 394 if (frame_count != NULL) 395 *frame_count = val & 0xffff; 396 return !!((val & BIT(31)) >> 31); 397 } 398 399 static int dpu_hw_intf_disable_te(struct dpu_hw_intf *intf) 400 { 401 struct dpu_hw_blk_reg_map *c; 402 403 if (!intf) 404 return -EINVAL; 405 406 c = &intf->hw; 407 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 0); 408 return 0; 409 } 410 411 static int dpu_hw_intf_connect_external_te(struct dpu_hw_intf *intf, 412 bool enable_external_te) 413 { 414 struct dpu_hw_blk_reg_map *c = &intf->hw; 415 u32 cfg; 416 int orig; 417 418 if (!intf) 419 return -EINVAL; 420 421 c = &intf->hw; 422 cfg = DPU_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC); 423 orig = (bool)(cfg & BIT(20)); 424 if (enable_external_te) 425 cfg |= BIT(20); 426 else 427 cfg &= ~BIT(20); 428 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 429 trace_dpu_intf_connect_ext_te(intf->idx - INTF_0, cfg); 430 431 return orig; 432 } 433 434 static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf, 435 struct dpu_hw_pp_vsync_info *info) 436 { 437 struct dpu_hw_blk_reg_map *c = &intf->hw; 438 u32 val; 439 440 if (!intf || !info) 441 return -EINVAL; 442 443 c = &intf->hw; 444 445 val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); 446 info->rd_ptr_init_val = val & 0xffff; 447 448 val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); 449 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; 450 info->rd_ptr_line_count = val & 0xffff; 451 452 val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT); 453 info->wr_ptr_line_count = val & 0xffff; 454 455 val = DPU_REG_READ(c, INTF_FRAME_COUNT); 456 info->intf_frame_count = val; 457 458 return 0; 459 } 460 461 static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, 462 u32 vsync_source) 463 { 464 struct dpu_hw_blk_reg_map *c; 465 466 if (!intf) 467 return; 468 469 c = &intf->hw; 470 471 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); 472 } 473 474 static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, 475 uint32_t encoder_id, u16 vdisplay) 476 { 477 struct dpu_hw_pp_vsync_info info; 478 int trial = 0; 479 480 /* If autorefresh is already disabled, we have nothing to do */ 481 if (!dpu_hw_intf_get_autorefresh_config(intf, NULL)) 482 return; 483 484 /* 485 * If autorefresh is enabled, disable it and make sure it is safe to 486 * proceed with current frame commit/push. Sequence followed is, 487 * 1. Disable TE 488 * 2. Disable autorefresh config 489 * 4. Poll for frame transfer ongoing to be false 490 * 5. Enable TE back 491 */ 492 493 dpu_hw_intf_connect_external_te(intf, false); 494 dpu_hw_intf_setup_autorefresh_config(intf, 0, false); 495 496 do { 497 udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); 498 if ((trial * DPU_ENC_MAX_POLL_TIMEOUT_US) 499 > (KICKOFF_TIMEOUT_MS * USEC_PER_MSEC)) { 500 DPU_ERROR("enc%d intf%d disable autorefresh failed\n", 501 encoder_id, intf->idx - INTF_0); 502 break; 503 } 504 505 trial++; 506 507 dpu_hw_intf_get_vsync_info(intf, &info); 508 } while (info.wr_ptr_line_count > 0 && 509 info.wr_ptr_line_count < vdisplay); 510 511 dpu_hw_intf_connect_external_te(intf, true); 512 513 DPU_DEBUG("enc%d intf%d disabled autorefresh\n", 514 encoder_id, intf->idx - INTF_0); 515 516 } 517 518 static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, 519 struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) 520 { 521 u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); 522 523 if (cmd_mode_cfg->data_compress) 524 intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; 525 526 if (cmd_mode_cfg->wide_bus_en) 527 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 528 529 DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); 530 } 531 532 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 533 const struct dpu_intf_cfg *cfg, 534 void __iomem *addr, 535 const struct dpu_mdss_version *mdss_rev) 536 { 537 struct dpu_hw_intf *c; 538 539 if (cfg->type == INTF_NONE) { 540 DPU_DEBUG("Skip intf %d with type NONE\n", cfg->id - INTF_0); 541 return NULL; 542 } 543 544 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL); 545 if (!c) 546 return ERR_PTR(-ENOMEM); 547 548 c->hw.blk_addr = addr + cfg->base; 549 c->hw.log_mask = DPU_DBG_MASK_INTF; 550 551 /* 552 * Assign ops 553 */ 554 c->idx = cfg->id; 555 c->cap = cfg; 556 557 c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; 558 c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 559 c->ops.get_status = dpu_hw_intf_get_status; 560 c->ops.enable_timing = dpu_hw_intf_enable_timing_engine; 561 c->ops.get_line_count = dpu_hw_intf_get_line_count; 562 c->ops.setup_misr = dpu_hw_intf_setup_misr; 563 c->ops.collect_misr = dpu_hw_intf_collect_misr; 564 565 if (cfg->features & BIT(DPU_INTF_INPUT_CTRL)) 566 c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 567 568 /* INTF TE is only for DSI interfaces */ 569 if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { 570 WARN_ON(!cfg->intr_tear_rd_ptr); 571 572 c->ops.enable_tearcheck = dpu_hw_intf_enable_te; 573 c->ops.disable_tearcheck = dpu_hw_intf_disable_te; 574 c->ops.connect_external_te = dpu_hw_intf_connect_external_te; 575 c->ops.vsync_sel = dpu_hw_intf_vsync_sel; 576 c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh; 577 } 578 579 /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but 580 * we can configure it for DPU 7.0+ since the wide bus and DSC flags 581 * would not be set for DPU < 7.0 anyways 582 */ 583 if (mdss_rev->core_major_ver >= 7) 584 c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; 585 586 return c; 587 } 588