1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_intf.h" 10 #include "dpu_kms.h" 11 #include "dpu_trace.h" 12 13 #include <linux/iopoll.h> 14 15 #include <drm/drm_managed.h> 16 17 #define INTF_TIMING_ENGINE_EN 0x000 18 #define INTF_CONFIG 0x004 19 #define INTF_HSYNC_CTL 0x008 20 #define INTF_VSYNC_PERIOD_F0 0x00C 21 #define INTF_VSYNC_PERIOD_F1 0x010 22 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014 23 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018 24 #define INTF_DISPLAY_V_START_F0 0x01C 25 #define INTF_DISPLAY_V_START_F1 0x020 26 #define INTF_DISPLAY_V_END_F0 0x024 27 #define INTF_DISPLAY_V_END_F1 0x028 28 #define INTF_ACTIVE_V_START_F0 0x02C 29 #define INTF_ACTIVE_V_START_F1 0x030 30 #define INTF_ACTIVE_V_END_F0 0x034 31 #define INTF_ACTIVE_V_END_F1 0x038 32 #define INTF_DISPLAY_HCTL 0x03C 33 #define INTF_ACTIVE_HCTL 0x040 34 #define INTF_BORDER_COLOR 0x044 35 #define INTF_UNDERFLOW_COLOR 0x048 36 #define INTF_HSYNC_SKEW 0x04C 37 #define INTF_POLARITY_CTL 0x050 38 #define INTF_TEST_CTL 0x054 39 #define INTF_TP_COLOR0 0x058 40 #define INTF_TP_COLOR1 0x05C 41 #define INTF_CONFIG2 0x060 42 #define INTF_DISPLAY_DATA_HCTL 0x064 43 #define INTF_ACTIVE_DATA_HCTL 0x068 44 45 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 46 #define INTF_PANEL_FORMAT 0x090 47 48 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 49 #define INTF_FRAME_COUNT 0x0AC 50 #define INTF_LINE_COUNT 0x0B0 51 52 #define INTF_DEFLICKER_CONFIG 0x0F0 53 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 54 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 55 56 #define INTF_TPG_ENABLE 0x100 57 #define INTF_TPG_MAIN_CONTROL 0x104 58 #define INTF_TPG_VIDEO_CONFIG 0x108 59 #define INTF_TPG_COMPONENT_LIMITS 0x10C 60 #define INTF_TPG_RECTANGLE 0x110 61 #define INTF_TPG_INITIAL_VALUE 0x114 62 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118 63 #define INTF_TPG_RGB_MAPPING 0x11C 64 #define INTF_PROG_FETCH_START 0x170 65 #define INTF_PROG_ROT_START 0x174 66 67 #define INTF_MISR_CTRL 0x180 68 #define INTF_MISR_SIGNATURE 0x184 69 70 #define INTF_MUX 0x25C 71 #define INTF_STATUS 0x26C 72 #define INTF_AVR_CONTROL 0x270 73 #define INTF_AVR_MODE 0x274 74 #define INTF_AVR_TRIGGER 0x278 75 #define INTF_AVR_VTOTAL 0x27C 76 #define INTF_TEAR_MDP_VSYNC_SEL 0x280 77 #define INTF_TEAR_TEAR_CHECK_EN 0x284 78 #define INTF_TEAR_SYNC_CONFIG_VSYNC 0x288 79 #define INTF_TEAR_SYNC_CONFIG_HEIGHT 0x28C 80 #define INTF_TEAR_SYNC_WRCOUNT 0x290 81 #define INTF_TEAR_VSYNC_INIT_VAL 0x294 82 #define INTF_TEAR_INT_COUNT_VAL 0x298 83 #define INTF_TEAR_SYNC_THRESH 0x29C 84 #define INTF_TEAR_START_POS 0x2A0 85 #define INTF_TEAR_RD_PTR_IRQ 0x2A4 86 #define INTF_TEAR_WR_PTR_IRQ 0x2A8 87 #define INTF_TEAR_OUT_LINE_COUNT 0x2AC 88 #define INTF_TEAR_LINE_COUNT 0x2B0 89 #define INTF_TEAR_AUTOREFRESH_CONFIG 0x2B4 90 91 #define INTF_CFG_ACTIVE_H_EN BIT(29) 92 #define INTF_CFG_ACTIVE_V_EN BIT(30) 93 94 #define INTF_CFG2_DATABUS_WIDEN BIT(0) 95 #define INTF_CFG2_DATA_HCTL_EN BIT(4) 96 #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) 97 98 99 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, 100 const struct dpu_hw_intf_timing_params *p, 101 const struct msm_format *fmt) 102 { 103 struct dpu_hw_blk_reg_map *c = &intf->hw; 104 u32 hsync_period, vsync_period; 105 u32 display_v_start, display_v_end; 106 u32 hsync_start_x, hsync_end_x; 107 u32 hsync_data_start_x, hsync_data_end_x; 108 u32 active_h_start, active_h_end; 109 u32 active_v_start, active_v_end; 110 u32 active_hctl, display_hctl, hsync_ctl; 111 u32 polarity_ctl, den_polarity; 112 u32 panel_format; 113 u32 intf_cfg, intf_cfg2 = 0; 114 u32 display_data_hctl = 0, active_data_hctl = 0; 115 u32 data_width; 116 bool dp_intf = false; 117 118 /* read interface_cfg */ 119 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); 120 121 if (intf->cap->type == INTF_DP) 122 dp_intf = true; 123 124 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + 125 p->h_front_porch; 126 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + 127 p->v_front_porch; 128 129 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * 130 hsync_period) + p->hsync_skew; 131 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + 132 p->hsync_skew - 1; 133 134 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; 135 hsync_end_x = hsync_period - p->h_front_porch - 1; 136 137 if (p->width != p->xres) { /* border fill added */ 138 active_h_start = hsync_start_x; 139 active_h_end = active_h_start + p->xres - 1; 140 } else { 141 active_h_start = 0; 142 active_h_end = 0; 143 } 144 145 if (p->height != p->yres) { /* border fill added */ 146 active_v_start = display_v_start; 147 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 148 } else { 149 active_v_start = 0; 150 active_v_end = 0; 151 } 152 153 if (active_h_end) { 154 active_hctl = (active_h_end << 16) | active_h_start; 155 intf_cfg |= INTF_CFG_ACTIVE_H_EN; 156 } else { 157 active_hctl = 0; 158 } 159 160 if (active_v_end) 161 intf_cfg |= INTF_CFG_ACTIVE_V_EN; 162 163 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; 164 display_hctl = (hsync_end_x << 16) | hsync_start_x; 165 166 if (p->wide_bus_en) 167 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 168 169 data_width = p->width; 170 171 /* 172 * If widebus is enabled, data is valid for only half the active window 173 * since the data rate is doubled in this mode. But for the compression 174 * mode in DP case, the p->width is already adjusted in 175 * drm_mode_to_intf_timing_params() 176 */ 177 if (p->wide_bus_en && !dp_intf) 178 data_width = p->width >> 1; 179 180 /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ 181 if (p->compression_en && !dp_intf && 182 intf->mdss_ver->core_major_ver >= 7) 183 intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; 184 185 hsync_data_start_x = hsync_start_x; 186 hsync_data_end_x = hsync_start_x + data_width - 1; 187 188 display_data_hctl = (hsync_data_end_x << 16) | hsync_data_start_x; 189 190 if (dp_intf) { 191 /* DP timing adjustment */ 192 display_v_start += p->hsync_pulse_width + p->h_back_porch; 193 display_v_end -= p->h_front_porch; 194 195 active_h_start = hsync_start_x; 196 active_h_end = active_h_start + p->xres - 1; 197 active_v_start = display_v_start; 198 active_v_end = active_v_start + (p->yres * hsync_period) - 1; 199 200 active_hctl = (active_h_end << 16) | active_h_start; 201 display_hctl = active_hctl; 202 203 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; 204 } 205 206 den_polarity = 0; 207 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ 208 (p->vsync_polarity << 1) | /* VSYNC Polarity */ 209 (p->hsync_polarity << 0); /* HSYNC Polarity */ 210 211 if (!MSM_FORMAT_IS_YUV(fmt)) 212 panel_format = (fmt->bpc_g_y | 213 (fmt->bpc_b_cb << 2) | 214 (fmt->bpc_r_cr << 4) | 215 (0x21 << 8)); 216 else 217 /* Interface treats all the pixel data in RGB888 format */ 218 panel_format = (BPC8 | 219 (BPC8 << 2) | 220 (BPC8 << 4) | 221 (0x21 << 8)); 222 223 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); 224 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); 225 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, 226 p->vsync_pulse_width * hsync_period); 227 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); 228 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); 229 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); 230 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); 231 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); 232 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); 233 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); 234 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr); 235 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew); 236 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl); 237 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); 238 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); 239 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); 240 if (intf->mdss_ver->core_major_ver >= 5) { 241 /* 242 * DATA_HCTL_EN controls data timing which can be different from 243 * video timing. It is recommended to enable it for all cases, except 244 * if compression is enabled in 1 pixel per clock mode 245 */ 246 if (!(p->compression_en && !p->wide_bus_en)) 247 intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; 248 249 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); 250 DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); 251 DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); 252 } 253 } 254 255 static void dpu_hw_intf_enable_timing_engine( 256 struct dpu_hw_intf *intf, 257 u8 enable) 258 { 259 struct dpu_hw_blk_reg_map *c = &intf->hw; 260 /* Note: Display interface select is handled in top block hw layer */ 261 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); 262 } 263 264 static void dpu_hw_intf_setup_prg_fetch( 265 struct dpu_hw_intf *intf, 266 const struct dpu_hw_intf_prog_fetch *fetch) 267 { 268 struct dpu_hw_blk_reg_map *c = &intf->hw; 269 int fetch_enable; 270 271 /* 272 * Fetch should always be outside the active lines. If the fetching 273 * is programmed within active region, hardware behavior is unknown. 274 */ 275 276 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); 277 if (fetch->enable) { 278 fetch_enable |= BIT(31); 279 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, 280 fetch->fetch_start); 281 } else { 282 fetch_enable &= ~BIT(31); 283 } 284 285 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); 286 } 287 288 static void dpu_hw_intf_bind_pingpong_blk( 289 struct dpu_hw_intf *intf, 290 const enum dpu_pingpong pp) 291 { 292 struct dpu_hw_blk_reg_map *c = &intf->hw; 293 u32 mux_cfg; 294 295 mux_cfg = DPU_REG_READ(c, INTF_MUX); 296 mux_cfg &= ~0xf; 297 298 if (pp) 299 mux_cfg |= (pp - PINGPONG_0) & 0x7; 300 else 301 mux_cfg |= 0xf; 302 303 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); 304 } 305 306 static void dpu_hw_intf_get_status( 307 struct dpu_hw_intf *intf, 308 struct dpu_hw_intf_status *s) 309 { 310 struct dpu_hw_blk_reg_map *c = &intf->hw; 311 312 if (intf->mdss_ver->core_major_ver >= 5) 313 s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); 314 else 315 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); 316 317 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); 318 if (s->is_en) { 319 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); 320 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); 321 } else { 322 s->line_count = 0; 323 s->frame_count = 0; 324 } 325 } 326 327 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) 328 { 329 struct dpu_hw_blk_reg_map *c; 330 331 if (!intf) 332 return 0; 333 334 c = &intf->hw; 335 336 return DPU_REG_READ(c, INTF_LINE_COUNT); 337 } 338 339 static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf) 340 { 341 dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1); 342 } 343 344 static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) 345 { 346 return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); 347 } 348 349 static int dpu_hw_intf_enable_te(struct dpu_hw_intf *intf, 350 struct dpu_hw_tear_check *te) 351 { 352 struct dpu_hw_blk_reg_map *c; 353 int cfg; 354 355 if (!intf) 356 return -EINVAL; 357 358 c = &intf->hw; 359 360 cfg = BIT(19); /* VSYNC_COUNTER_EN */ 361 if (te->hw_vsync_mode) 362 cfg |= BIT(20); 363 364 cfg |= te->vsync_count; 365 366 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 367 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); 368 DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val); 369 DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq); 370 DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos); 371 DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, 372 ((te->sync_threshold_continue << 16) | 373 te->sync_threshold_start)); 374 DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, 375 (te->start_pos + te->sync_threshold_start + 1)); 376 377 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1); 378 379 return 0; 380 } 381 382 static void dpu_hw_intf_setup_autorefresh_config(struct dpu_hw_intf *intf, 383 u32 frame_count, bool enable) 384 { 385 struct dpu_hw_blk_reg_map *c; 386 u32 refresh_cfg; 387 388 c = &intf->hw; 389 refresh_cfg = DPU_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG); 390 if (enable) 391 refresh_cfg = BIT(31) | frame_count; 392 else 393 refresh_cfg &= ~BIT(31); 394 395 DPU_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg); 396 } 397 398 /* 399 * dpu_hw_intf_get_autorefresh_config - Get autorefresh config from HW 400 * @intf: DPU intf structure 401 * @frame_count: Used to return the current frame count from hw 402 * 403 * Returns: True if autorefresh enabled, false if disabled. 404 */ 405 static bool dpu_hw_intf_get_autorefresh_config(struct dpu_hw_intf *intf, 406 u32 *frame_count) 407 { 408 u32 val = DPU_REG_READ(&intf->hw, INTF_TEAR_AUTOREFRESH_CONFIG); 409 410 if (frame_count != NULL) 411 *frame_count = val & 0xffff; 412 return !!((val & BIT(31)) >> 31); 413 } 414 415 static int dpu_hw_intf_disable_te(struct dpu_hw_intf *intf) 416 { 417 struct dpu_hw_blk_reg_map *c; 418 419 if (!intf) 420 return -EINVAL; 421 422 c = &intf->hw; 423 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 0); 424 return 0; 425 } 426 427 static int dpu_hw_intf_connect_external_te(struct dpu_hw_intf *intf, 428 bool enable_external_te) 429 { 430 struct dpu_hw_blk_reg_map *c = &intf->hw; 431 u32 cfg; 432 int orig; 433 434 if (!intf) 435 return -EINVAL; 436 437 c = &intf->hw; 438 cfg = DPU_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC); 439 orig = (bool)(cfg & BIT(20)); 440 if (enable_external_te) 441 cfg |= BIT(20); 442 else 443 cfg &= ~BIT(20); 444 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg); 445 trace_dpu_intf_connect_ext_te(intf->idx - INTF_0, cfg); 446 447 return orig; 448 } 449 450 static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf, 451 struct dpu_hw_pp_vsync_info *info) 452 { 453 struct dpu_hw_blk_reg_map *c = &intf->hw; 454 u32 val; 455 456 if (!intf || !info) 457 return -EINVAL; 458 459 c = &intf->hw; 460 461 val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL); 462 info->rd_ptr_init_val = val & 0xffff; 463 464 val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL); 465 info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; 466 info->rd_ptr_line_count = val & 0xffff; 467 468 val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT); 469 info->wr_ptr_line_count = val & 0xffff; 470 471 val = DPU_REG_READ(c, INTF_FRAME_COUNT); 472 info->intf_frame_count = val; 473 474 return 0; 475 } 476 477 static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, 478 enum dpu_vsync_source vsync_source) 479 { 480 struct dpu_hw_blk_reg_map *c; 481 482 if (!intf) 483 return; 484 485 c = &intf->hw; 486 487 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); 488 } 489 490 static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, 491 uint32_t encoder_id, u16 vdisplay) 492 { 493 struct dpu_hw_pp_vsync_info info; 494 int trial = 0; 495 496 /* If autorefresh is already disabled, we have nothing to do */ 497 if (!dpu_hw_intf_get_autorefresh_config(intf, NULL)) 498 return; 499 500 /* 501 * If autorefresh is enabled, disable it and make sure it is safe to 502 * proceed with current frame commit/push. Sequence followed is, 503 * 1. Disable TE 504 * 2. Disable autorefresh config 505 * 4. Poll for frame transfer ongoing to be false 506 * 5. Enable TE back 507 */ 508 509 dpu_hw_intf_connect_external_te(intf, false); 510 dpu_hw_intf_setup_autorefresh_config(intf, 0, false); 511 512 do { 513 udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); 514 if ((trial * DPU_ENC_MAX_POLL_TIMEOUT_US) 515 > (KICKOFF_TIMEOUT_MS * USEC_PER_MSEC)) { 516 DPU_ERROR("enc%d intf%d disable autorefresh failed\n", 517 encoder_id, intf->idx - INTF_0); 518 break; 519 } 520 521 trial++; 522 523 dpu_hw_intf_get_vsync_info(intf, &info); 524 } while (info.wr_ptr_line_count > 0 && 525 info.wr_ptr_line_count < vdisplay); 526 527 dpu_hw_intf_connect_external_te(intf, true); 528 529 DPU_DEBUG("enc%d intf%d disabled autorefresh\n", 530 encoder_id, intf->idx - INTF_0); 531 532 } 533 534 static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf, 535 struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) 536 { 537 u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2); 538 539 if (cmd_mode_cfg->data_compress) 540 intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; 541 542 if (cmd_mode_cfg->wide_bus_en) 543 intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; 544 545 DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); 546 } 547 548 /** 549 * dpu_hw_intf_init() - Initializes the INTF driver for the passed 550 * interface catalog entry. 551 * @dev: Corresponding device for devres management 552 * @cfg: interface catalog entry for which driver object is required 553 * @addr: mapped register io address of MDP 554 * @mdss_rev: dpu core's major and minor versions 555 */ 556 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 557 const struct dpu_intf_cfg *cfg, 558 void __iomem *addr, 559 const struct dpu_mdss_version *mdss_rev) 560 { 561 struct dpu_hw_intf *c; 562 563 if (cfg->type == INTF_NONE) { 564 DPU_DEBUG("Skip intf %d with type NONE\n", cfg->id - INTF_0); 565 return NULL; 566 } 567 568 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL); 569 if (!c) 570 return ERR_PTR(-ENOMEM); 571 572 c->hw.blk_addr = addr + cfg->base; 573 c->hw.log_mask = DPU_DBG_MASK_INTF; 574 575 /* 576 * Assign ops 577 */ 578 c->idx = cfg->id; 579 c->cap = cfg; 580 581 c->mdss_ver = mdss_rev; 582 583 c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; 584 c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; 585 c->ops.get_status = dpu_hw_intf_get_status; 586 c->ops.enable_timing = dpu_hw_intf_enable_timing_engine; 587 c->ops.get_line_count = dpu_hw_intf_get_line_count; 588 c->ops.setup_misr = dpu_hw_intf_setup_misr; 589 c->ops.collect_misr = dpu_hw_intf_collect_misr; 590 591 if (mdss_rev->core_major_ver >= 5) 592 c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; 593 594 /* INTF TE is only for DSI interfaces */ 595 if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) { 596 WARN_ON(!cfg->intr_tear_rd_ptr); 597 598 c->ops.enable_tearcheck = dpu_hw_intf_enable_te; 599 c->ops.disable_tearcheck = dpu_hw_intf_disable_te; 600 c->ops.connect_external_te = dpu_hw_intf_connect_external_te; 601 c->ops.vsync_sel = dpu_hw_intf_vsync_sel; 602 c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh; 603 } 604 605 /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but 606 * we can configure it for DPU 7.0+ since the wide bus and DSC flags 607 * would not be set for DPU < 7.0 anyways 608 */ 609 if (mdss_rev->core_major_ver >= 7) 610 c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; 611 612 return c; 613 } 614