1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/bitops.h> 6 #include <linux/slab.h> 7 8 #include "dpu_kms.h" 9 #include "dpu_hw_interrupts.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_mdss.h" 12 13 /** 14 * Register offsets in MDSS register file for the interrupt registers 15 * w.r.t. to the MDP base 16 */ 17 #define MDP_SSPP_TOP0_OFF 0x0 18 #define MDP_INTF_0_OFF 0x6A000 19 #define MDP_INTF_1_OFF 0x6A800 20 #define MDP_INTF_2_OFF 0x6B000 21 #define MDP_INTF_3_OFF 0x6B800 22 #define MDP_INTF_4_OFF 0x6C000 23 #define MDP_AD4_0_OFF 0x7C000 24 #define MDP_AD4_1_OFF 0x7D000 25 #define MDP_AD4_INTR_EN_OFF 0x41c 26 #define MDP_AD4_INTR_CLEAR_OFF 0x424 27 #define MDP_AD4_INTR_STATUS_OFF 0x420 28 #define MDP_INTF_0_OFF_REV_7xxx 0x34000 29 #define MDP_INTF_1_OFF_REV_7xxx 0x35000 30 #define MDP_INTF_5_OFF_REV_7xxx 0x39000 31 32 /** 33 * WB interrupt status bit definitions 34 */ 35 #define DPU_INTR_WB_0_DONE BIT(0) 36 #define DPU_INTR_WB_1_DONE BIT(1) 37 #define DPU_INTR_WB_2_DONE BIT(4) 38 39 /** 40 * WDOG timer interrupt status bit definitions 41 */ 42 #define DPU_INTR_WD_TIMER_0_DONE BIT(2) 43 #define DPU_INTR_WD_TIMER_1_DONE BIT(3) 44 #define DPU_INTR_WD_TIMER_2_DONE BIT(5) 45 #define DPU_INTR_WD_TIMER_3_DONE BIT(6) 46 #define DPU_INTR_WD_TIMER_4_DONE BIT(7) 47 48 /** 49 * Pingpong interrupt status bit definitions 50 */ 51 #define DPU_INTR_PING_PONG_0_DONE BIT(8) 52 #define DPU_INTR_PING_PONG_1_DONE BIT(9) 53 #define DPU_INTR_PING_PONG_2_DONE BIT(10) 54 #define DPU_INTR_PING_PONG_3_DONE BIT(11) 55 #define DPU_INTR_PING_PONG_0_RD_PTR BIT(12) 56 #define DPU_INTR_PING_PONG_1_RD_PTR BIT(13) 57 #define DPU_INTR_PING_PONG_2_RD_PTR BIT(14) 58 #define DPU_INTR_PING_PONG_3_RD_PTR BIT(15) 59 #define DPU_INTR_PING_PONG_0_WR_PTR BIT(16) 60 #define DPU_INTR_PING_PONG_1_WR_PTR BIT(17) 61 #define DPU_INTR_PING_PONG_2_WR_PTR BIT(18) 62 #define DPU_INTR_PING_PONG_3_WR_PTR BIT(19) 63 #define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20) 64 #define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21) 65 #define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22) 66 #define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23) 67 68 /** 69 * Interface interrupt status bit definitions 70 */ 71 #define DPU_INTR_INTF_0_UNDERRUN BIT(24) 72 #define DPU_INTR_INTF_1_UNDERRUN BIT(26) 73 #define DPU_INTR_INTF_2_UNDERRUN BIT(28) 74 #define DPU_INTR_INTF_3_UNDERRUN BIT(30) 75 #define DPU_INTR_INTF_5_UNDERRUN BIT(22) 76 #define DPU_INTR_INTF_0_VSYNC BIT(25) 77 #define DPU_INTR_INTF_1_VSYNC BIT(27) 78 #define DPU_INTR_INTF_2_VSYNC BIT(29) 79 #define DPU_INTR_INTF_3_VSYNC BIT(31) 80 #define DPU_INTR_INTF_5_VSYNC BIT(23) 81 82 /** 83 * Pingpong Secondary interrupt status bit definitions 84 */ 85 #define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0) 86 #define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4) 87 #define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8) 88 #define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22) 89 #define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28) 90 91 /** 92 * Pingpong TEAR detection interrupt status bit definitions 93 */ 94 #define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16) 95 #define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17) 96 #define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18) 97 #define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19) 98 99 /** 100 * Pingpong TE detection interrupt status bit definitions 101 */ 102 #define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24) 103 #define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25) 104 #define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26) 105 #define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27) 106 107 /** 108 * Ctl start interrupt status bit definitions 109 */ 110 #define DPU_INTR_CTL_0_START BIT(9) 111 #define DPU_INTR_CTL_1_START BIT(10) 112 #define DPU_INTR_CTL_2_START BIT(11) 113 #define DPU_INTR_CTL_3_START BIT(12) 114 #define DPU_INTR_CTL_4_START BIT(13) 115 116 /** 117 * Concurrent WB overflow interrupt status bit definitions 118 */ 119 #define DPU_INTR_CWB_2_OVERFLOW BIT(14) 120 #define DPU_INTR_CWB_3_OVERFLOW BIT(15) 121 122 /** 123 * Histogram VIG done interrupt status bit definitions 124 */ 125 #define DPU_INTR_HIST_VIG_0_DONE BIT(0) 126 #define DPU_INTR_HIST_VIG_1_DONE BIT(4) 127 #define DPU_INTR_HIST_VIG_2_DONE BIT(8) 128 #define DPU_INTR_HIST_VIG_3_DONE BIT(10) 129 130 /** 131 * Histogram VIG reset Sequence done interrupt status bit definitions 132 */ 133 #define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1) 134 #define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5) 135 #define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9) 136 #define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11) 137 138 /** 139 * Histogram DSPP done interrupt status bit definitions 140 */ 141 #define DPU_INTR_HIST_DSPP_0_DONE BIT(12) 142 #define DPU_INTR_HIST_DSPP_1_DONE BIT(16) 143 #define DPU_INTR_HIST_DSPP_2_DONE BIT(20) 144 #define DPU_INTR_HIST_DSPP_3_DONE BIT(22) 145 146 /** 147 * Histogram DSPP reset Sequence done interrupt status bit definitions 148 */ 149 #define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13) 150 #define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17) 151 #define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21) 152 #define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23) 153 154 /** 155 * INTF interrupt status bit definitions 156 */ 157 #define DPU_INTR_VIDEO_INTO_STATIC BIT(0) 158 #define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1) 159 #define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2) 160 #define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3) 161 #define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4) 162 #define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5) 163 #define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6) 164 #define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7) 165 #define DPU_INTR_PROG_LINE BIT(8) 166 167 /** 168 * AD4 interrupt status bit definitions 169 */ 170 #define DPU_INTR_BACKLIGHT_UPDATED BIT(0) 171 /** 172 * struct dpu_intr_reg - array of DPU register sets 173 * @clr_off: offset to CLEAR reg 174 * @en_off: offset to ENABLE reg 175 * @status_off: offset to STATUS reg 176 */ 177 struct dpu_intr_reg { 178 u32 clr_off; 179 u32 en_off; 180 u32 status_off; 181 }; 182 183 /** 184 * struct dpu_irq_type - maps each irq with i/f 185 * @intr_type: type of interrupt listed in dpu_intr_type 186 * @instance_idx: instance index of the associated HW block in DPU 187 * @irq_mask: corresponding bit in the interrupt status reg 188 * @reg_idx: which reg set to use 189 */ 190 struct dpu_irq_type { 191 u32 intr_type; 192 u32 instance_idx; 193 u32 irq_mask; 194 u32 reg_idx; 195 }; 196 197 /* 198 * struct dpu_intr_reg - List of DPU interrupt registers 199 */ 200 static const struct dpu_intr_reg dpu_intr_set[] = { 201 { 202 MDP_SSPP_TOP0_OFF+INTR_CLEAR, 203 MDP_SSPP_TOP0_OFF+INTR_EN, 204 MDP_SSPP_TOP0_OFF+INTR_STATUS 205 }, 206 { 207 MDP_SSPP_TOP0_OFF+INTR2_CLEAR, 208 MDP_SSPP_TOP0_OFF+INTR2_EN, 209 MDP_SSPP_TOP0_OFF+INTR2_STATUS 210 }, 211 { 212 MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR, 213 MDP_SSPP_TOP0_OFF+HIST_INTR_EN, 214 MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS 215 }, 216 { 217 MDP_INTF_0_OFF+INTF_INTR_CLEAR, 218 MDP_INTF_0_OFF+INTF_INTR_EN, 219 MDP_INTF_0_OFF+INTF_INTR_STATUS 220 }, 221 { 222 MDP_INTF_1_OFF+INTF_INTR_CLEAR, 223 MDP_INTF_1_OFF+INTF_INTR_EN, 224 MDP_INTF_1_OFF+INTF_INTR_STATUS 225 }, 226 { 227 MDP_INTF_2_OFF+INTF_INTR_CLEAR, 228 MDP_INTF_2_OFF+INTF_INTR_EN, 229 MDP_INTF_2_OFF+INTF_INTR_STATUS 230 }, 231 { 232 MDP_INTF_3_OFF+INTF_INTR_CLEAR, 233 MDP_INTF_3_OFF+INTF_INTR_EN, 234 MDP_INTF_3_OFF+INTF_INTR_STATUS 235 }, 236 { 237 MDP_INTF_4_OFF+INTF_INTR_CLEAR, 238 MDP_INTF_4_OFF+INTF_INTR_EN, 239 MDP_INTF_4_OFF+INTF_INTR_STATUS 240 }, 241 { 242 MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF, 243 MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF, 244 MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF, 245 }, 246 { 247 MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF, 248 MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF, 249 MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF, 250 }, 251 { 252 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR, 253 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN, 254 MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS 255 }, 256 { 257 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR, 258 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN, 259 MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS 260 }, 261 { 262 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR, 263 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, 264 MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS 265 }, 266 }; 267 268 /* 269 * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this 270 * table that have a matching interface type and 271 * instance index. 272 */ 273 static const struct dpu_irq_type dpu_irq_map[] = { 274 /* BEGIN MAP_RANGE: 0-31, INTR */ 275 /* irq_idx: 0-3 */ 276 { DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0}, 277 { DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0}, 278 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0}, 279 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0}, 280 /* irq_idx: 4-7 */ 281 { DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0}, 282 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0}, 283 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0}, 284 { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0}, 285 /* irq_idx: 8-11 */ 286 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0, 287 DPU_INTR_PING_PONG_0_DONE, 0}, 288 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1, 289 DPU_INTR_PING_PONG_1_DONE, 0}, 290 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2, 291 DPU_INTR_PING_PONG_2_DONE, 0}, 292 { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3, 293 DPU_INTR_PING_PONG_3_DONE, 0}, 294 /* irq_idx: 12-15 */ 295 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0, 296 DPU_INTR_PING_PONG_0_RD_PTR, 0}, 297 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1, 298 DPU_INTR_PING_PONG_1_RD_PTR, 0}, 299 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2, 300 DPU_INTR_PING_PONG_2_RD_PTR, 0}, 301 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3, 302 DPU_INTR_PING_PONG_3_RD_PTR, 0}, 303 /* irq_idx: 16-19 */ 304 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0, 305 DPU_INTR_PING_PONG_0_WR_PTR, 0}, 306 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1, 307 DPU_INTR_PING_PONG_1_WR_PTR, 0}, 308 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2, 309 DPU_INTR_PING_PONG_2_WR_PTR, 0}, 310 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, 311 DPU_INTR_PING_PONG_3_WR_PTR, 0}, 312 /* irq_idx: 20-23 */ 313 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, 314 DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, 315 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, 316 DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, 317 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, 318 DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, 319 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, 320 DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, 321 /* irq_idx: 24-27 */ 322 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, 323 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, 324 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0}, 325 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0}, 326 /* irq_idx: 28-31 */ 327 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0}, 328 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, 329 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, 330 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, 331 /* irq_idx:32-33 */ 332 { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, 333 { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, 334 /* irq_idx:34-63 */ 335 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 336 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 337 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 338 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 339 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 340 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 341 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 342 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 343 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 344 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 345 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 346 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 347 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 348 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 349 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 350 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 351 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 352 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 353 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 354 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 355 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 356 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 357 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 358 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 359 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 360 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 361 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 362 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 363 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 364 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 365 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 366 { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, 367 /* BEGIN MAP_RANGE: 64-95, INTR2 */ 368 /* irq_idx: 64-67 */ 369 { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0, 370 DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1}, 371 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 372 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 373 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 374 /* irq_idx: 68-71 */ 375 { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0, 376 DPU_INTR_PING_PONG_S0_WR_PTR, 1}, 377 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 378 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 379 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 380 /* irq_idx: 72 */ 381 { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0, 382 DPU_INTR_PING_PONG_S0_RD_PTR, 1}, 383 /* irq_idx: 73-77 */ 384 { DPU_IRQ_TYPE_CTL_START, CTL_0, 385 DPU_INTR_CTL_0_START, 1}, 386 { DPU_IRQ_TYPE_CTL_START, CTL_1, 387 DPU_INTR_CTL_1_START, 1}, 388 { DPU_IRQ_TYPE_CTL_START, CTL_2, 389 DPU_INTR_CTL_2_START, 1}, 390 { DPU_IRQ_TYPE_CTL_START, CTL_3, 391 DPU_INTR_CTL_3_START, 1}, 392 { DPU_IRQ_TYPE_CTL_START, CTL_4, 393 DPU_INTR_CTL_4_START, 1}, 394 /* irq_idx: 78-79 */ 395 { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1}, 396 { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1}, 397 /* irq_idx: 80-83 */ 398 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0, 399 DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1}, 400 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1, 401 DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1}, 402 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2, 403 DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1}, 404 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3, 405 DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1}, 406 /* irq_idx: 84-87 */ 407 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 408 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 409 { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0, 410 DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1}, 411 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 412 /* irq_idx: 88-91 */ 413 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0, 414 DPU_INTR_PING_PONG_0_TE_DETECTED, 1}, 415 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1, 416 DPU_INTR_PING_PONG_1_TE_DETECTED, 1}, 417 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2, 418 DPU_INTR_PING_PONG_2_TE_DETECTED, 1}, 419 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3, 420 DPU_INTR_PING_PONG_3_TE_DETECTED, 1}, 421 /* irq_idx: 92-95 */ 422 { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0, 423 DPU_INTR_PING_PONG_S0_TE_DETECTED, 1}, 424 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 425 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 426 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 427 /* irq_idx: 96-127 */ 428 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 429 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 430 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 431 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 432 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 433 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 434 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 435 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 436 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 437 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 438 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 439 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 440 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 441 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 442 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 443 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 444 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 445 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 446 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 447 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 448 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 449 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 450 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 451 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 452 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 453 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 454 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 455 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 456 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 457 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 458 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 459 { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, 460 /* BEGIN MAP_RANGE: 128-159 HIST */ 461 /* irq_idx: 128-131 */ 462 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2}, 463 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0, 464 DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2}, 465 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 466 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 467 /* irq_idx: 132-135 */ 468 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2}, 469 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1, 470 DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2}, 471 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 472 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 473 /* irq_idx: 136-139 */ 474 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, 475 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2, 476 DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2}, 477 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2}, 478 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3, 479 DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2}, 480 /* irq_idx: 140-143 */ 481 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2}, 482 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0, 483 DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2}, 484 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 485 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 486 /* irq_idx: 144-147 */ 487 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2}, 488 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1, 489 DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2}, 490 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 491 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 492 /* irq_idx: 148-151 */ 493 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2}, 494 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2, 495 DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2}, 496 { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2}, 497 { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3, 498 DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2}, 499 /* irq_idx: 152-155 */ 500 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 501 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 502 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 503 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 504 /* irq_idx: 156-159 */ 505 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 506 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 507 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 508 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 509 /* irq_idx: 160-191 */ 510 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 511 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 512 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 513 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 514 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 515 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 516 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 517 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 518 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 519 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 520 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 521 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 522 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 523 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 524 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 525 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 526 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 527 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 528 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 529 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 530 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 531 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 532 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 533 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 534 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 535 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 536 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 537 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 538 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 539 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 540 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 541 { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, 542 /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */ 543 /* irq_idx: 192-195 */ 544 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, 545 DPU_INTR_VIDEO_INTO_STATIC, 3}, 546 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, 547 DPU_INTR_VIDEO_OUTOF_STATIC, 3}, 548 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, 549 DPU_INTR_DSICMD_0_INTO_STATIC, 3}, 550 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, 551 DPU_INTR_DSICMD_0_OUTOF_STATIC, 3}, 552 /* irq_idx: 196-199 */ 553 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, 554 DPU_INTR_DSICMD_1_INTO_STATIC, 3}, 555 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, 556 DPU_INTR_DSICMD_1_OUTOF_STATIC, 3}, 557 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, 558 DPU_INTR_DSICMD_2_INTO_STATIC, 3}, 559 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, 560 DPU_INTR_DSICMD_2_OUTOF_STATIC, 3}, 561 /* irq_idx: 200-203 */ 562 { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3}, 563 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 564 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 565 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 566 /* irq_idx: 204-207 */ 567 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 568 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 569 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 570 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 571 /* irq_idx: 208-211 */ 572 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 573 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 574 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 575 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 576 /* irq_idx: 212-215 */ 577 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 578 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 579 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 580 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 581 /* irq_idx: 216-219 */ 582 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 583 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 584 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 585 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 586 /* irq_idx: 220-223 */ 587 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 588 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 589 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 590 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 591 /* irq_idx: 224-255 */ 592 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 593 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 594 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 595 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 596 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 597 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 598 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 599 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 600 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 601 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 602 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 603 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 604 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 605 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 606 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 607 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 608 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 609 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 610 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 611 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 612 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 613 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 614 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 615 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 616 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 617 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 618 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 619 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 620 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 621 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 622 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 623 { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, 624 /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */ 625 /* irq_idx: 256-259 */ 626 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, 627 DPU_INTR_VIDEO_INTO_STATIC, 4}, 628 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, 629 DPU_INTR_VIDEO_OUTOF_STATIC, 4}, 630 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, 631 DPU_INTR_DSICMD_0_INTO_STATIC, 4}, 632 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, 633 DPU_INTR_DSICMD_0_OUTOF_STATIC, 4}, 634 /* irq_idx: 260-263 */ 635 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, 636 DPU_INTR_DSICMD_1_INTO_STATIC, 4}, 637 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, 638 DPU_INTR_DSICMD_1_OUTOF_STATIC, 4}, 639 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, 640 DPU_INTR_DSICMD_2_INTO_STATIC, 4}, 641 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, 642 DPU_INTR_DSICMD_2_OUTOF_STATIC, 4}, 643 /* irq_idx: 264-267 */ 644 { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4}, 645 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 646 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 647 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 648 /* irq_idx: 268-271 */ 649 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 650 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 651 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 652 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 653 /* irq_idx: 272-275 */ 654 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 655 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 656 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 657 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 658 /* irq_idx: 276-279 */ 659 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 660 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 661 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 662 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 663 /* irq_idx: 280-283 */ 664 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 665 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 666 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 667 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 668 /* irq_idx: 284-287 */ 669 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 670 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 671 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 672 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 673 /* irq_idx: 288-319 */ 674 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 675 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 676 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 677 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 678 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 679 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 680 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 681 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 682 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 683 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 684 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 685 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 686 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 687 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 688 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 689 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 690 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 691 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 692 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 693 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 694 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 695 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 696 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 697 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 698 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 699 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 700 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 701 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 702 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 703 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 704 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 705 { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, 706 /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */ 707 /* irq_idx: 320-323 */ 708 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2, 709 DPU_INTR_VIDEO_INTO_STATIC, 5}, 710 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2, 711 DPU_INTR_VIDEO_OUTOF_STATIC, 5}, 712 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2, 713 DPU_INTR_DSICMD_0_INTO_STATIC, 5}, 714 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2, 715 DPU_INTR_DSICMD_0_OUTOF_STATIC, 5}, 716 /* irq_idx: 324-327 */ 717 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2, 718 DPU_INTR_DSICMD_1_INTO_STATIC, 5}, 719 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2, 720 DPU_INTR_DSICMD_1_OUTOF_STATIC, 5}, 721 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2, 722 DPU_INTR_DSICMD_2_INTO_STATIC, 5}, 723 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2, 724 DPU_INTR_DSICMD_2_OUTOF_STATIC, 5}, 725 /* irq_idx: 328-331 */ 726 { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5}, 727 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 728 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 729 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 730 /* irq_idx: 332-335 */ 731 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 732 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 733 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 734 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 735 /* irq_idx: 336-339 */ 736 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 737 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 738 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 739 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 740 /* irq_idx: 340-343 */ 741 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 742 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 743 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 744 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 745 /* irq_idx: 344-347 */ 746 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 747 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 748 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 749 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 750 /* irq_idx: 348-351 */ 751 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 752 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 753 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 754 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 755 /* irq_idx: 352-383 */ 756 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 757 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 758 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 759 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 760 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 761 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 762 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 763 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 764 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 765 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 766 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 767 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 768 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 769 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 770 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 771 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 772 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 773 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 774 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 775 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 776 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 777 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 778 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 779 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 780 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 781 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 782 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 783 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 784 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 785 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 786 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 787 { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, 788 /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */ 789 /* irq_idx: 384-387 */ 790 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3, 791 DPU_INTR_VIDEO_INTO_STATIC, 6}, 792 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3, 793 DPU_INTR_VIDEO_OUTOF_STATIC, 6}, 794 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3, 795 DPU_INTR_DSICMD_0_INTO_STATIC, 6}, 796 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3, 797 DPU_INTR_DSICMD_0_OUTOF_STATIC, 6}, 798 /* irq_idx: 388-391 */ 799 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3, 800 DPU_INTR_DSICMD_1_INTO_STATIC, 6}, 801 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3, 802 DPU_INTR_DSICMD_1_OUTOF_STATIC, 6}, 803 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3, 804 DPU_INTR_DSICMD_2_INTO_STATIC, 6}, 805 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3, 806 DPU_INTR_DSICMD_2_OUTOF_STATIC, 6}, 807 /* irq_idx: 392-395 */ 808 { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6}, 809 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 810 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 811 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 812 /* irq_idx: 396-399 */ 813 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 814 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 815 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 816 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 817 /* irq_idx: 400-403 */ 818 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 819 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 820 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 821 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 822 /* irq_idx: 404-407 */ 823 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 824 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 825 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 826 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 827 /* irq_idx: 408-411 */ 828 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 829 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 830 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 831 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 832 /* irq_idx: 412-415 */ 833 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 834 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 835 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 836 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 837 /* irq_idx: 416-447*/ 838 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 839 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 840 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 841 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 842 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 843 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 844 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 845 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 846 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 847 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 848 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 849 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 850 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 851 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 852 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 853 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 854 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 855 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 856 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 857 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 858 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 859 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 860 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 861 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 862 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 863 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 864 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 865 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 866 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 867 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 868 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 869 { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, 870 /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */ 871 /* irq_idx: 448-451 */ 872 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4, 873 DPU_INTR_VIDEO_INTO_STATIC, 7}, 874 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4, 875 DPU_INTR_VIDEO_OUTOF_STATIC, 7}, 876 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4, 877 DPU_INTR_DSICMD_0_INTO_STATIC, 7}, 878 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4, 879 DPU_INTR_DSICMD_0_OUTOF_STATIC, 7}, 880 /* irq_idx: 452-455 */ 881 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4, 882 DPU_INTR_DSICMD_1_INTO_STATIC, 7}, 883 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4, 884 DPU_INTR_DSICMD_1_OUTOF_STATIC, 7}, 885 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4, 886 DPU_INTR_DSICMD_2_INTO_STATIC, 7}, 887 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4, 888 DPU_INTR_DSICMD_2_OUTOF_STATIC, 7}, 889 /* irq_idx: 456-459 */ 890 { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7}, 891 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 892 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 893 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 894 /* irq_idx: 460-463 */ 895 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 896 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 897 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 898 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 899 /* irq_idx: 464-467 */ 900 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 901 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 902 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 903 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 904 /* irq_idx: 468-471 */ 905 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 906 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 907 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 908 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 909 /* irq_idx: 472-475 */ 910 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 911 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 912 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 913 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 914 /* irq_idx: 476-479 */ 915 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 916 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 917 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 918 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 919 /* irq_idx: 480-511 */ 920 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 921 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 922 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 923 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 924 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 925 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 926 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 927 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 928 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 929 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 930 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 931 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 932 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 933 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 934 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 935 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 936 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 937 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 938 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 939 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 940 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 941 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 942 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 943 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 944 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 945 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 946 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 947 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 948 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 949 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 950 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 951 { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, 952 /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */ 953 /* irq_idx: 512-515 */ 954 { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8}, 955 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 956 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 957 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 958 /* irq_idx: 516-519 */ 959 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 960 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 961 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 962 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 963 /* irq_idx: 520-523 */ 964 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 965 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 966 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 967 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 968 /* irq_idx: 524-527 */ 969 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 970 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 971 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 972 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 973 /* irq_idx: 528-531 */ 974 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 975 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 976 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 977 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 978 /* irq_idx: 532-535 */ 979 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 980 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 981 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 982 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 983 /* irq_idx: 536-539 */ 984 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 985 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 986 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 987 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 988 /* irq_idx: 540-543 */ 989 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 990 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 991 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 992 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 993 /* irq_idx: 544-575*/ 994 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 995 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 996 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 997 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 998 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 999 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1000 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1001 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1002 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1003 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1004 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1005 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1006 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1007 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1008 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1009 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1010 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1011 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1012 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1013 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1014 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1015 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1016 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1017 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1018 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1019 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1020 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1021 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1022 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1023 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1024 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1025 { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, 1026 /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */ 1027 /* irq_idx: 576-579 */ 1028 { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9}, 1029 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1030 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1031 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1032 /* irq_idx: 580-583 */ 1033 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1034 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1035 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1036 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1037 /* irq_idx: 584-587 */ 1038 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1039 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1040 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1041 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1042 /* irq_idx: 588-591 */ 1043 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1044 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1045 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1046 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1047 /* irq_idx: 592-595 */ 1048 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1049 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1050 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1051 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1052 /* irq_idx: 596-599 */ 1053 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1054 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1055 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1056 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1057 /* irq_idx: 600-603 */ 1058 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1059 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1060 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1061 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1062 /* irq_idx: 604-607 */ 1063 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1064 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1065 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1066 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1067 /* irq_idx: 608-639 */ 1068 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1069 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1070 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1071 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1072 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1073 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1074 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1075 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1076 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1077 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1078 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1079 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1080 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1081 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1082 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1083 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1084 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1085 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1086 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1087 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1088 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1089 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1090 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1091 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1092 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1093 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1094 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1095 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1096 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1097 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1098 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1099 { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, 1100 /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */ 1101 /* irq_idx: 640-643 */ 1102 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, 1103 DPU_INTR_VIDEO_INTO_STATIC, 10}, 1104 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, 1105 DPU_INTR_VIDEO_OUTOF_STATIC, 10}, 1106 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, 1107 DPU_INTR_DSICMD_0_INTO_STATIC, 10}, 1108 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, 1109 DPU_INTR_DSICMD_0_OUTOF_STATIC, 10}, 1110 /* irq_idx: 644-647 */ 1111 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, 1112 DPU_INTR_DSICMD_1_INTO_STATIC, 10}, 1113 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, 1114 DPU_INTR_DSICMD_1_OUTOF_STATIC, 10}, 1115 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, 1116 DPU_INTR_DSICMD_2_INTO_STATIC, 10}, 1117 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, 1118 DPU_INTR_DSICMD_2_OUTOF_STATIC, 10}, 1119 /* irq_idx: 648-651 */ 1120 { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10}, 1121 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1122 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1123 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1124 /* irq_idx: 652-655 */ 1125 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1126 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1127 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1128 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1129 /* irq_idx: 656-659 */ 1130 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1131 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1132 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1133 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1134 /* irq_idx: 660-663 */ 1135 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1136 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1137 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1138 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1139 /* irq_idx: 664-667 */ 1140 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1141 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1142 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1143 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1144 /* irq_idx: 668-671 */ 1145 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1146 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1147 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1148 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1149 /* irq_idx: 672-703 */ 1150 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1151 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1152 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1153 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1154 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1155 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1156 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1157 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1158 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1159 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1160 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1161 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1162 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1163 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1164 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1165 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1166 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1167 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1168 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1169 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1170 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1171 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1172 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1173 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1174 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1175 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1176 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1177 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1178 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1179 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1180 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1181 { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, 1182 /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */ 1183 /* irq_idx: 704-707 */ 1184 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, 1185 DPU_INTR_VIDEO_INTO_STATIC, 11}, 1186 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, 1187 DPU_INTR_VIDEO_OUTOF_STATIC, 11}, 1188 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, 1189 DPU_INTR_DSICMD_0_INTO_STATIC, 11}, 1190 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, 1191 DPU_INTR_DSICMD_0_OUTOF_STATIC, 11}, 1192 /* irq_idx: 708-711 */ 1193 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, 1194 DPU_INTR_DSICMD_1_INTO_STATIC, 11}, 1195 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, 1196 DPU_INTR_DSICMD_1_OUTOF_STATIC, 11}, 1197 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, 1198 DPU_INTR_DSICMD_2_INTO_STATIC, 11}, 1199 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, 1200 DPU_INTR_DSICMD_2_OUTOF_STATIC, 11}, 1201 /* irq_idx: 712-715 */ 1202 { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11}, 1203 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1204 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1205 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1206 /* irq_idx: 716-719 */ 1207 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1208 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1209 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1210 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1211 /* irq_idx: 720-723 */ 1212 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1213 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1214 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1215 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1216 /* irq_idx: 724-727 */ 1217 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1218 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1219 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1220 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1221 /* irq_idx: 728-731 */ 1222 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1223 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1224 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1225 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1226 /* irq_idx: 732-735 */ 1227 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1228 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1229 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1230 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1231 /* irq_idx: 736-767 */ 1232 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1233 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1234 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1235 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1236 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1237 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1238 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1239 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1240 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1241 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1242 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1243 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1244 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1245 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1246 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1247 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1248 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1249 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1250 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1251 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1252 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1253 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1254 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1255 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1256 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1257 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1258 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1259 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1260 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1261 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1262 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1263 { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, 1264 /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */ 1265 /* irq_idx: 768-771 */ 1266 { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5, 1267 DPU_INTR_VIDEO_INTO_STATIC, 12}, 1268 { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5, 1269 DPU_INTR_VIDEO_OUTOF_STATIC, 12}, 1270 { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5, 1271 DPU_INTR_DSICMD_0_INTO_STATIC, 12}, 1272 { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5, 1273 DPU_INTR_DSICMD_0_OUTOF_STATIC, 12}, 1274 /* irq_idx: 772-775 */ 1275 { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5, 1276 DPU_INTR_DSICMD_1_INTO_STATIC, 12}, 1277 { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5, 1278 DPU_INTR_DSICMD_1_OUTOF_STATIC, 12}, 1279 { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5, 1280 DPU_INTR_DSICMD_2_INTO_STATIC, 12}, 1281 { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5, 1282 DPU_INTR_DSICMD_2_OUTOF_STATIC, 12}, 1283 /* irq_idx: 776-779 */ 1284 { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12}, 1285 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1286 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1287 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1288 /* irq_idx: 780-783 */ 1289 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1290 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1291 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1292 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1293 /* irq_idx: 784-787 */ 1294 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1295 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1296 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1297 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1298 /* irq_idx: 788-791 */ 1299 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1300 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1301 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1302 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1303 /* irq_idx: 792-795 */ 1304 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1305 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1306 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1307 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1308 /* irq_idx: 796-799 */ 1309 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1310 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1311 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1312 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1313 /* irq_idx: 800-831 */ 1314 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1315 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1316 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1317 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1318 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1319 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1320 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1321 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1322 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1323 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1324 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1325 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1326 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1327 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1328 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1329 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1330 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1331 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1332 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1333 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1334 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1335 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1336 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1337 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1338 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1339 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1340 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1341 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1342 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1343 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1344 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1345 { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, 1346 }; 1347 1348 static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr, 1349 enum dpu_intr_type intr_type, u32 instance_idx) 1350 { 1351 int i; 1352 1353 for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) { 1354 if (intr_type == dpu_irq_map[i].intr_type && 1355 instance_idx == dpu_irq_map[i].instance_idx && 1356 !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type))) 1357 return i; 1358 } 1359 1360 pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n", 1361 intr_type, instance_idx); 1362 return -EINVAL; 1363 } 1364 1365 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, 1366 void (*cbfunc)(void *, int), 1367 void *arg) 1368 { 1369 int reg_idx; 1370 int irq_idx; 1371 int start_idx; 1372 int end_idx; 1373 u32 irq_status; 1374 unsigned long irq_flags; 1375 1376 if (!intr) 1377 return; 1378 1379 /* 1380 * The dispatcher will save the IRQ status before calling here. 1381 * Now need to go through each IRQ status and find matching 1382 * irq lookup index. 1383 */ 1384 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1385 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { 1386 irq_status = intr->save_irq_status[reg_idx]; 1387 1388 /* 1389 * Each Interrupt register has a range of 64 indexes, and 1390 * that is static for dpu_irq_map. 1391 */ 1392 start_idx = reg_idx * 64; 1393 end_idx = start_idx + 64; 1394 1395 if (!test_bit(reg_idx, &intr->irq_mask) || 1396 start_idx >= ARRAY_SIZE(dpu_irq_map)) 1397 continue; 1398 1399 /* 1400 * Search through matching intr status from irq map. 1401 * start_idx and end_idx defined the search range in 1402 * the dpu_irq_map. 1403 */ 1404 for (irq_idx = start_idx; 1405 (irq_idx < end_idx) && irq_status; 1406 irq_idx++) 1407 if ((irq_status & dpu_irq_map[irq_idx].irq_mask) && 1408 (dpu_irq_map[irq_idx].reg_idx == reg_idx) && 1409 !(intr->obsolete_irq & 1410 BIT(dpu_irq_map[irq_idx].intr_type))) { 1411 /* 1412 * Once a match on irq mask, perform a callback 1413 * to the given cbfunc. cbfunc will take care 1414 * the interrupt status clearing. If cbfunc is 1415 * not provided, then the interrupt clearing 1416 * is here. 1417 */ 1418 if (cbfunc) 1419 cbfunc(arg, irq_idx); 1420 else 1421 intr->ops.clear_intr_status_nolock( 1422 intr, irq_idx); 1423 1424 /* 1425 * When callback finish, clear the irq_status 1426 * with the matching mask. Once irq_status 1427 * is all cleared, the search can be stopped. 1428 */ 1429 irq_status &= ~dpu_irq_map[irq_idx].irq_mask; 1430 } 1431 } 1432 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1433 } 1434 1435 static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) 1436 { 1437 int reg_idx; 1438 unsigned long irq_flags; 1439 const struct dpu_intr_reg *reg; 1440 const struct dpu_irq_type *irq; 1441 const char *dbgstr = NULL; 1442 uint32_t cache_irq_mask; 1443 1444 if (!intr) 1445 return -EINVAL; 1446 1447 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 1448 pr_err("invalid IRQ index: [%d]\n", irq_idx); 1449 return -EINVAL; 1450 } 1451 1452 irq = &dpu_irq_map[irq_idx]; 1453 reg_idx = irq->reg_idx; 1454 reg = &dpu_intr_set[reg_idx]; 1455 1456 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1457 cache_irq_mask = intr->cache_irq_mask[reg_idx]; 1458 if (cache_irq_mask & irq->irq_mask) { 1459 dbgstr = "DPU IRQ already set:"; 1460 } else { 1461 dbgstr = "DPU IRQ enabled:"; 1462 1463 cache_irq_mask |= irq->irq_mask; 1464 /* Cleaning any pending interrupt */ 1465 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); 1466 /* Enabling interrupts with the new mask */ 1467 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); 1468 1469 /* ensure register write goes through */ 1470 wmb(); 1471 1472 intr->cache_irq_mask[reg_idx] = cache_irq_mask; 1473 } 1474 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1475 1476 pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, 1477 irq->irq_mask, cache_irq_mask); 1478 1479 return 0; 1480 } 1481 1482 static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) 1483 { 1484 int reg_idx; 1485 const struct dpu_intr_reg *reg; 1486 const struct dpu_irq_type *irq; 1487 const char *dbgstr = NULL; 1488 uint32_t cache_irq_mask; 1489 1490 if (!intr) 1491 return -EINVAL; 1492 1493 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 1494 pr_err("invalid IRQ index: [%d]\n", irq_idx); 1495 return -EINVAL; 1496 } 1497 1498 irq = &dpu_irq_map[irq_idx]; 1499 reg_idx = irq->reg_idx; 1500 reg = &dpu_intr_set[reg_idx]; 1501 1502 cache_irq_mask = intr->cache_irq_mask[reg_idx]; 1503 if ((cache_irq_mask & irq->irq_mask) == 0) { 1504 dbgstr = "DPU IRQ is already cleared:"; 1505 } else { 1506 dbgstr = "DPU IRQ mask disable:"; 1507 1508 cache_irq_mask &= ~irq->irq_mask; 1509 /* Disable interrupts based on the new mask */ 1510 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); 1511 /* Cleaning any pending interrupt */ 1512 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); 1513 1514 /* ensure register write goes through */ 1515 wmb(); 1516 1517 intr->cache_irq_mask[reg_idx] = cache_irq_mask; 1518 } 1519 1520 pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, 1521 irq->irq_mask, cache_irq_mask); 1522 1523 return 0; 1524 } 1525 1526 static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) 1527 { 1528 unsigned long irq_flags; 1529 1530 if (!intr) 1531 return -EINVAL; 1532 1533 if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { 1534 pr_err("invalid IRQ index: [%d]\n", irq_idx); 1535 return -EINVAL; 1536 } 1537 1538 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1539 dpu_hw_intr_disable_irq_nolock(intr, irq_idx); 1540 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1541 1542 return 0; 1543 } 1544 1545 static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr) 1546 { 1547 int i; 1548 1549 if (!intr) 1550 return -EINVAL; 1551 1552 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 1553 if (test_bit(i, &intr->irq_mask)) 1554 DPU_REG_WRITE(&intr->hw, 1555 dpu_intr_set[i].clr_off, 0xffffffff); 1556 } 1557 1558 /* ensure register writes go through */ 1559 wmb(); 1560 1561 return 0; 1562 } 1563 1564 static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) 1565 { 1566 int i; 1567 1568 if (!intr) 1569 return -EINVAL; 1570 1571 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 1572 if (test_bit(i, &intr->irq_mask)) 1573 DPU_REG_WRITE(&intr->hw, 1574 dpu_intr_set[i].en_off, 0x00000000); 1575 } 1576 1577 /* ensure register writes go through */ 1578 wmb(); 1579 1580 return 0; 1581 } 1582 1583 static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) 1584 { 1585 int i; 1586 u32 enable_mask; 1587 unsigned long irq_flags; 1588 1589 if (!intr) 1590 return; 1591 1592 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1593 for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { 1594 if (!test_bit(i, &intr->irq_mask)) 1595 continue; 1596 1597 /* Read interrupt status */ 1598 intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, 1599 dpu_intr_set[i].status_off); 1600 1601 /* Read enable mask */ 1602 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); 1603 1604 /* and clear the interrupt */ 1605 if (intr->save_irq_status[i]) 1606 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 1607 intr->save_irq_status[i]); 1608 1609 /* Finally update IRQ status based on enable mask */ 1610 intr->save_irq_status[i] &= enable_mask; 1611 } 1612 1613 /* ensure register writes go through */ 1614 wmb(); 1615 1616 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1617 } 1618 1619 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, 1620 int irq_idx) 1621 { 1622 int reg_idx; 1623 1624 if (!intr) 1625 return; 1626 1627 reg_idx = dpu_irq_map[irq_idx].reg_idx; 1628 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, 1629 dpu_irq_map[irq_idx].irq_mask); 1630 1631 /* ensure register writes go through */ 1632 wmb(); 1633 } 1634 1635 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, 1636 int irq_idx, bool clear) 1637 { 1638 int reg_idx; 1639 unsigned long irq_flags; 1640 u32 intr_status; 1641 1642 if (!intr) 1643 return 0; 1644 1645 if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) { 1646 pr_err("invalid IRQ index: [%d]\n", irq_idx); 1647 return 0; 1648 } 1649 1650 spin_lock_irqsave(&intr->irq_lock, irq_flags); 1651 1652 reg_idx = dpu_irq_map[irq_idx].reg_idx; 1653 intr_status = DPU_REG_READ(&intr->hw, 1654 dpu_intr_set[reg_idx].status_off) & 1655 dpu_irq_map[irq_idx].irq_mask; 1656 if (intr_status && clear) 1657 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, 1658 intr_status); 1659 1660 /* ensure register writes go through */ 1661 wmb(); 1662 1663 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); 1664 1665 return intr_status; 1666 } 1667 1668 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) 1669 { 1670 ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup; 1671 ops->enable_irq = dpu_hw_intr_enable_irq; 1672 ops->disable_irq = dpu_hw_intr_disable_irq; 1673 ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; 1674 ops->clear_all_irqs = dpu_hw_intr_clear_irqs; 1675 ops->disable_all_irqs = dpu_hw_intr_disable_irqs; 1676 ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; 1677 ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; 1678 ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; 1679 } 1680 1681 static void __intr_offset(struct dpu_mdss_cfg *m, 1682 void __iomem *addr, struct dpu_hw_blk_reg_map *hw) 1683 { 1684 hw->base_off = addr; 1685 hw->blk_off = m->mdp[0].base; 1686 hw->hwversion = m->hwversion; 1687 } 1688 1689 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, 1690 struct dpu_mdss_cfg *m) 1691 { 1692 struct dpu_hw_intr *intr; 1693 1694 if (!addr || !m) 1695 return ERR_PTR(-EINVAL); 1696 1697 intr = kzalloc(sizeof(*intr), GFP_KERNEL); 1698 if (!intr) 1699 return ERR_PTR(-ENOMEM); 1700 1701 __intr_offset(m, addr, &intr->hw); 1702 __setup_intr_ops(&intr->ops); 1703 1704 intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); 1705 1706 intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), 1707 GFP_KERNEL); 1708 if (intr->cache_irq_mask == NULL) { 1709 kfree(intr); 1710 return ERR_PTR(-ENOMEM); 1711 } 1712 1713 intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), 1714 GFP_KERNEL); 1715 if (intr->save_irq_status == NULL) { 1716 kfree(intr->cache_irq_mask); 1717 kfree(intr); 1718 return ERR_PTR(-ENOMEM); 1719 } 1720 1721 intr->irq_mask = m->mdss_irqs; 1722 intr->obsolete_irq = m->obsolete_irq; 1723 1724 spin_lock_init(&intr->irq_lock); 1725 1726 return intr; 1727 } 1728 1729 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) 1730 { 1731 if (intr) { 1732 kfree(intr->cache_irq_mask); 1733 kfree(intr->save_irq_status); 1734 kfree(intr); 1735 } 1736 } 1737 1738