1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2022, Linaro Limited 4 */ 5 6 #include <drm/drm_managed.h> 7 8 #include <drm/display/drm_dsc_helper.h> 9 10 #include "dpu_kms.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hwio.h" 13 #include "dpu_hw_mdss.h" 14 #include "dpu_hw_dsc.h" 15 16 #define DSC_COMMON_MODE 0x000 17 #define DSC_ENC 0x004 18 #define DSC_PICTURE 0x008 19 #define DSC_SLICE 0x00C 20 #define DSC_CHUNK_SIZE 0x010 21 #define DSC_DELAY 0x014 22 #define DSC_SCALE_INITIAL 0x018 23 #define DSC_SCALE_DEC_INTERVAL 0x01C 24 #define DSC_SCALE_INC_INTERVAL 0x020 25 #define DSC_FIRST_LINE_BPG_OFFSET 0x024 26 #define DSC_BPG_OFFSET 0x028 27 #define DSC_DSC_OFFSET 0x02C 28 #define DSC_FLATNESS 0x030 29 #define DSC_RC_MODEL_SIZE 0x034 30 #define DSC_RC 0x038 31 #define DSC_RC_BUF_THRESH 0x03C 32 #define DSC_RANGE_MIN_QP 0x074 33 #define DSC_RANGE_MAX_QP 0x0B0 34 #define DSC_RANGE_BPG_OFFSET 0x0EC 35 36 #define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0)) 37 38 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) 39 { 40 struct dpu_hw_blk_reg_map *c = &dsc->hw; 41 42 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); 43 } 44 45 static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, 46 struct drm_dsc_config *dsc, 47 u32 mode, 48 u32 initial_lines) 49 { 50 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 51 u32 data; 52 u32 slice_last_group_size; 53 u32 det_thresh_flatness; 54 bool is_cmd_mode = !(mode & DSC_MODE_VIDEO); 55 bool input_10_bits = dsc->bits_per_component == 10; 56 57 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); 58 59 if (is_cmd_mode) 60 initial_lines += 1; 61 62 slice_last_group_size = (dsc->slice_width + 2) % 3; 63 64 data = (initial_lines << 20); 65 data |= (slice_last_group_size << 18); 66 /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ 67 data |= (dsc->bits_per_pixel << 8); 68 data |= (dsc->block_pred_enable << 7); 69 data |= (dsc->line_buf_depth << 3); 70 data |= (dsc->simple_422 << 2); 71 data |= (dsc->convert_rgb << 1); 72 data |= input_10_bits; 73 74 DPU_REG_WRITE(c, DSC_ENC, data); 75 76 data = dsc->pic_width << 16; 77 data |= dsc->pic_height; 78 DPU_REG_WRITE(c, DSC_PICTURE, data); 79 80 data = dsc->slice_width << 16; 81 data |= dsc->slice_height; 82 DPU_REG_WRITE(c, DSC_SLICE, data); 83 84 data = dsc->slice_chunk_size << 16; 85 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); 86 87 data = dsc->initial_dec_delay << 16; 88 data |= dsc->initial_xmit_delay; 89 DPU_REG_WRITE(c, DSC_DELAY, data); 90 91 data = dsc->initial_scale_value; 92 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); 93 94 data = dsc->scale_decrement_interval; 95 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); 96 97 data = dsc->scale_increment_interval; 98 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); 99 100 data = dsc->first_line_bpg_offset; 101 DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data); 102 103 data = dsc->nfl_bpg_offset << 16; 104 data |= dsc->slice_bpg_offset; 105 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); 106 107 data = dsc->initial_offset << 16; 108 data |= dsc->final_offset; 109 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); 110 111 det_thresh_flatness = drm_dsc_flatness_det_thresh(dsc); 112 data = det_thresh_flatness << 10; 113 data |= dsc->flatness_max_qp << 5; 114 data |= dsc->flatness_min_qp; 115 DPU_REG_WRITE(c, DSC_FLATNESS, data); 116 117 data = dsc->rc_model_size; 118 DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data); 119 120 data = dsc->rc_tgt_offset_low << 18; 121 data |= dsc->rc_tgt_offset_high << 14; 122 data |= dsc->rc_quant_incr_limit1 << 9; 123 data |= dsc->rc_quant_incr_limit0 << 4; 124 data |= dsc->rc_edge_factor; 125 DPU_REG_WRITE(c, DSC_RC, data); 126 } 127 128 static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, 129 struct drm_dsc_config *dsc) 130 { 131 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params; 132 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 133 u32 off; 134 int i; 135 136 off = DSC_RC_BUF_THRESH; 137 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) { 138 DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]); 139 off += 4; 140 } 141 142 off = DSC_RANGE_MIN_QP; 143 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 144 DPU_REG_WRITE(c, off, rc[i].range_min_qp); 145 off += 4; 146 } 147 148 off = DSC_RANGE_MAX_QP; 149 for (i = 0; i < 15; i++) { 150 DPU_REG_WRITE(c, off, rc[i].range_max_qp); 151 off += 4; 152 } 153 154 off = DSC_RANGE_BPG_OFFSET; 155 for (i = 0; i < 15; i++) { 156 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); 157 off += 4; 158 } 159 } 160 161 static void dpu_hw_dsc_bind_pingpong_blk( 162 struct dpu_hw_dsc *hw_dsc, 163 const enum dpu_pingpong pp) 164 { 165 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 166 int mux_cfg = 0xF; 167 u32 dsc_ctl_offset; 168 169 dsc_ctl_offset = DSC_CTL(hw_dsc->idx); 170 171 if (pp) 172 mux_cfg = (pp - PINGPONG_0) & 0x7; 173 174 if (pp) 175 DRM_DEBUG_KMS("Binding dsc:%d to pp:%d\n", 176 hw_dsc->idx - DSC_0, pp - PINGPONG_0); 177 else 178 DRM_DEBUG_KMS("Unbinding dsc:%d from any pp\n", 179 hw_dsc->idx - DSC_0); 180 181 DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); 182 } 183 184 static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, 185 unsigned long cap) 186 { 187 ops->dsc_disable = dpu_hw_dsc_disable; 188 ops->dsc_config = dpu_hw_dsc_config; 189 ops->dsc_config_thresh = dpu_hw_dsc_config_thresh; 190 if (cap & BIT(DPU_DSC_OUTPUT_CTRL)) 191 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 192 }; 193 194 /** 195 * dpu_hw_dsc_init() - Initializes the DSC hw driver object. 196 * @dev: Corresponding device for devres management 197 * @cfg: DSC catalog entry for which driver object is required 198 * @addr: Mapped register io address of MDP 199 * Return: Error code or allocated dpu_hw_dsc context 200 */ 201 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 202 const struct dpu_dsc_cfg *cfg, 203 void __iomem *addr) 204 { 205 struct dpu_hw_dsc *c; 206 207 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL); 208 if (!c) 209 return ERR_PTR(-ENOMEM); 210 211 c->hw.blk_addr = addr + cfg->base; 212 c->hw.log_mask = DPU_DBG_MASK_DSC; 213 214 c->idx = cfg->id; 215 c->caps = cfg; 216 _setup_dsc_ops(&c->ops, c->caps->features); 217 218 return c; 219 } 220