1*aae87364SJessica Zhang /* SPDX-License-Identifier: GPL-2.0-only */ 2*aae87364SJessica Zhang /* 3*aae87364SJessica Zhang * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved 4*aae87364SJessica Zhang */ 5*aae87364SJessica Zhang 6*aae87364SJessica Zhang #ifndef _DPU_HW_CWB_H 7*aae87364SJessica Zhang #define _DPU_HW_CWB_H 8*aae87364SJessica Zhang 9*aae87364SJessica Zhang #include "dpu_hw_util.h" 10*aae87364SJessica Zhang 11*aae87364SJessica Zhang struct dpu_hw_cwb; 12*aae87364SJessica Zhang 13*aae87364SJessica Zhang enum cwb_mode_input { 14*aae87364SJessica Zhang INPUT_MODE_LM_OUT, 15*aae87364SJessica Zhang INPUT_MODE_DSPP_OUT, 16*aae87364SJessica Zhang INPUT_MODE_MAX 17*aae87364SJessica Zhang }; 18*aae87364SJessica Zhang 19*aae87364SJessica Zhang /** 20*aae87364SJessica Zhang * struct dpu_hw_cwb_setup_cfg : Describes configuration for CWB mux 21*aae87364SJessica Zhang * @pp_idx: Index of the real-time pinpong that the CWB mux will 22*aae87364SJessica Zhang * feed the CWB mux 23*aae87364SJessica Zhang * @input: Input tap point 24*aae87364SJessica Zhang */ 25*aae87364SJessica Zhang struct dpu_hw_cwb_setup_cfg { 26*aae87364SJessica Zhang enum dpu_pingpong pp_idx; 27*aae87364SJessica Zhang enum cwb_mode_input input; 28*aae87364SJessica Zhang }; 29*aae87364SJessica Zhang 30*aae87364SJessica Zhang /** 31*aae87364SJessica Zhang * 32*aae87364SJessica Zhang * struct dpu_hw_cwb_ops : Interface to the cwb hw driver functions 33*aae87364SJessica Zhang * @config_cwb: configure CWB mux 34*aae87364SJessica Zhang */ 35*aae87364SJessica Zhang struct dpu_hw_cwb_ops { 36*aae87364SJessica Zhang void (*config_cwb)(struct dpu_hw_cwb *ctx, 37*aae87364SJessica Zhang struct dpu_hw_cwb_setup_cfg *cwb_cfg); 38*aae87364SJessica Zhang }; 39*aae87364SJessica Zhang 40*aae87364SJessica Zhang /** 41*aae87364SJessica Zhang * struct dpu_hw_cwb : CWB mux driver object 42*aae87364SJessica Zhang * @base: Hardware block base structure 43*aae87364SJessica Zhang * @hw: Block hardware details 44*aae87364SJessica Zhang * @idx: CWB index 45*aae87364SJessica Zhang * @ops: handle to operations possible for this CWB 46*aae87364SJessica Zhang */ 47*aae87364SJessica Zhang struct dpu_hw_cwb { 48*aae87364SJessica Zhang struct dpu_hw_blk base; 49*aae87364SJessica Zhang struct dpu_hw_blk_reg_map hw; 50*aae87364SJessica Zhang 51*aae87364SJessica Zhang enum dpu_cwb idx; 52*aae87364SJessica Zhang 53*aae87364SJessica Zhang struct dpu_hw_cwb_ops ops; 54*aae87364SJessica Zhang }; 55*aae87364SJessica Zhang 56*aae87364SJessica Zhang /** 57*aae87364SJessica Zhang * dpu_hw_cwb - convert base object dpu_hw_base to container 58*aae87364SJessica Zhang * @hw: Pointer to base hardware block 59*aae87364SJessica Zhang * return: Pointer to hardware block container 60*aae87364SJessica Zhang */ 61*aae87364SJessica Zhang static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw) 62*aae87364SJessica Zhang { 63*aae87364SJessica Zhang return container_of(hw, struct dpu_hw_cwb, base); 64*aae87364SJessica Zhang } 65*aae87364SJessica Zhang 66*aae87364SJessica Zhang struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev, 67*aae87364SJessica Zhang const struct dpu_cwb_cfg *cfg, 68*aae87364SJessica Zhang void __iomem *addr); 69*aae87364SJessica Zhang 70*aae87364SJessica Zhang #endif /*_DPU_HW_CWB_H */ 71