1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_HW_CTL_H 7 #define _DPU_HW_CTL_H 8 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hw_sspp.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @mode_3d: 3d mux configuration 40 * @merge_3d: 3d merge block used 41 * @intf_mode_sel: Interface mode, cmd / vid 42 * @cdm: CDM block used 43 * @stream_sel: Stream selection for multi-stream interfaces 44 * @dsc: DSC BIT masks used 45 * @cwb: CWB BIT masks used 46 */ 47 struct dpu_hw_intf_cfg { 48 enum dpu_intf intf; 49 enum dpu_wb wb; 50 enum dpu_3d_blend_mode mode_3d; 51 enum dpu_merge_3d merge_3d; 52 enum dpu_ctl_mode_sel intf_mode_sel; 53 enum dpu_cdm cdm; 54 int stream_sel; 55 unsigned int cwb; 56 unsigned int dsc; 57 }; 58 59 /** 60 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 61 * Assumption is these functions will be called after clocks are enabled 62 */ 63 struct dpu_hw_ctl_ops { 64 /** 65 * kickoff hw operation for Sw controlled interfaces 66 * DSI cmd mode and WB interface are SW controlled 67 * @ctx : ctl path ctx pointer 68 */ 69 void (*trigger_start)(struct dpu_hw_ctl *ctx); 70 71 /** 72 * check if the ctl is started 73 * @ctx : ctl path ctx pointer 74 * @Return: true if started, false if stopped 75 */ 76 bool (*is_started)(struct dpu_hw_ctl *ctx); 77 78 /** 79 * kickoff prepare is in progress hw operation for sw 80 * controlled interfaces: DSI cmd mode and WB interface 81 * are SW controlled 82 * @ctx : ctl path ctx pointer 83 */ 84 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 85 86 /** 87 * Clear the value of the cached pending_flush_mask 88 * No effect on hardware. 89 * Required to be implemented. 90 * @ctx : ctl path ctx pointer 91 */ 92 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 93 94 /** 95 * Query the value of the cached pending_flush_mask 96 * No effect on hardware 97 * @ctx : ctl path ctx pointer 98 */ 99 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 100 101 /** 102 * OR in the given flushbits to the cached pending_flush_mask 103 * No effect on hardware 104 * @ctx : ctl path ctx pointer 105 * @flushbits : module flushmask 106 */ 107 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 108 u32 flushbits); 109 110 /** 111 * OR in the given flushbits to the cached pending_(wb_)flush_mask 112 * No effect on hardware 113 * @ctx : ctl path ctx pointer 114 * @blk : writeback block index 115 */ 116 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, 117 enum dpu_wb blk); 118 119 /** 120 * OR in the given flushbits to the cached pending_(cwb_)flush_mask 121 * No effect on hardware 122 * @ctx : ctl path ctx pointer 123 * @blk : concurrent writeback block index 124 */ 125 void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx, 126 enum dpu_cwb blk); 127 128 /** 129 * OR in the given flushbits to the cached pending_(intf_)flush_mask 130 * No effect on hardware 131 * @ctx : ctl path ctx pointer 132 * @blk : interface block index 133 */ 134 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, 135 enum dpu_intf blk); 136 137 /** 138 * OR in the given flushbits to the cached pending_(periph_)flush_mask 139 * No effect on hardware 140 * @ctx : ctl path ctx pointer 141 * @blk : interface block index 142 */ 143 void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx, 144 enum dpu_intf blk); 145 146 /** 147 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 148 * No effect on hardware 149 * @ctx : ctl path ctx pointer 150 * @blk : interface block index 151 */ 152 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, 153 enum dpu_merge_3d blk); 154 155 /** 156 * OR in the given flushbits to the cached pending_flush_mask 157 * No effect on hardware 158 * @ctx : ctl path ctx pointer 159 * @blk : SSPP block index 160 */ 161 void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx, 162 enum dpu_sspp blk); 163 164 /** 165 * OR in the given flushbits to the cached pending_flush_mask 166 * No effect on hardware 167 * @ctx : ctl path ctx pointer 168 * @blk : LM block index 169 */ 170 void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx, 171 enum dpu_lm blk); 172 173 /** 174 * OR in the given flushbits to the cached pending_flush_mask 175 * No effect on hardware 176 * @ctx : ctl path ctx pointer 177 * @blk : DSPP block index 178 * @dspp_sub_blk : DSPP sub-block index 179 */ 180 void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, 181 enum dpu_dspp blk, u32 dspp_sub_blk); 182 183 /** 184 * OR in the given flushbits to the cached pending_(dsc_)flush_mask 185 * No effect on hardware 186 * @ctx: ctl path ctx pointer 187 * @blk: interface block index 188 */ 189 void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, 190 enum dpu_dsc blk); 191 192 /** 193 * OR in the given flushbits to the cached pending_(cdm_)flush_mask 194 * No effect on hardware 195 * @ctx: ctl path ctx pointer 196 * @cdm_num: idx of cdm to be flushed 197 */ 198 void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num); 199 200 /** 201 * Write the value of the pending_flush_mask to hardware 202 * @ctx : ctl path ctx pointer 203 */ 204 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 205 206 /** 207 * Read the value of the flush register 208 * @ctx : ctl path ctx pointer 209 * @Return: value of the ctl flush register. 210 */ 211 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 212 213 /** 214 * Setup ctl_path interface config 215 * @ctx 216 * @cfg : interface config structure pointer 217 */ 218 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 219 struct dpu_hw_intf_cfg *cfg); 220 221 /** 222 * reset ctl_path interface config 223 * @ctx : ctl path ctx pointer 224 * @cfg : interface config structure pointer 225 */ 226 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, 227 struct dpu_hw_intf_cfg *cfg); 228 229 int (*reset)(struct dpu_hw_ctl *c); 230 231 /* 232 * wait_reset_status - checks ctl reset status 233 * @ctx : ctl path ctx pointer 234 * 235 * This function checks the ctl reset status bit. 236 * If the reset bit is set, it keeps polling the status till the hw 237 * reset is complete. 238 * Returns: 0 on success or -error if reset incomplete within interval 239 */ 240 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 241 242 /** 243 * Set all blend stages to disabled 244 * @ctx : ctl path ctx pointer 245 */ 246 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 247 248 /** 249 * Configure layer mixer to pipe configuration 250 * @ctx : ctl path ctx pointer 251 * @lm : layer mixer enumeration 252 * @cfg : blend stage configuration 253 */ 254 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 255 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 256 257 void (*set_active_pipes)(struct dpu_hw_ctl *ctx, 258 unsigned long *fetch_active); 259 }; 260 261 /** 262 * struct dpu_hw_ctl : CTL PATH driver object 263 * @base: hardware block base structure 264 * @hw: block register map object 265 * @idx: control path index 266 * @caps: control path capabilities 267 * @mixer_count: number of mixers 268 * @mixer_hw_caps: mixer hardware capabilities 269 * @pending_flush_mask: storage for pending ctl_flush managed via ops 270 * @pending_intf_flush_mask: pending INTF flush 271 * @pending_wb_flush_mask: pending WB flush 272 * @pending_cwb_flush_mask: pending CWB flush 273 * @pending_dsc_flush_mask: pending DSC flush 274 * @pending_cdm_flush_mask: pending CDM flush 275 * @ops: operation list 276 */ 277 struct dpu_hw_ctl { 278 struct dpu_hw_blk base; 279 struct dpu_hw_blk_reg_map hw; 280 281 /* ctl path */ 282 int idx; 283 const struct dpu_ctl_cfg *caps; 284 int mixer_count; 285 const struct dpu_lm_cfg *mixer_hw_caps; 286 u32 pending_flush_mask; 287 u32 pending_intf_flush_mask; 288 u32 pending_wb_flush_mask; 289 u32 pending_cwb_flush_mask; 290 u32 pending_periph_flush_mask; 291 u32 pending_merge_3d_flush_mask; 292 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; 293 u32 pending_dsc_flush_mask; 294 u32 pending_cdm_flush_mask; 295 296 /* ops */ 297 struct dpu_hw_ctl_ops ops; 298 }; 299 300 /** 301 * dpu_hw_ctl - convert base object dpu_hw_base to container 302 * @hw: Pointer to base hardware block 303 * return: Pointer to hardware block container 304 */ 305 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 306 { 307 return container_of(hw, struct dpu_hw_ctl, base); 308 } 309 310 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 311 const struct dpu_ctl_cfg *cfg, 312 void __iomem *addr, 313 u32 mixer_count, 314 const struct dpu_lm_cfg *mixer); 315 316 #endif /*_DPU_HW_CTL_H */ 317