1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_HW_CTL_H 7 #define _DPU_HW_CTL_H 8 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hw_sspp.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @intf_master: Master interface id in the dual pipe topology 40 * @mode_3d: 3d mux configuration 41 * @merge_3d: 3d merge block used 42 * @intf_mode_sel: Interface mode, cmd / vid 43 * @cdm: CDM block used 44 * @stream_sel: Stream selection for multi-stream interfaces 45 * @dsc: DSC BIT masks used 46 * @cwb: CWB BIT masks used 47 */ 48 struct dpu_hw_intf_cfg { 49 enum dpu_intf intf; 50 enum dpu_intf intf_master; 51 enum dpu_wb wb; 52 enum dpu_3d_blend_mode mode_3d; 53 enum dpu_merge_3d merge_3d; 54 enum dpu_ctl_mode_sel intf_mode_sel; 55 enum dpu_cdm cdm; 56 int stream_sel; 57 unsigned int cwb; 58 unsigned int dsc; 59 }; 60 61 /** 62 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 63 * Assumption is these functions will be called after clocks are enabled 64 */ 65 struct dpu_hw_ctl_ops { 66 /** 67 * kickoff hw operation for Sw controlled interfaces 68 * DSI cmd mode and WB interface are SW controlled 69 * @ctx : ctl path ctx pointer 70 */ 71 void (*trigger_start)(struct dpu_hw_ctl *ctx); 72 73 /** 74 * check if the ctl is started 75 * @ctx : ctl path ctx pointer 76 * @Return: true if started, false if stopped 77 */ 78 bool (*is_started)(struct dpu_hw_ctl *ctx); 79 80 /** 81 * kickoff prepare is in progress hw operation for sw 82 * controlled interfaces: DSI cmd mode and WB interface 83 * are SW controlled 84 * @ctx : ctl path ctx pointer 85 */ 86 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 87 88 /** 89 * Clear the value of the cached pending_flush_mask 90 * No effect on hardware. 91 * Required to be implemented. 92 * @ctx : ctl path ctx pointer 93 */ 94 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 95 96 /** 97 * Query the value of the cached pending_flush_mask 98 * No effect on hardware 99 * @ctx : ctl path ctx pointer 100 */ 101 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 102 103 /** 104 * OR in the given flushbits to the cached pending_flush_mask 105 * No effect on hardware 106 * @ctx : ctl path ctx pointer 107 * @flushbits : module flushmask 108 */ 109 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 110 u32 flushbits); 111 112 /** 113 * OR in the given flushbits to the cached pending_(wb_)flush_mask 114 * No effect on hardware 115 * @ctx : ctl path ctx pointer 116 * @blk : writeback block index 117 */ 118 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, 119 enum dpu_wb blk); 120 121 /** 122 * OR in the given flushbits to the cached pending_(cwb_)flush_mask 123 * No effect on hardware 124 * @ctx : ctl path ctx pointer 125 * @blk : concurrent writeback block index 126 */ 127 void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx, 128 enum dpu_cwb blk); 129 130 /** 131 * OR in the given flushbits to the cached pending_(intf_)flush_mask 132 * No effect on hardware 133 * @ctx : ctl path ctx pointer 134 * @blk : interface block index 135 */ 136 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, 137 enum dpu_intf blk); 138 139 /** 140 * OR in the given flushbits to the cached pending_(periph_)flush_mask 141 * No effect on hardware 142 * @ctx : ctl path ctx pointer 143 * @blk : interface block index 144 */ 145 void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx, 146 enum dpu_intf blk); 147 148 /** 149 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 150 * No effect on hardware 151 * @ctx : ctl path ctx pointer 152 * @blk : interface block index 153 */ 154 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, 155 enum dpu_merge_3d blk); 156 157 /** 158 * OR in the given flushbits to the cached pending_flush_mask 159 * No effect on hardware 160 * @ctx : ctl path ctx pointer 161 * @blk : SSPP block index 162 */ 163 void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx, 164 enum dpu_sspp blk); 165 166 /** 167 * OR in the given flushbits to the cached pending_flush_mask 168 * No effect on hardware 169 * @ctx : ctl path ctx pointer 170 * @blk : LM block index 171 */ 172 void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx, 173 enum dpu_lm blk); 174 175 /** 176 * OR in the given flushbits to the cached pending_flush_mask 177 * No effect on hardware 178 * @ctx : ctl path ctx pointer 179 * @blk : DSPP block index 180 * @dspp_sub_blk : DSPP sub-block index 181 */ 182 void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, 183 enum dpu_dspp blk, u32 dspp_sub_blk); 184 185 /** 186 * OR in the given flushbits to the cached pending_(dsc_)flush_mask 187 * No effect on hardware 188 * @ctx: ctl path ctx pointer 189 * @blk: interface block index 190 */ 191 void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, 192 enum dpu_dsc blk); 193 194 /** 195 * OR in the given flushbits to the cached pending_(cdm_)flush_mask 196 * No effect on hardware 197 * @ctx: ctl path ctx pointer 198 * @cdm_num: idx of cdm to be flushed 199 */ 200 void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num); 201 202 /** 203 * Write the value of the pending_flush_mask to hardware 204 * @ctx : ctl path ctx pointer 205 */ 206 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 207 208 /** 209 * Read the value of the flush register 210 * @ctx : ctl path ctx pointer 211 * @Return: value of the ctl flush register. 212 */ 213 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 214 215 /** 216 * Setup ctl_path interface config 217 * @ctx 218 * @cfg : interface config structure pointer 219 */ 220 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 221 struct dpu_hw_intf_cfg *cfg); 222 223 /** 224 * reset ctl_path interface config 225 * @ctx : ctl path ctx pointer 226 * @cfg : interface config structure pointer 227 */ 228 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, 229 struct dpu_hw_intf_cfg *cfg); 230 231 int (*reset)(struct dpu_hw_ctl *c); 232 233 /* 234 * wait_reset_status - checks ctl reset status 235 * @ctx : ctl path ctx pointer 236 * 237 * This function checks the ctl reset status bit. 238 * If the reset bit is set, it keeps polling the status till the hw 239 * reset is complete. 240 * Returns: 0 on success or -error if reset incomplete within interval 241 */ 242 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 243 244 /** 245 * Set all blend stages to disabled 246 * @ctx : ctl path ctx pointer 247 */ 248 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 249 250 /** 251 * Configure layer mixer to pipe configuration 252 * @ctx : ctl path ctx pointer 253 * @lm : layer mixer enumeration 254 * @cfg : blend stage configuration 255 */ 256 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 257 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 258 259 void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, 260 unsigned long *fetch_active); 261 262 /** 263 * Set active pipes attached to this CTL 264 * @ctx: ctl path ctx pointer 265 * @active_pipes: bitmap of enum dpu_sspp 266 */ 267 void (*set_active_pipes)(struct dpu_hw_ctl *ctx, 268 unsigned long *active_pipes); 269 270 /** 271 * Set active layer mixers attached to this CTL 272 * @ctx: ctl path ctx pointer 273 * @active_lms: bitmap of enum dpu_lm 274 */ 275 void (*set_active_lms)(struct dpu_hw_ctl *ctx, 276 unsigned long *active_lms); 277 278 }; 279 280 /** 281 * struct dpu_hw_ctl : CTL PATH driver object 282 * @base: hardware block base structure 283 * @hw: block register map object 284 * @idx: control path index 285 * @caps: control path capabilities 286 * @mixer_count: number of mixers 287 * @mixer_hw_caps: mixer hardware capabilities 288 * @pending_flush_mask: storage for pending ctl_flush managed via ops 289 * @pending_intf_flush_mask: pending INTF flush 290 * @pending_wb_flush_mask: pending WB flush 291 * @pending_cwb_flush_mask: pending CWB flush 292 * @pending_dsc_flush_mask: pending DSC flush 293 * @pending_cdm_flush_mask: pending CDM flush 294 * @mdss_ver: MDSS revision information 295 * @ops: operation list 296 */ 297 struct dpu_hw_ctl { 298 struct dpu_hw_blk base; 299 struct dpu_hw_blk_reg_map hw; 300 301 /* ctl path */ 302 int idx; 303 const struct dpu_ctl_cfg *caps; 304 int mixer_count; 305 const struct dpu_lm_cfg *mixer_hw_caps; 306 u32 pending_flush_mask; 307 u32 pending_intf_flush_mask; 308 u32 pending_wb_flush_mask; 309 u32 pending_cwb_flush_mask; 310 u32 pending_periph_flush_mask; 311 u32 pending_merge_3d_flush_mask; 312 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; 313 u32 pending_dsc_flush_mask; 314 u32 pending_cdm_flush_mask; 315 316 const struct dpu_mdss_version *mdss_ver; 317 318 /* ops */ 319 struct dpu_hw_ctl_ops ops; 320 }; 321 322 /** 323 * dpu_hw_ctl - convert base object dpu_hw_base to container 324 * @hw: Pointer to base hardware block 325 * return: Pointer to hardware block container 326 */ 327 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 328 { 329 return container_of(hw, struct dpu_hw_ctl, base); 330 } 331 332 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 333 const struct dpu_ctl_cfg *cfg, 334 void __iomem *addr, 335 const struct dpu_mdss_version *mdss_ver, 336 u32 mixer_count, 337 const struct dpu_lm_cfg *mixer); 338 339 #endif /*_DPU_HW_CTL_H */ 340