1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_HW_CTL_H 7 #define _DPU_HW_CTL_H 8 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hw_sspp.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @mode_3d: 3d mux configuration 40 * @merge_3d: 3d merge block used 41 * @intf_mode_sel: Interface mode, cmd / vid 42 * @stream_sel: Stream selection for multi-stream interfaces 43 * @dsc: DSC BIT masks used 44 */ 45 struct dpu_hw_intf_cfg { 46 enum dpu_intf intf; 47 enum dpu_wb wb; 48 enum dpu_3d_blend_mode mode_3d; 49 enum dpu_merge_3d merge_3d; 50 enum dpu_ctl_mode_sel intf_mode_sel; 51 int stream_sel; 52 unsigned int dsc; 53 }; 54 55 /** 56 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 57 * Assumption is these functions will be called after clocks are enabled 58 */ 59 struct dpu_hw_ctl_ops { 60 /** 61 * kickoff hw operation for Sw controlled interfaces 62 * DSI cmd mode and WB interface are SW controlled 63 * @ctx : ctl path ctx pointer 64 */ 65 void (*trigger_start)(struct dpu_hw_ctl *ctx); 66 67 /** 68 * check if the ctl is started 69 * @ctx : ctl path ctx pointer 70 * @Return: true if started, false if stopped 71 */ 72 bool (*is_started)(struct dpu_hw_ctl *ctx); 73 74 /** 75 * kickoff prepare is in progress hw operation for sw 76 * controlled interfaces: DSI cmd mode and WB interface 77 * are SW controlled 78 * @ctx : ctl path ctx pointer 79 */ 80 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 81 82 /** 83 * Clear the value of the cached pending_flush_mask 84 * No effect on hardware 85 * @ctx : ctl path ctx pointer 86 */ 87 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 88 89 /** 90 * Query the value of the cached pending_flush_mask 91 * No effect on hardware 92 * @ctx : ctl path ctx pointer 93 */ 94 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 95 96 /** 97 * OR in the given flushbits to the cached pending_flush_mask 98 * No effect on hardware 99 * @ctx : ctl path ctx pointer 100 * @flushbits : module flushmask 101 */ 102 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 103 u32 flushbits); 104 105 /** 106 * OR in the given flushbits to the cached pending_(wb_)flush_mask 107 * No effect on hardware 108 * @ctx : ctl path ctx pointer 109 * @blk : writeback block index 110 */ 111 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, 112 enum dpu_wb blk); 113 114 /** 115 * OR in the given flushbits to the cached pending_(intf_)flush_mask 116 * No effect on hardware 117 * @ctx : ctl path ctx pointer 118 * @blk : interface block index 119 */ 120 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, 121 enum dpu_intf blk); 122 123 /** 124 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 125 * No effect on hardware 126 * @ctx : ctl path ctx pointer 127 * @blk : interface block index 128 */ 129 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, 130 enum dpu_merge_3d blk); 131 132 /** 133 * OR in the given flushbits to the cached pending_flush_mask 134 * No effect on hardware 135 * @ctx : ctl path ctx pointer 136 * @blk : SSPP block index 137 */ 138 void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx, 139 enum dpu_sspp blk); 140 141 /** 142 * OR in the given flushbits to the cached pending_flush_mask 143 * No effect on hardware 144 * @ctx : ctl path ctx pointer 145 * @blk : LM block index 146 */ 147 void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx, 148 enum dpu_lm blk); 149 150 /** 151 * OR in the given flushbits to the cached pending_flush_mask 152 * No effect on hardware 153 * @ctx : ctl path ctx pointer 154 * @blk : DSPP block index 155 * @dspp_sub_blk : DSPP sub-block index 156 */ 157 void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, 158 enum dpu_dspp blk, u32 dspp_sub_blk); 159 160 /** 161 * OR in the given flushbits to the cached pending_(dsc_)flush_mask 162 * No effect on hardware 163 * @ctx: ctl path ctx pointer 164 * @blk: interface block index 165 */ 166 void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, 167 enum dpu_dsc blk); 168 169 /** 170 * Write the value of the pending_flush_mask to hardware 171 * @ctx : ctl path ctx pointer 172 */ 173 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 174 175 /** 176 * Read the value of the flush register 177 * @ctx : ctl path ctx pointer 178 * @Return: value of the ctl flush register. 179 */ 180 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 181 182 /** 183 * Setup ctl_path interface config 184 * @ctx 185 * @cfg : interface config structure pointer 186 */ 187 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 188 struct dpu_hw_intf_cfg *cfg); 189 190 /** 191 * reset ctl_path interface config 192 * @ctx : ctl path ctx pointer 193 * @cfg : interface config structure pointer 194 */ 195 void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx, 196 struct dpu_hw_intf_cfg *cfg); 197 198 int (*reset)(struct dpu_hw_ctl *c); 199 200 /* 201 * wait_reset_status - checks ctl reset status 202 * @ctx : ctl path ctx pointer 203 * 204 * This function checks the ctl reset status bit. 205 * If the reset bit is set, it keeps polling the status till the hw 206 * reset is complete. 207 * Returns: 0 on success or -error if reset incomplete within interval 208 */ 209 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 210 211 /** 212 * Set all blend stages to disabled 213 * @ctx : ctl path ctx pointer 214 */ 215 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 216 217 /** 218 * Configure layer mixer to pipe configuration 219 * @ctx : ctl path ctx pointer 220 * @lm : layer mixer enumeration 221 * @cfg : blend stage configuration 222 */ 223 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 224 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 225 226 void (*set_active_pipes)(struct dpu_hw_ctl *ctx, 227 unsigned long *fetch_active); 228 }; 229 230 /** 231 * struct dpu_hw_ctl : CTL PATH driver object 232 * @base: hardware block base structure 233 * @hw: block register map object 234 * @idx: control path index 235 * @caps: control path capabilities 236 * @mixer_count: number of mixers 237 * @mixer_hw_caps: mixer hardware capabilities 238 * @pending_flush_mask: storage for pending ctl_flush managed via ops 239 * @pending_intf_flush_mask: pending INTF flush 240 * @pending_wb_flush_mask: pending WB flush 241 * @pending_dsc_flush_mask: pending DSC flush 242 * @ops: operation list 243 */ 244 struct dpu_hw_ctl { 245 struct dpu_hw_blk base; 246 struct dpu_hw_blk_reg_map hw; 247 248 /* ctl path */ 249 int idx; 250 const struct dpu_ctl_cfg *caps; 251 int mixer_count; 252 const struct dpu_lm_cfg *mixer_hw_caps; 253 u32 pending_flush_mask; 254 u32 pending_intf_flush_mask; 255 u32 pending_wb_flush_mask; 256 u32 pending_merge_3d_flush_mask; 257 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; 258 u32 pending_dsc_flush_mask; 259 260 /* ops */ 261 struct dpu_hw_ctl_ops ops; 262 }; 263 264 /** 265 * dpu_hw_ctl - convert base object dpu_hw_base to container 266 * @hw: Pointer to base hardware block 267 * return: Pointer to hardware block container 268 */ 269 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 270 { 271 return container_of(hw, struct dpu_hw_ctl, base); 272 } 273 274 /** 275 * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. 276 * Should be called before accessing any ctl_path register. 277 * @cfg: ctl_path catalog entry for which driver object is required 278 * @addr: mapped register io address of MDP 279 * @mixer_count: Number of mixers in @mixer 280 * @mixer: Pointer to an array of Layer Mixers defined in the catalog 281 */ 282 struct dpu_hw_ctl *dpu_hw_ctl_init(const struct dpu_ctl_cfg *cfg, 283 void __iomem *addr, 284 u32 mixer_count, 285 const struct dpu_lm_cfg *mixer); 286 287 /** 288 * dpu_hw_ctl_destroy(): Destroys ctl driver context 289 * should be called to free the context 290 */ 291 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 292 293 #endif /*_DPU_HW_CTL_H */ 294