1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef __DPU_ENCODER_PHYS_H__ 8 #define __DPU_ENCODER_PHYS_H__ 9 10 #include <drm/drm_writeback.h> 11 #include <linux/jiffies.h> 12 13 #include "dpu_kms.h" 14 #include "dpu_hw_intf.h" 15 #include "dpu_hw_wb.h" 16 #include "dpu_hw_pingpong.h" 17 #include "dpu_hw_cdm.h" 18 #include "dpu_hw_ctl.h" 19 #include "dpu_hw_top.h" 20 #include "dpu_hw_util.h" 21 #include "dpu_encoder.h" 22 #include "dpu_crtc.h" 23 24 #define DPU_ENCODER_NAME_MAX 16 25 26 /* wait for at most 2 vsync for lowest refresh rate (24hz) */ 27 #define KICKOFF_TIMEOUT_MS 84 28 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS) 29 30 /** 31 * enum dpu_enc_split_role - Role this physical encoder will play in a 32 * split-panel configuration, where one panel is master, and others slaves. 33 * Masters have extra responsibilities, like managing the VBLANK IRQ. 34 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master. 35 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config. 36 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config. 37 */ 38 enum dpu_enc_split_role { 39 ENC_ROLE_SOLO, 40 ENC_ROLE_MASTER, 41 ENC_ROLE_SLAVE, 42 }; 43 44 /** 45 * enum dpu_enc_enable_state - current enabled state of the physical encoder 46 * @DPU_ENC_DISABLING: Encoder transitioning to disable state 47 * Events bounding transition are encoder type specific 48 * @DPU_ENC_DISABLED: Encoder is disabled 49 * @DPU_ENC_ENABLING: Encoder transitioning to enabled 50 * Events bounding transition are encoder type specific 51 * @DPU_ENC_ENABLED: Encoder is enabled 52 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset 53 * to recover from a previous error 54 */ 55 enum dpu_enc_enable_state { 56 DPU_ENC_DISABLING, 57 DPU_ENC_DISABLED, 58 DPU_ENC_ENABLING, 59 DPU_ENC_ENABLED, 60 DPU_ENC_ERR_NEEDS_HW_RESET 61 }; 62 63 struct dpu_encoder_phys; 64 65 /** 66 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to 67 * the containing virtual encoder. 68 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence 69 * @is_master: Whether this phys_enc is the current master 70 * encoder. Can be switched at enable time. Based 71 * on split_role and current mode (CMD/VID). 72 * @atomic_mode_set: DRM Call. Set a DRM mode. 73 * This likely caches the mode, for use at enable. 74 * @enable: DRM Call. Enable a DRM mode. 75 * @disable: DRM Call. Disable mode. 76 * @atomic_check: DRM Call. Atomic check new DRM state. 77 * @control_vblank_irq Register/Deregister for VBLANK IRQ 78 * @wait_for_commit_done: Wait for hardware to have flushed the 79 * current pending frames to hardware 80 * @wait_for_tx_complete: Wait for hardware to transfer the pixels 81 * to the panel 82 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use 83 * @prepare_for_kickoff: Do any work necessary prior to a kickoff 84 * For CMD encoder, may wait for previous tx done 85 * @handle_post_kickoff: Do any work necessary post-kickoff work 86 * @trigger_start: Process start event on physical encoder 87 * @needs_single_flush: Whether encoder slaves need to be flushed 88 * @irq_control: Handler to enable/disable all the encoder IRQs 89 * @prepare_idle_pc: phys encoder can update the vsync_enable status 90 * on idle power collapse prepare 91 * @restore: Restore all the encoder configs. 92 * @get_line_count: Obtain current vertical line count 93 */ 94 95 struct dpu_encoder_phys_ops { 96 void (*prepare_commit)(struct dpu_encoder_phys *encoder); 97 bool (*is_master)(struct dpu_encoder_phys *encoder); 98 void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, 99 struct drm_crtc_state *crtc_state, 100 struct drm_connector_state *conn_state); 101 void (*enable)(struct dpu_encoder_phys *encoder); 102 void (*disable)(struct dpu_encoder_phys *encoder); 103 int (*atomic_check)(struct dpu_encoder_phys *encoder, 104 struct drm_crtc_state *crtc_state, 105 struct drm_connector_state *conn_state); 106 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); 107 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); 108 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); 109 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc); 110 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); 111 void (*trigger_start)(struct dpu_encoder_phys *phys_enc); 112 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); 113 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); 114 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); 115 void (*restore)(struct dpu_encoder_phys *phys); 116 int (*get_line_count)(struct dpu_encoder_phys *phys); 117 int (*get_frame_count)(struct dpu_encoder_phys *phys); 118 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc, 119 struct drm_writeback_job *job); 120 void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc, 121 struct drm_writeback_job *job); 122 bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc); 123 }; 124 125 /** 126 * enum dpu_intr_idx - dpu encoder interrupt index 127 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel 128 * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel 129 * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel 130 * @INTR_IDX_RDPTR: Readpointer done interrupt for cmd mode panel 131 * @INTR_IDX_WB_DONE: Writeback done interrupt for virtual connector 132 */ 133 enum dpu_intr_idx { 134 INTR_IDX_VSYNC, 135 INTR_IDX_PINGPONG, 136 INTR_IDX_UNDERRUN, 137 INTR_IDX_CTL_START, 138 INTR_IDX_RDPTR, 139 INTR_IDX_WB_DONE, 140 INTR_IDX_MAX, 141 }; 142 143 /** 144 * struct dpu_encoder_phys - physical encoder that drives a single INTF block 145 * tied to a specific panel / sub-panel. Abstract type, sub-classed by 146 * phys_vid or phys_cmd for video mode or command mode encs respectively. 147 * @parent: Pointer to the containing virtual encoder 148 * @ops: Operations exposed to the virtual encoder 149 * @parent_ops: Callbacks exposed by the parent to the phys_enc 150 * @hw_mdptop: Hardware interface to the top registers 151 * @hw_ctl: Hardware interface to the ctl registers 152 * @hw_pp: Hardware interface to the ping pong registers 153 * @hw_intf: Hardware interface to the intf registers 154 * @hw_wb: Hardware interface to the wb registers 155 * @hw_cdm: Hardware interface to the CDM registers 156 * @dpu_kms: Pointer to the dpu_kms top level 157 * @cached_mode: DRM mode cached at mode_set time, acted on in enable 158 * @vblank_ctl_lock: Vblank ctl mutex lock to protect vblank_refcount 159 * @enabled: Whether the encoder has enabled and running a mode 160 * @split_role: Role to play in a split-panel configuration 161 * @intf_mode: Interface mode 162 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 163 * @enable_state: Enable state tracking 164 * @vblank_refcount: Reference count of vblank request 165 * @vsync_cnt: Vsync count for the physical encoder 166 * @underrun_cnt: Underrun count for the physical encoder 167 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs 168 * vs. the number of done/vblank irqs. Should hover 169 * between 0-2 Incremented when a new kickoff is 170 * scheduled. Decremented in irq handler 171 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start 172 * pending. 173 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes 174 * @irq: IRQ indices 175 * @has_intf_te: Interface TE configuration support 176 */ 177 struct dpu_encoder_phys { 178 struct drm_encoder *parent; 179 struct dpu_encoder_phys_ops ops; 180 struct dpu_hw_mdp *hw_mdptop; 181 struct dpu_hw_ctl *hw_ctl; 182 struct dpu_hw_pingpong *hw_pp; 183 struct dpu_hw_intf *hw_intf; 184 struct dpu_hw_wb *hw_wb; 185 struct dpu_hw_cdm *hw_cdm; 186 struct dpu_kms *dpu_kms; 187 struct drm_display_mode cached_mode; 188 struct mutex vblank_ctl_lock; 189 enum dpu_enc_split_role split_role; 190 enum dpu_intf_mode intf_mode; 191 spinlock_t *enc_spinlock; 192 enum dpu_enc_enable_state enable_state; 193 int vblank_refcount; 194 atomic_t vsync_cnt; 195 atomic_t underrun_cnt; 196 atomic_t pending_ctlstart_cnt; 197 atomic_t pending_kickoff_cnt; 198 wait_queue_head_t pending_kickoff_wq; 199 unsigned int irq[INTR_IDX_MAX]; 200 bool has_intf_te; 201 }; 202 203 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) 204 { 205 atomic_inc_return(&phys->pending_ctlstart_cnt); 206 return atomic_inc_return(&phys->pending_kickoff_cnt); 207 } 208 209 /** 210 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command 211 * mode specific operations 212 * @base: Baseclass physical encoder structure 213 * @wbirq_refcount: Reference count of writeback interrupt 214 * @wb_done_timeout_cnt: number of wb done irq timeout errors 215 * @wb_cfg: writeback block config to store fb related details 216 * @cdm_cfg: cdm block config needed to store writeback block's CDM configuration 217 * @wb_conn: backpointer to writeback connector 218 * @wb_job: backpointer to current writeback job 219 * @dest: dpu buffer layout for current writeback output buffer 220 */ 221 struct dpu_encoder_phys_wb { 222 struct dpu_encoder_phys base; 223 atomic_t wbirq_refcount; 224 int wb_done_timeout_cnt; 225 struct dpu_hw_wb_cfg wb_cfg; 226 struct dpu_hw_cdm_cfg cdm_cfg; 227 struct drm_writeback_connector *wb_conn; 228 struct drm_writeback_job *wb_job; 229 struct dpu_hw_fmt_layout dest; 230 }; 231 232 /** 233 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command 234 * mode specific operations 235 * @base: Baseclass physical encoder structure 236 * @intf_idx: Intf Block index used by this phys encoder 237 * @stream_sel: Stream selection for multi-stream interfaces 238 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt 239 * after ctl_start instead of before next frame kickoff 240 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors 241 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK 242 * @pending_vblank_wq: Wait queue for blocking until VBLANK received 243 */ 244 struct dpu_encoder_phys_cmd { 245 struct dpu_encoder_phys base; 246 int stream_sel; 247 bool serialize_wait4pp; 248 int pp_timeout_report_cnt; 249 atomic_t pending_vblank_cnt; 250 wait_queue_head_t pending_vblank_wq; 251 }; 252 253 /** 254 * struct dpu_enc_phys_init_params - initialization parameters for phys encs 255 * @dpu_kms: Pointer to the dpu_kms top level 256 * @parent: Pointer to the containing virtual encoder 257 * @parent_ops: Callbacks exposed by the parent to the phys_enc 258 * @split_role: Role to play in a split-panel configuration 259 * @hw_intf: Hardware interface to the intf registers 260 * @hw_wb: Hardware interface to the wb registers 261 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 262 */ 263 struct dpu_enc_phys_init_params { 264 struct dpu_kms *dpu_kms; 265 struct drm_encoder *parent; 266 enum dpu_enc_split_role split_role; 267 struct dpu_hw_intf *hw_intf; 268 struct dpu_hw_wb *hw_wb; 269 spinlock_t *enc_spinlock; 270 }; 271 272 /** 273 * dpu_encoder_wait_info - container for passing arguments to irq wait functions 274 * @wq: wait queue structure 275 * @atomic_cnt: wait until atomic_cnt equals zero 276 * @timeout_ms: timeout value in milliseconds 277 */ 278 struct dpu_encoder_wait_info { 279 wait_queue_head_t *wq; 280 atomic_t *atomic_cnt; 281 s64 timeout_ms; 282 }; 283 284 /** 285 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 286 * @p: Pointer to init params structure 287 * Return: Error code or newly allocated encoder 288 */ 289 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, 290 struct dpu_enc_phys_init_params *p); 291 292 /** 293 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 294 * @dev: Corresponding device for devres management 295 * @p: Pointer to init params structure 296 * Return: Error code or newly allocated encoder 297 */ 298 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, 299 struct dpu_enc_phys_init_params *p); 300 301 /** 302 * dpu_encoder_phys_wb_init - initialize writeback encoder 303 * @dev: Corresponding device for devres management 304 * @init: Pointer to init info structure with initialization params 305 */ 306 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, 307 struct dpu_enc_phys_init_params *p); 308 309 /** 310 * dpu_encoder_helper_trigger_start - control start helper function 311 * This helper function may be optionally specified by physical 312 * encoders if they require ctl_start triggering. 313 * @phys_enc: Pointer to physical encoder structure 314 */ 315 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 316 317 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 318 struct dpu_encoder_phys *phys_enc) 319 { 320 struct dpu_crtc_state *dpu_cstate; 321 322 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) 323 return BLEND_3D_NONE; 324 325 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); 326 327 /* Use merge_3d unless DSC MERGE topology is used */ 328 if (phys_enc->split_role == ENC_ROLE_SOLO && 329 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS && 330 !dpu_encoder_use_dsc_merge(phys_enc->parent)) 331 return BLEND_3D_H_ROW_INT; 332 333 return BLEND_3D_NONE; 334 } 335 336 /** 337 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 338 * This helper function is used by physical encoder to get DSC blocks mask 339 * used for this encoder. 340 * @phys_enc: Pointer to physical encoder structure 341 */ 342 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); 343 344 /** 345 * dpu_encoder_helper_split_config - split display configuration helper function 346 * This helper function may be used by physical encoders to configure 347 * the split display related registers. 348 * @phys_enc: Pointer to physical encoder structure 349 * @interface: enum dpu_intf setting 350 */ 351 void dpu_encoder_helper_split_config( 352 struct dpu_encoder_phys *phys_enc, 353 enum dpu_intf interface); 354 355 /** 356 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 357 * timed out, including reporting frame error event to crtc and debug dump 358 * @phys_enc: Pointer to physical encoder structure 359 * @intr_idx: Failing interrupt index 360 */ 361 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 362 enum dpu_intr_idx intr_idx); 363 364 /** 365 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 366 * note: will call dpu_encoder_helper_wait_for_irq on timeout 367 * @phys_enc: Pointer to physical encoder structure 368 * @irq: IRQ index 369 * @func: IRQ callback to be called in case of timeout 370 * @wait_info: wait info struct 371 * @Return: 0 or -ERROR 372 */ 373 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 374 unsigned int irq, 375 void (*func)(void *arg), 376 struct dpu_encoder_wait_info *wait_info); 377 378 /** 379 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 380 * @phys_enc: Pointer to physical encoder structure 381 */ 382 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 383 384 /** 385 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 386 * @drm_enc: Pointer to drm encoder structure 387 * @phys_enc: Pointer to physical encoder 388 * Note: This is called from IRQ handler context. 389 */ 390 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 391 struct dpu_encoder_phys *phy_enc); 392 393 /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 394 * @drm_enc: Pointer to drm encoder structure 395 * @phys_enc: Pointer to physical encoder 396 * Note: This is called from IRQ handler context. 397 */ 398 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 399 struct dpu_encoder_phys *phy_enc); 400 401 /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame 402 * @drm_enc: Pointer to drm encoder structure 403 * @phys_enc: Pointer to physical encoder 404 * @event: Event to process 405 */ 406 void dpu_encoder_frame_done_callback( 407 struct drm_encoder *drm_enc, 408 struct dpu_encoder_phys *ready_phys, u32 event); 409 410 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys, 411 struct dpu_enc_phys_init_params *p); 412 413 #endif /* __dpu_encoder_phys_H__ */ 414