xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h (revision 37744feebc086908fd89760650f458ab19071750)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #ifndef __DPU_ENCODER_H__
9 #define __DPU_ENCODER_H__
10 
11 #include <drm/drm_crtc.h>
12 #include "dpu_hw_mdss.h"
13 
14 #define DPU_ENCODER_FRAME_EVENT_DONE			BIT(0)
15 #define DPU_ENCODER_FRAME_EVENT_ERROR			BIT(1)
16 #define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD		BIT(2)
17 #define DPU_ENCODER_FRAME_EVENT_IDLE			BIT(3)
18 
19 #define IDLE_TIMEOUT	(66 - 16/2)
20 
21 /**
22  * Encoder functions and data types
23  * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
24  */
25 struct dpu_encoder_hw_resources {
26 	enum dpu_intf_mode intfs[INTF_MAX];
27 };
28 
29 /**
30  * dpu_encoder_get_hw_resources - Populate table of required hardware resources
31  * @encoder:	encoder pointer
32  * @hw_res:	resource table to populate with encoder required resources
33  */
34 void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,
35 				  struct dpu_encoder_hw_resources *hw_res);
36 
37 /**
38  * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
39  * @encoder:	encoder pointer
40  * @crtc:	crtc pointer
41  */
42 void dpu_encoder_assign_crtc(struct drm_encoder *encoder,
43 			     struct drm_crtc *crtc);
44 
45 /**
46  * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if
47  *	the encoder is assigned to the given crtc
48  * @encoder:	encoder pointer
49  * @crtc:	crtc pointer
50  * @enable:	true if vblank should be enabled
51  */
52 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder,
53 					struct drm_crtc *crtc, bool enable);
54 
55 /**
56  * dpu_encoder_register_frame_event_callback - provide callback to encoder that
57  *	will be called after the request is complete, or other events.
58  * @encoder:	encoder pointer
59  * @cb:		callback pointer, provide NULL to deregister
60  * @data:	user data provided to callback
61  */
62 void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder,
63 		void (*cb)(void *, u32), void *data);
64 
65 /**
66  * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
67  *	path (i.e. ctl flush and start) at next appropriate time.
68  *	Immediately: if no previous commit is outstanding.
69  *	Delayed: Block until next trigger can be issued.
70  * @encoder:	encoder pointer
71  */
72 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
73 
74 /**
75  * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
76  *        kickoff and trigger the ctl prepare progress for command mode display.
77  * @encoder:	encoder pointer
78  */
79 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
80 
81 /**
82  * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
83  *	(i.e. ctl flush and start) immediately.
84  * @encoder:	encoder pointer
85  */
86 void dpu_encoder_kickoff(struct drm_encoder *encoder);
87 
88 /**
89  * dpu_encoder_wakeup_time - get the time of the next vsync
90  */
91 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time);
92 
93 /**
94  * dpu_encoder_wait_for_event - Waits for encoder events
95  * @encoder:	encoder pointer
96  * @event:      event to wait for
97  * MSM_ENC_COMMIT_DONE -  Wait for hardware to have flushed the current pending
98  *                        frames to hardware at a vblank or ctl_start
99  *                        Encoders will map this differently depending on the
100  *                        panel type.
101  *	                  vid mode -> vsync_irq
102  *                        cmd mode -> ctl_start
103  * MSM_ENC_TX_COMPLETE -  Wait for the hardware to transfer all the pixels to
104  *                        the panel. Encoders will map this differently
105  *                        depending on the panel type.
106  *                        vid mode -> vsync_irq
107  *                        cmd mode -> pp_done
108  * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
109  */
110 int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
111 						enum msm_event_wait event);
112 
113 /*
114  * dpu_encoder_get_intf_mode - get interface mode of the given encoder
115  * @encoder: Pointer to drm encoder object
116  */
117 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder);
118 
119 /**
120  * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs
121  * @encoder:	encoder pointer
122  */
123 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder);
124 
125 /**
126  * dpu_encoder_init - initialize virtual encoder object
127  * @dev:        Pointer to drm device structure
128  * @disp_info:  Pointer to display information structure
129  * Returns:     Pointer to newly created drm encoder
130  */
131 struct drm_encoder *dpu_encoder_init(
132 		struct drm_device *dev,
133 		int drm_enc_mode);
134 
135 /**
136  * dpu_encoder_setup - setup dpu_encoder for the display probed
137  * @dev:		Pointer to drm device structure
138  * @enc:		Pointer to the drm_encoder
139  * @disp_info:	Pointer to the display info
140  */
141 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
142 		struct msm_display_info *disp_info);
143 
144 /**
145  * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
146  *	atomic commit, before any registers are written
147  * @drm_enc:    Pointer to previously created drm encoder structure
148  */
149 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc);
150 
151 /**
152  * dpu_encoder_set_idle_timeout - set the idle timeout for video
153  *                    and command mode encoders.
154  * @drm_enc:    Pointer to previously created drm encoder structure
155  * @idle_timeout:    idle timeout duration in milliseconds
156  */
157 void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc,
158 							u32 idle_timeout);
159 
160 #endif /* __DPU_ENCODER_H__ */
161