1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_framebuffer.h> 20 21 #include "msm_drv.h" 22 #include "dpu_kms.h" 23 #include "dpu_hwio.h" 24 #include "dpu_hw_catalog.h" 25 #include "dpu_hw_intf.h" 26 #include "dpu_hw_ctl.h" 27 #include "dpu_hw_cwb.h" 28 #include "dpu_hw_dspp.h" 29 #include "dpu_hw_dsc.h" 30 #include "dpu_hw_merge3d.h" 31 #include "dpu_hw_cdm.h" 32 #include "dpu_formats.h" 33 #include "dpu_encoder_phys.h" 34 #include "dpu_crtc.h" 35 #include "dpu_trace.h" 36 #include "dpu_core_irq.h" 37 #include "disp/msm_disp_snapshot.h" 38 39 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 41 42 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 44 45 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\ 46 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 47 48 /* 49 * Two to anticipate panels that can do cmd/vid dynamic switching 50 * plan is to create all possible physical encoder types, and switch between 51 * them at runtime 52 */ 53 #define NUM_PHYS_ENCODER_TYPES 2 54 55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 57 58 #define MAX_CHANNELS_PER_ENC 2 59 60 #define IDLE_SHORT_TIMEOUT 1 61 62 /* timeout in frames waiting for frame done */ 63 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 64 65 /** 66 * enum dpu_enc_rc_events - events for resource control state machine 67 * @DPU_ENC_RC_EVENT_KICKOFF: 68 * This event happens at NORMAL priority. 69 * Event that signals the start of the transfer. When this event is 70 * received, enable MDP/DSI core clocks. Regardless of the previous 71 * state, the resource should be in ON state at the end of this event. 72 * @DPU_ENC_RC_EVENT_FRAME_DONE: 73 * This event happens at INTERRUPT level. 74 * Event signals the end of the data transfer after the PP FRAME_DONE 75 * event. At the end of this event, a delayed work is scheduled to go to 76 * IDLE_PC state after IDLE_TIMEOUT time. 77 * @DPU_ENC_RC_EVENT_PRE_STOP: 78 * This event happens at NORMAL priority. 79 * This event, when received during the ON state, leave the RC STATE 80 * in the PRE_OFF state. It should be followed by the STOP event as 81 * part of encoder disable. 82 * If received during IDLE or OFF states, it will do nothing. 83 * @DPU_ENC_RC_EVENT_STOP: 84 * This event happens at NORMAL priority. 85 * When this event is received, disable all the MDP/DSI core clocks, and 86 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 87 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 88 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 89 * Resource state should be in OFF at the end of the event. 90 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 91 * This event happens at NORMAL priority from a work item. 92 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 93 * This would disable MDP/DSI core clocks and change the resource state 94 * to IDLE. 95 */ 96 enum dpu_enc_rc_events { 97 DPU_ENC_RC_EVENT_KICKOFF = 1, 98 DPU_ENC_RC_EVENT_FRAME_DONE, 99 DPU_ENC_RC_EVENT_PRE_STOP, 100 DPU_ENC_RC_EVENT_STOP, 101 DPU_ENC_RC_EVENT_ENTER_IDLE 102 }; 103 104 /* 105 * enum dpu_enc_rc_states - states that the resource control maintains 106 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 107 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 108 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 109 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 110 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 111 */ 112 enum dpu_enc_rc_states { 113 DPU_ENC_RC_STATE_OFF, 114 DPU_ENC_RC_STATE_PRE_OFF, 115 DPU_ENC_RC_STATE_ON, 116 DPU_ENC_RC_STATE_IDLE 117 }; 118 119 /** 120 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 121 * encoders. Virtual encoder manages one "logical" display. Physical 122 * encoders manage one intf block, tied to a specific panel/sub-panel. 123 * Virtual encoder defers as much as possible to the physical encoders. 124 * Virtual encoder registers itself with the DRM Framework as the encoder. 125 * @base: drm_encoder base class for registration with DRM 126 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 127 * @enabled: True if the encoder is active, protected by enc_lock 128 * @commit_done_timedout: True if there has been a timeout on commit after 129 * enabling the encoder. 130 * @num_phys_encs: Actual number of physical encoders contained. 131 * @phys_encs: Container of physical encoders managed. 132 * @cur_master: Pointer to the current master in this mode. Optimization 133 * Only valid after enable. Cleared as disable. 134 * @cur_slave: As above but for the slave encoder. 135 * @hw_pp: Handle to the pingpong blocks used for the display. No. 136 * pingpong blocks can be different than num_phys_encs. 137 * @hw_cwb: Handle to the CWB muxes used for concurrent writeback 138 * display. Number of CWB muxes can be different than 139 * num_phys_encs. 140 * @hw_dsc: Handle to the DSC blocks used for the display. 141 * @dsc_mask: Bitmask of used DSC blocks. 142 * @cwb_mask: Bitmask of used CWB muxes 143 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 144 * for partial update right-only cases, such as pingpong 145 * split where virtual pingpong does not generate IRQs 146 * @crtc: Pointer to the currently assigned crtc. Normally you 147 * would use crtc->state->encoder_mask to determine the 148 * link between encoder/crtc. However in this case we need 149 * to track crtc in the disable() hook which is called 150 * _after_ encoder_mask is cleared. 151 * @connector: If a mode is set, cached pointer to the active connector 152 * @enc_lock: Lock around physical encoder 153 * create/destroy/enable/disable 154 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 155 * busy processing current command. 156 * Bit0 = phys_encs[0] etc. 157 * @frame_done_timeout_ms: frame done timeout in ms 158 * @frame_done_timeout_cnt: atomic counter tracking the number of frame 159 * done timeouts 160 * @frame_done_timer: watchdog timer for frame done event 161 * @disp_info: local copy of msm_display_info struct 162 * @idle_pc_supported: indicate if idle power collaps is supported 163 * @rc_lock: resource control mutex lock to protect 164 * virt encoder over various state changes 165 * @rc_state: resource controller state 166 * @delayed_off_work: delayed worker to schedule disabling of 167 * clks and resources after IDLE_TIMEOUT time. 168 * @topology: topology of the display 169 * @idle_timeout: idle timeout duration in milliseconds 170 * @wide_bus_en: wide bus is enabled on this interface 171 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 172 */ 173 struct dpu_encoder_virt { 174 struct drm_encoder base; 175 spinlock_t enc_spinlock; 176 177 bool enabled; 178 bool commit_done_timedout; 179 180 unsigned int num_phys_encs; 181 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 182 struct dpu_encoder_phys *cur_master; 183 struct dpu_encoder_phys *cur_slave; 184 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 185 struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC]; 186 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 187 188 unsigned int dsc_mask; 189 unsigned int cwb_mask; 190 191 bool intfs_swapped; 192 193 struct drm_crtc *crtc; 194 struct drm_connector *connector; 195 196 struct mutex enc_lock; 197 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 198 199 atomic_t frame_done_timeout_ms; 200 atomic_t frame_done_timeout_cnt; 201 struct timer_list frame_done_timer; 202 203 struct msm_display_info disp_info; 204 205 bool idle_pc_supported; 206 struct mutex rc_lock; 207 enum dpu_enc_rc_states rc_state; 208 struct delayed_work delayed_off_work; 209 struct msm_display_topology topology; 210 211 u32 idle_timeout; 212 213 bool wide_bus_en; 214 215 /* DSC configuration */ 216 struct drm_dsc_config *dsc; 217 }; 218 219 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 220 221 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 222 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 223 }; 224 225 /** 226 * dpu_encoder_get_drm_fmt - return DRM fourcc format 227 * @phys_enc: Pointer to physical encoder structure 228 */ 229 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) 230 { 231 struct drm_encoder *drm_enc; 232 struct dpu_encoder_virt *dpu_enc; 233 struct drm_display_info *info; 234 struct drm_display_mode *mode; 235 236 drm_enc = phys_enc->parent; 237 dpu_enc = to_dpu_encoder_virt(drm_enc); 238 info = &dpu_enc->connector->display_info; 239 mode = &phys_enc->cached_mode; 240 241 if (drm_mode_is_420_only(info, mode)) 242 return DRM_FORMAT_YUV420; 243 244 return DRM_FORMAT_RGB888; 245 } 246 247 /** 248 * dpu_encoder_needs_periph_flush - return true if physical encoder requires 249 * peripheral flush 250 * @phys_enc: Pointer to physical encoder structure 251 */ 252 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) 253 { 254 struct drm_encoder *drm_enc; 255 struct dpu_encoder_virt *dpu_enc; 256 struct msm_display_info *disp_info; 257 struct msm_drm_private *priv; 258 struct drm_display_mode *mode; 259 260 drm_enc = phys_enc->parent; 261 dpu_enc = to_dpu_encoder_virt(drm_enc); 262 disp_info = &dpu_enc->disp_info; 263 priv = drm_enc->dev->dev_private; 264 mode = &phys_enc->cached_mode; 265 266 return phys_enc->hw_intf->cap->type == INTF_DP && 267 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode); 268 } 269 270 /** 271 * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 272 * @drm_enc: Pointer to previously created drm encoder structure 273 */ 274 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 275 { 276 const struct dpu_encoder_virt *dpu_enc; 277 struct msm_drm_private *priv = drm_enc->dev->dev_private; 278 const struct msm_display_info *disp_info; 279 int index; 280 281 dpu_enc = to_dpu_encoder_virt(drm_enc); 282 disp_info = &dpu_enc->disp_info; 283 index = disp_info->h_tile_instance[0]; 284 285 if (disp_info->intf_type == INTF_DP) 286 return msm_dp_wide_bus_available(priv->dp[index]); 287 else if (disp_info->intf_type == INTF_DSI) 288 return msm_dsi_wide_bus_enabled(priv->dsi[index]); 289 290 return false; 291 } 292 293 /** 294 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 295 * for the encoder. 296 * @drm_enc: Pointer to previously created drm encoder structure 297 */ 298 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) 299 { 300 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 301 302 return dpu_enc->dsc ? true : false; 303 } 304 305 /** 306 * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 307 * in virtual encoder that can collect CRC values 308 * @drm_enc: Pointer to previously created drm encoder structure 309 * Returns: Number of physical encoders for given drm encoder 310 */ 311 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 312 { 313 struct dpu_encoder_virt *dpu_enc; 314 int i, num_intf = 0; 315 316 dpu_enc = to_dpu_encoder_virt(drm_enc); 317 318 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 319 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 320 321 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 322 && phys->hw_intf->ops.collect_misr) 323 num_intf++; 324 } 325 326 return num_intf; 327 } 328 329 /** 330 * dpu_encoder_setup_misr - enable misr calculations 331 * @drm_enc: Pointer to previously created drm encoder structure 332 */ 333 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 334 { 335 struct dpu_encoder_virt *dpu_enc; 336 337 int i; 338 339 dpu_enc = to_dpu_encoder_virt(drm_enc); 340 341 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 342 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 343 344 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 345 continue; 346 347 phys->hw_intf->ops.setup_misr(phys->hw_intf); 348 } 349 } 350 351 /** 352 * dpu_encoder_get_crc - get the crc value from interface blocks 353 * @drm_enc: Pointer to previously created drm encoder structure 354 * @crcs: array to fill with CRC data 355 * @pos: offset into the @crcs array 356 * Returns: 0 on success, error otherwise 357 */ 358 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 359 { 360 struct dpu_encoder_virt *dpu_enc; 361 362 int i, rc = 0, entries_added = 0; 363 364 if (!drm_enc->crtc) { 365 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 366 return -EINVAL; 367 } 368 369 dpu_enc = to_dpu_encoder_virt(drm_enc); 370 371 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 372 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 373 374 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 375 continue; 376 377 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 378 if (rc) 379 return rc; 380 entries_added++; 381 } 382 383 return entries_added; 384 } 385 386 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 387 { 388 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 389 390 if (!hw_pp->ops.setup_dither) 391 return; 392 393 switch (bpc) { 394 case 6: 395 dither_cfg.c0_bitdepth = 6; 396 dither_cfg.c1_bitdepth = 6; 397 dither_cfg.c2_bitdepth = 6; 398 dither_cfg.c3_bitdepth = 6; 399 dither_cfg.temporal_en = 0; 400 break; 401 default: 402 hw_pp->ops.setup_dither(hw_pp, NULL); 403 return; 404 } 405 406 memcpy(&dither_cfg.matrix, dither_matrix, 407 sizeof(u32) * DITHER_MATRIX_SZ); 408 409 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 410 } 411 412 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 413 { 414 switch (intf_mode) { 415 case INTF_MODE_VIDEO: 416 return "INTF_MODE_VIDEO"; 417 case INTF_MODE_CMD: 418 return "INTF_MODE_CMD"; 419 case INTF_MODE_WB_BLOCK: 420 return "INTF_MODE_WB_BLOCK"; 421 case INTF_MODE_WB_LINE: 422 return "INTF_MODE_WB_LINE"; 423 default: 424 return "INTF_MODE_UNKNOWN"; 425 } 426 } 427 428 /** 429 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 430 * timed out, including reporting frame error event to crtc and debug dump 431 * @phys_enc: Pointer to physical encoder structure 432 * @intr_idx: Failing interrupt index 433 */ 434 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 435 enum dpu_intr_idx intr_idx) 436 { 437 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 438 DRMID(phys_enc->parent), 439 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 440 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 441 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 442 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 443 444 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 445 DPU_ENCODER_FRAME_EVENT_ERROR); 446 } 447 448 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 449 u32 irq_idx, struct dpu_encoder_wait_info *info); 450 451 /** 452 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 453 * note: will call dpu_encoder_helper_wait_for_irq on timeout 454 * @phys_enc: Pointer to physical encoder structure 455 * @irq_idx: IRQ index 456 * @func: IRQ callback to be called in case of timeout 457 * @wait_info: wait info struct 458 * @return: 0 or -ERROR 459 */ 460 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 461 unsigned int irq_idx, 462 void (*func)(void *arg), 463 struct dpu_encoder_wait_info *wait_info) 464 { 465 u32 irq_status; 466 int ret; 467 468 if (!wait_info) { 469 DPU_ERROR("invalid params\n"); 470 return -EINVAL; 471 } 472 /* note: do master / slave checking outside */ 473 474 /* return EWOULDBLOCK since we know the wait isn't necessary */ 475 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 476 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 477 DRMID(phys_enc->parent), func, 478 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 479 return -EWOULDBLOCK; 480 } 481 482 if (irq_idx == 0) { 483 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 484 DRMID(phys_enc->parent), func); 485 return 0; 486 } 487 488 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 489 DRMID(phys_enc->parent), func, 490 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 491 atomic_read(wait_info->atomic_cnt)); 492 493 ret = dpu_encoder_helper_wait_event_timeout( 494 DRMID(phys_enc->parent), 495 irq_idx, 496 wait_info); 497 498 if (ret <= 0) { 499 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 500 if (irq_status) { 501 unsigned long flags; 502 503 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 504 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 505 DRMID(phys_enc->parent), func, 506 phys_enc->hw_pp->idx - PINGPONG_0, 507 atomic_read(wait_info->atomic_cnt)); 508 local_irq_save(flags); 509 func(phys_enc); 510 local_irq_restore(flags); 511 ret = 0; 512 } else { 513 ret = -ETIMEDOUT; 514 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 515 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 516 DRMID(phys_enc->parent), func, 517 phys_enc->hw_pp->idx - PINGPONG_0, 518 atomic_read(wait_info->atomic_cnt)); 519 } 520 } else { 521 ret = 0; 522 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 523 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 524 phys_enc->hw_pp->idx - PINGPONG_0, 525 atomic_read(wait_info->atomic_cnt)); 526 } 527 528 return ret; 529 } 530 531 /** 532 * dpu_encoder_get_vsync_count - get vsync count for the encoder. 533 * @drm_enc: Pointer to previously created drm encoder structure 534 */ 535 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 536 { 537 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 538 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 539 return phys ? atomic_read(&phys->vsync_cnt) : 0; 540 } 541 542 /** 543 * dpu_encoder_get_linecount - get interface line count for the encoder. 544 * @drm_enc: Pointer to previously created drm encoder structure 545 */ 546 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 547 { 548 struct dpu_encoder_virt *dpu_enc; 549 struct dpu_encoder_phys *phys; 550 int linecount = 0; 551 552 dpu_enc = to_dpu_encoder_virt(drm_enc); 553 phys = dpu_enc ? dpu_enc->cur_master : NULL; 554 555 if (phys && phys->ops.get_line_count) 556 linecount = phys->ops.get_line_count(phys); 557 558 return linecount; 559 } 560 561 /** 562 * dpu_encoder_helper_split_config - split display configuration helper function 563 * This helper function may be used by physical encoders to configure 564 * the split display related registers. 565 * @phys_enc: Pointer to physical encoder structure 566 * @interface: enum dpu_intf setting 567 */ 568 void dpu_encoder_helper_split_config( 569 struct dpu_encoder_phys *phys_enc, 570 enum dpu_intf interface) 571 { 572 struct dpu_encoder_virt *dpu_enc; 573 struct split_pipe_cfg cfg = { 0 }; 574 struct dpu_hw_mdp *hw_mdptop; 575 struct msm_display_info *disp_info; 576 577 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 578 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 579 return; 580 } 581 582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 583 hw_mdptop = phys_enc->hw_mdptop; 584 disp_info = &dpu_enc->disp_info; 585 586 if (disp_info->intf_type != INTF_DSI) 587 return; 588 589 /** 590 * disable split modes since encoder will be operating in as the only 591 * encoder, either for the entire use case in the case of, for example, 592 * single DSI, or for this frame in the case of left/right only partial 593 * update. 594 */ 595 if (phys_enc->split_role == ENC_ROLE_SOLO) { 596 if (hw_mdptop->ops.setup_split_pipe) 597 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 598 return; 599 } 600 601 cfg.en = true; 602 cfg.mode = phys_enc->intf_mode; 603 cfg.intf = interface; 604 605 if (cfg.en && phys_enc->ops.needs_single_flush && 606 phys_enc->ops.needs_single_flush(phys_enc)) 607 cfg.split_flush_en = true; 608 609 if (phys_enc->split_role == ENC_ROLE_MASTER) { 610 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 611 612 if (hw_mdptop->ops.setup_split_pipe) 613 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 614 } 615 } 616 617 /** 618 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 619 * @drm_enc: Pointer to previously created drm encoder structure 620 */ 621 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 622 { 623 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 624 int i, intf_count = 0, num_dsc = 0; 625 626 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 627 if (dpu_enc->phys_encs[i]) 628 intf_count++; 629 630 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 631 if (dpu_enc->hw_dsc[i]) 632 num_dsc++; 633 634 return (num_dsc > 0) && (num_dsc > intf_count); 635 } 636 637 /** 638 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 639 * This helper function is used by physical encoder to get DSC config 640 * used for this encoder. 641 * @drm_enc: Pointer to encoder structure 642 */ 643 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 644 { 645 struct msm_drm_private *priv = drm_enc->dev->dev_private; 646 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 647 int index = dpu_enc->disp_info.h_tile_instance[0]; 648 649 if (dpu_enc->disp_info.intf_type == INTF_DSI) 650 return msm_dsi_get_dsc_config(priv->dsi[index]); 651 652 return NULL; 653 } 654 655 void dpu_encoder_update_topology(struct drm_encoder *drm_enc, 656 struct msm_display_topology *topology, 657 struct drm_atomic_state *state, 658 const struct drm_display_mode *adj_mode) 659 { 660 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 661 struct msm_drm_private *priv = dpu_enc->base.dev->dev_private; 662 struct msm_display_info *disp_info = &dpu_enc->disp_info; 663 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 664 struct drm_connector *connector; 665 struct drm_connector_state *conn_state; 666 struct drm_framebuffer *fb; 667 struct drm_dsc_config *dsc; 668 669 int i; 670 671 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 672 if (dpu_enc->phys_encs[i]) 673 topology->num_intf++; 674 675 dsc = dpu_encoder_get_dsc_config(drm_enc); 676 677 /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ 678 if (dsc) { 679 /* 680 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces 681 * when Display Stream Compression (DSC) is enabled, 682 * and when enough DSC blocks are available. 683 * This is power-optimal and can drive up to (including) 4k 684 * screens. 685 */ 686 WARN(topology->num_intf > 2, 687 "DSC topology cannot support more than 2 interfaces\n"); 688 if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2) 689 topology->num_dsc = 2; 690 else 691 topology->num_dsc = 1; 692 } 693 694 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 695 if (!connector) 696 return; 697 conn_state = drm_atomic_get_new_connector_state(state, connector); 698 if (!conn_state) 699 return; 700 701 /* 702 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. 703 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() 704 * earlier. 705 */ 706 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { 707 fb = conn_state->writeback_job->fb; 708 709 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) 710 topology->num_cdm++; 711 } else if (disp_info->intf_type == INTF_DP) { 712 if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) 713 topology->num_cdm++; 714 } 715 } 716 717 bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state) 718 { 719 struct drm_connector *connector; 720 struct drm_connector_state *conn_state; 721 struct drm_framebuffer *fb; 722 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 723 724 if (!drm_enc || !state) 725 return false; 726 727 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 728 if (!connector) 729 return false; 730 731 conn_state = drm_atomic_get_new_connector_state(state, connector); 732 733 /** 734 * These checks are duplicated from dpu_encoder_update_topology() since 735 * CRTC and encoder don't hold topology information 736 */ 737 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 738 fb = conn_state->writeback_job->fb; 739 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) { 740 if (!dpu_enc->cur_master->hw_cdm) 741 return true; 742 } else { 743 if (dpu_enc->cur_master->hw_cdm) 744 return true; 745 } 746 } 747 748 return false; 749 } 750 751 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 752 struct msm_display_info *disp_info) 753 { 754 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 755 struct msm_drm_private *priv; 756 struct dpu_kms *dpu_kms; 757 struct dpu_hw_mdp *hw_mdptop; 758 struct drm_encoder *drm_enc; 759 struct dpu_encoder_phys *phys_enc; 760 int i; 761 762 if (!dpu_enc || !disp_info) { 763 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 764 dpu_enc != NULL, disp_info != NULL); 765 return; 766 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 767 DPU_ERROR("invalid num phys enc %d/%d\n", 768 dpu_enc->num_phys_encs, 769 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 770 return; 771 } 772 773 drm_enc = &dpu_enc->base; 774 /* this pointers are checked in virt_enable_helper */ 775 priv = drm_enc->dev->dev_private; 776 777 dpu_kms = to_dpu_kms(priv->kms); 778 hw_mdptop = dpu_kms->hw_mdp; 779 if (!hw_mdptop) { 780 DPU_ERROR("invalid mdptop\n"); 781 return; 782 } 783 784 if (hw_mdptop->ops.setup_vsync_source) { 785 for (i = 0; i < dpu_enc->num_phys_encs; i++) 786 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 787 788 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 789 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 790 791 vsync_cfg.vsync_source = disp_info->vsync_source; 792 793 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 794 795 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 796 phys_enc = dpu_enc->phys_encs[i]; 797 798 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 799 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 800 vsync_cfg.vsync_source); 801 } 802 } 803 } 804 805 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) 806 { 807 struct dpu_encoder_virt *dpu_enc; 808 int i; 809 810 if (!drm_enc) { 811 DPU_ERROR("invalid encoder\n"); 812 return; 813 } 814 815 dpu_enc = to_dpu_encoder_virt(drm_enc); 816 817 DPU_DEBUG_ENC(dpu_enc, "\n"); 818 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 819 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 820 821 phys->ops.irq_enable(phys); 822 } 823 } 824 825 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) 826 { 827 struct dpu_encoder_virt *dpu_enc; 828 int i; 829 830 if (!drm_enc) { 831 DPU_ERROR("invalid encoder\n"); 832 return; 833 } 834 835 dpu_enc = to_dpu_encoder_virt(drm_enc); 836 837 DPU_DEBUG_ENC(dpu_enc, "\n"); 838 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 839 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 840 841 phys->ops.irq_disable(phys); 842 } 843 } 844 845 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc) 846 { 847 struct msm_drm_private *priv; 848 struct dpu_kms *dpu_kms; 849 struct dpu_encoder_virt *dpu_enc; 850 851 dpu_enc = to_dpu_encoder_virt(drm_enc); 852 priv = drm_enc->dev->dev_private; 853 dpu_kms = to_dpu_kms(priv->kms); 854 855 trace_dpu_enc_rc_enable(DRMID(drm_enc)); 856 857 if (!dpu_enc->cur_master) { 858 DPU_ERROR("encoder master not set\n"); 859 return; 860 } 861 862 /* enable DPU core clks */ 863 pm_runtime_get_sync(&dpu_kms->pdev->dev); 864 865 /* enable all the irq */ 866 _dpu_encoder_irq_enable(drm_enc); 867 } 868 869 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc) 870 { 871 struct msm_drm_private *priv; 872 struct dpu_kms *dpu_kms; 873 struct dpu_encoder_virt *dpu_enc; 874 875 dpu_enc = to_dpu_encoder_virt(drm_enc); 876 priv = drm_enc->dev->dev_private; 877 dpu_kms = to_dpu_kms(priv->kms); 878 879 trace_dpu_enc_rc_disable(DRMID(drm_enc)); 880 881 if (!dpu_enc->cur_master) { 882 DPU_ERROR("encoder master not set\n"); 883 return; 884 } 885 886 /* disable all the irq */ 887 _dpu_encoder_irq_disable(drm_enc); 888 889 /* disable DPU core clks */ 890 pm_runtime_put_sync(&dpu_kms->pdev->dev); 891 } 892 893 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 894 u32 sw_event) 895 { 896 struct dpu_encoder_virt *dpu_enc; 897 struct msm_drm_private *priv; 898 bool is_vid_mode = false; 899 900 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 901 DPU_ERROR("invalid parameters\n"); 902 return -EINVAL; 903 } 904 dpu_enc = to_dpu_encoder_virt(drm_enc); 905 priv = drm_enc->dev->dev_private; 906 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 907 908 /* 909 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 910 * events and return early for other events (ie wb display). 911 */ 912 if (!dpu_enc->idle_pc_supported && 913 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 914 sw_event != DPU_ENC_RC_EVENT_STOP && 915 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 916 return 0; 917 918 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 919 dpu_enc->rc_state, "begin"); 920 921 switch (sw_event) { 922 case DPU_ENC_RC_EVENT_KICKOFF: 923 /* cancel delayed off work, if any */ 924 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 925 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 926 sw_event); 927 928 mutex_lock(&dpu_enc->rc_lock); 929 930 /* return if the resource control is already in ON state */ 931 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 932 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 933 DRMID(drm_enc), sw_event); 934 mutex_unlock(&dpu_enc->rc_lock); 935 return 0; 936 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 937 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 938 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 939 DRMID(drm_enc), sw_event, 940 dpu_enc->rc_state); 941 mutex_unlock(&dpu_enc->rc_lock); 942 return -EINVAL; 943 } 944 945 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 946 _dpu_encoder_irq_enable(drm_enc); 947 else 948 _dpu_encoder_resource_enable(drm_enc); 949 950 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 951 952 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 953 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 954 "kickoff"); 955 956 mutex_unlock(&dpu_enc->rc_lock); 957 break; 958 959 case DPU_ENC_RC_EVENT_FRAME_DONE: 960 /* 961 * mutex lock is not used as this event happens at interrupt 962 * context. And locking is not required as, the other events 963 * like KICKOFF and STOP does a wait-for-idle before executing 964 * the resource_control 965 */ 966 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 967 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 968 DRMID(drm_enc), sw_event, 969 dpu_enc->rc_state); 970 return -EINVAL; 971 } 972 973 /* 974 * schedule off work item only when there are no 975 * frames pending 976 */ 977 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 978 DRM_DEBUG_KMS("id:%d skip schedule work\n", 979 DRMID(drm_enc)); 980 return 0; 981 } 982 983 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 984 msecs_to_jiffies(dpu_enc->idle_timeout)); 985 986 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 987 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 988 "frame done"); 989 break; 990 991 case DPU_ENC_RC_EVENT_PRE_STOP: 992 /* cancel delayed off work, if any */ 993 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 994 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 995 sw_event); 996 997 mutex_lock(&dpu_enc->rc_lock); 998 999 if (is_vid_mode && 1000 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 1001 _dpu_encoder_irq_enable(drm_enc); 1002 } 1003 /* skip if is already OFF or IDLE, resources are off already */ 1004 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 1005 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 1006 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 1007 DRMID(drm_enc), sw_event, 1008 dpu_enc->rc_state); 1009 mutex_unlock(&dpu_enc->rc_lock); 1010 return 0; 1011 } 1012 1013 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 1014 1015 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1016 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1017 "pre stop"); 1018 1019 mutex_unlock(&dpu_enc->rc_lock); 1020 break; 1021 1022 case DPU_ENC_RC_EVENT_STOP: 1023 mutex_lock(&dpu_enc->rc_lock); 1024 1025 /* return if the resource control is already in OFF state */ 1026 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 1027 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 1028 DRMID(drm_enc), sw_event); 1029 mutex_unlock(&dpu_enc->rc_lock); 1030 return 0; 1031 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 1032 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 1033 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1034 mutex_unlock(&dpu_enc->rc_lock); 1035 return -EINVAL; 1036 } 1037 1038 /** 1039 * expect to arrive here only if in either idle state or pre-off 1040 * and in IDLE state the resources are already disabled 1041 */ 1042 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 1043 _dpu_encoder_resource_disable(drm_enc); 1044 1045 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 1046 1047 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1048 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1049 "stop"); 1050 1051 mutex_unlock(&dpu_enc->rc_lock); 1052 break; 1053 1054 case DPU_ENC_RC_EVENT_ENTER_IDLE: 1055 mutex_lock(&dpu_enc->rc_lock); 1056 1057 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 1058 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 1059 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1060 mutex_unlock(&dpu_enc->rc_lock); 1061 return 0; 1062 } 1063 1064 /* 1065 * if we are in ON but a frame was just kicked off, 1066 * ignore the IDLE event, it's probably a stale timer event 1067 */ 1068 if (dpu_enc->frame_busy_mask[0]) { 1069 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 1070 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1071 mutex_unlock(&dpu_enc->rc_lock); 1072 return 0; 1073 } 1074 1075 if (is_vid_mode) 1076 _dpu_encoder_irq_disable(drm_enc); 1077 else 1078 _dpu_encoder_resource_disable(drm_enc); 1079 1080 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 1081 1082 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1083 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1084 "idle"); 1085 1086 mutex_unlock(&dpu_enc->rc_lock); 1087 break; 1088 1089 default: 1090 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 1091 sw_event); 1092 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1093 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1094 "error"); 1095 break; 1096 } 1097 1098 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1099 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1100 "end"); 1101 return 0; 1102 } 1103 1104 /** 1105 * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 1106 * @drm_enc: Pointer to previously created drm encoder structure 1107 * @job: Pointer to the current drm writeback job 1108 */ 1109 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1110 struct drm_writeback_job *job) 1111 { 1112 struct dpu_encoder_virt *dpu_enc; 1113 int i; 1114 1115 dpu_enc = to_dpu_encoder_virt(drm_enc); 1116 1117 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1118 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1119 1120 if (phys->ops.prepare_wb_job) 1121 phys->ops.prepare_wb_job(phys, job); 1122 1123 } 1124 } 1125 1126 /** 1127 * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 1128 * @drm_enc: Pointer to previously created drm encoder structure 1129 * @job: Pointer to the current drm writeback job 1130 */ 1131 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1132 struct drm_writeback_job *job) 1133 { 1134 struct dpu_encoder_virt *dpu_enc; 1135 int i; 1136 1137 dpu_enc = to_dpu_encoder_virt(drm_enc); 1138 1139 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1140 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1141 1142 if (phys->ops.cleanup_wb_job) 1143 phys->ops.cleanup_wb_job(phys, job); 1144 1145 } 1146 } 1147 1148 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1149 struct drm_crtc_state *crtc_state, 1150 struct drm_connector_state *conn_state) 1151 { 1152 struct dpu_encoder_virt *dpu_enc; 1153 struct msm_drm_private *priv; 1154 struct dpu_kms *dpu_kms; 1155 struct dpu_global_state *global_state; 1156 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1157 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1158 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1159 struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC]; 1160 int num_ctl, num_pp, num_dsc; 1161 int num_cwb = 0; 1162 bool is_cwb_encoder; 1163 unsigned int dsc_mask = 0; 1164 unsigned int cwb_mask = 0; 1165 int i; 1166 1167 if (!drm_enc) { 1168 DPU_ERROR("invalid encoder\n"); 1169 return; 1170 } 1171 1172 dpu_enc = to_dpu_encoder_virt(drm_enc); 1173 DPU_DEBUG_ENC(dpu_enc, "\n"); 1174 1175 priv = drm_enc->dev->dev_private; 1176 dpu_kms = to_dpu_kms(priv->kms); 1177 is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) && 1178 dpu_enc->disp_info.intf_type == INTF_WB; 1179 1180 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1181 if (IS_ERR_OR_NULL(global_state)) { 1182 DPU_ERROR("Failed to get global state"); 1183 return; 1184 } 1185 1186 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1187 1188 /* Query resource that have been reserved in atomic check step. */ 1189 if (is_cwb_encoder) { 1190 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1191 drm_enc->crtc, 1192 DPU_HW_BLK_DCWB_PINGPONG, 1193 hw_pp, ARRAY_SIZE(hw_pp)); 1194 num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1195 drm_enc->crtc, 1196 DPU_HW_BLK_CWB, 1197 hw_cwb, ARRAY_SIZE(hw_cwb)); 1198 } else { 1199 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1200 drm_enc->crtc, 1201 DPU_HW_BLK_PINGPONG, hw_pp, 1202 ARRAY_SIZE(hw_pp)); 1203 } 1204 1205 for (i = 0; i < num_cwb; i++) { 1206 dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]); 1207 cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); 1208 } 1209 1210 dpu_enc->cwb_mask = cwb_mask; 1211 1212 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1213 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1214 1215 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1216 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1217 : NULL; 1218 1219 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1220 drm_enc->crtc, DPU_HW_BLK_DSC, 1221 hw_dsc, ARRAY_SIZE(hw_dsc)); 1222 for (i = 0; i < num_dsc; i++) { 1223 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1224 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1225 } 1226 1227 dpu_enc->dsc_mask = dsc_mask; 1228 1229 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || 1230 dpu_enc->disp_info.intf_type == INTF_DP) { 1231 struct dpu_hw_blk *hw_cdm = NULL; 1232 1233 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1234 drm_enc->crtc, DPU_HW_BLK_CDM, 1235 &hw_cdm, 1); 1236 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1237 } 1238 1239 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1240 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1241 1242 phys->hw_pp = dpu_enc->hw_pp[i]; 1243 if (!phys->hw_pp) { 1244 DPU_ERROR_ENC(dpu_enc, 1245 "no pp block assigned at idx: %d\n", i); 1246 return; 1247 } 1248 1249 /* Use first (and only) CTL if active CTLs are supported */ 1250 if (num_ctl == 1) 1251 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]); 1252 else 1253 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; 1254 if (!phys->hw_ctl) { 1255 DPU_ERROR_ENC(dpu_enc, 1256 "no ctl block assigned at idx: %d\n", i); 1257 return; 1258 } 1259 1260 phys->cached_mode = crtc_state->adjusted_mode; 1261 if (phys->ops.atomic_mode_set) 1262 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1263 } 1264 } 1265 1266 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1267 { 1268 struct dpu_encoder_virt *dpu_enc = NULL; 1269 int i; 1270 1271 if (!drm_enc || !drm_enc->dev) { 1272 DPU_ERROR("invalid parameters\n"); 1273 return; 1274 } 1275 1276 dpu_enc = to_dpu_encoder_virt(drm_enc); 1277 if (!dpu_enc || !dpu_enc->cur_master) { 1278 DPU_ERROR("invalid dpu encoder/master\n"); 1279 return; 1280 } 1281 1282 1283 if (dpu_enc->disp_info.intf_type == INTF_DP && 1284 dpu_enc->cur_master->hw_mdptop && 1285 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1286 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1287 dpu_enc->cur_master->hw_mdptop); 1288 1289 if (dpu_enc->disp_info.is_cmd_mode) 1290 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1291 1292 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1293 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1294 unsigned bpc = dpu_enc->connector->display_info.bpc; 1295 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1296 if (!dpu_enc->hw_pp[i]) 1297 continue; 1298 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1299 } 1300 } 1301 } 1302 1303 /** 1304 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 1305 * @drm_enc: encoder pointer 1306 */ 1307 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1308 { 1309 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1310 1311 mutex_lock(&dpu_enc->enc_lock); 1312 1313 if (!dpu_enc->enabled) 1314 goto out; 1315 1316 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1317 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1318 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1319 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1320 1321 _dpu_encoder_virt_enable_helper(drm_enc); 1322 1323 out: 1324 mutex_unlock(&dpu_enc->enc_lock); 1325 } 1326 1327 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1328 struct drm_atomic_state *state) 1329 { 1330 struct dpu_encoder_virt *dpu_enc = NULL; 1331 int ret = 0; 1332 struct drm_display_mode *cur_mode = NULL; 1333 1334 dpu_enc = to_dpu_encoder_virt(drm_enc); 1335 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1336 1337 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 1338 1339 mutex_lock(&dpu_enc->enc_lock); 1340 1341 dpu_enc->commit_done_timedout = false; 1342 1343 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 1344 1345 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1346 1347 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc); 1348 1349 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1350 cur_mode->vdisplay); 1351 1352 /* always enable slave encoder before master */ 1353 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1354 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1355 1356 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1357 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1358 1359 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1360 if (ret) { 1361 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1362 ret); 1363 goto out; 1364 } 1365 1366 _dpu_encoder_virt_enable_helper(drm_enc); 1367 1368 dpu_enc->enabled = true; 1369 1370 out: 1371 mutex_unlock(&dpu_enc->enc_lock); 1372 } 1373 1374 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1375 struct drm_atomic_state *state) 1376 { 1377 struct dpu_encoder_virt *dpu_enc = NULL; 1378 struct drm_crtc *crtc; 1379 struct drm_crtc_state *old_state = NULL; 1380 int i = 0; 1381 1382 dpu_enc = to_dpu_encoder_virt(drm_enc); 1383 DPU_DEBUG_ENC(dpu_enc, "\n"); 1384 1385 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1386 if (crtc) 1387 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1388 1389 /* 1390 * The encoder is already disabled if self refresh mode was set earlier, 1391 * in the old_state for the corresponding crtc. 1392 */ 1393 if (old_state && old_state->self_refresh_active) 1394 return; 1395 1396 mutex_lock(&dpu_enc->enc_lock); 1397 dpu_enc->enabled = false; 1398 1399 trace_dpu_enc_disable(DRMID(drm_enc)); 1400 1401 /* wait for idle */ 1402 dpu_encoder_wait_for_tx_complete(drm_enc); 1403 1404 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1405 1406 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1407 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1408 1409 if (phys->ops.disable) 1410 phys->ops.disable(phys); 1411 } 1412 1413 1414 /* after phys waits for frame-done, should be no more frames pending */ 1415 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1416 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1417 timer_delete_sync(&dpu_enc->frame_done_timer); 1418 } 1419 1420 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1421 1422 dpu_enc->connector = NULL; 1423 1424 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1425 1426 mutex_unlock(&dpu_enc->enc_lock); 1427 } 1428 1429 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1430 struct dpu_rm *dpu_rm, 1431 enum dpu_intf_type type, u32 controller_id) 1432 { 1433 int i = 0; 1434 1435 if (type == INTF_WB) 1436 return NULL; 1437 1438 for (i = 0; i < catalog->intf_count; i++) { 1439 if (catalog->intf[i].type == type 1440 && catalog->intf[i].controller_id == controller_id) { 1441 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1442 } 1443 } 1444 1445 return NULL; 1446 } 1447 1448 /** 1449 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 1450 * @drm_enc: Pointer to drm encoder structure 1451 * @phy_enc: Pointer to physical encoder 1452 * Note: This is called from IRQ handler context. 1453 */ 1454 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1455 struct dpu_encoder_phys *phy_enc) 1456 { 1457 struct dpu_encoder_virt *dpu_enc = NULL; 1458 unsigned long lock_flags; 1459 1460 if (!drm_enc || !phy_enc) 1461 return; 1462 1463 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1464 dpu_enc = to_dpu_encoder_virt(drm_enc); 1465 1466 atomic_inc(&phy_enc->vsync_cnt); 1467 1468 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1469 if (dpu_enc->crtc) 1470 dpu_crtc_vblank_callback(dpu_enc->crtc); 1471 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1472 1473 DPU_ATRACE_END("encoder_vblank_callback"); 1474 } 1475 1476 /** 1477 * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 1478 * @drm_enc: Pointer to drm encoder structure 1479 * @phy_enc: Pointer to physical encoder 1480 * Note: This is called from IRQ handler context. 1481 */ 1482 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1483 struct dpu_encoder_phys *phy_enc) 1484 { 1485 if (!phy_enc) 1486 return; 1487 1488 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1489 atomic_inc(&phy_enc->underrun_cnt); 1490 1491 /* trigger dump only on the first underrun */ 1492 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1493 msm_disp_snapshot_state(drm_enc->dev); 1494 1495 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1496 atomic_read(&phy_enc->underrun_cnt)); 1497 DPU_ATRACE_END("encoder_underrun_callback"); 1498 } 1499 1500 /** 1501 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 1502 * @drm_enc: encoder pointer 1503 * @crtc: crtc pointer 1504 */ 1505 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1506 { 1507 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1508 unsigned long lock_flags; 1509 1510 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1511 /* crtc should always be cleared before re-assigning */ 1512 WARN_ON(crtc && dpu_enc->crtc); 1513 dpu_enc->crtc = crtc; 1514 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1515 } 1516 1517 /** 1518 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 1519 * the encoder is assigned to the given crtc 1520 * @drm_enc: encoder pointer 1521 * @crtc: crtc pointer 1522 * @enable: true if vblank should be enabled 1523 */ 1524 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1525 struct drm_crtc *crtc, bool enable) 1526 { 1527 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1528 unsigned long lock_flags; 1529 int i; 1530 1531 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1532 1533 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1534 if (dpu_enc->crtc != crtc) { 1535 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1536 return; 1537 } 1538 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1539 1540 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1541 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1542 1543 if (phys->ops.control_vblank_irq) 1544 phys->ops.control_vblank_irq(phys, enable); 1545 } 1546 } 1547 1548 /** 1549 * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys 1550 * encoder completes last request frame 1551 * @drm_enc: Pointer to drm encoder structure 1552 * @ready_phys: Pointer to physical encoder 1553 * @event: Event to process 1554 */ 1555 void dpu_encoder_frame_done_callback( 1556 struct drm_encoder *drm_enc, 1557 struct dpu_encoder_phys *ready_phys, u32 event) 1558 { 1559 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1560 unsigned int i; 1561 1562 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1563 | DPU_ENCODER_FRAME_EVENT_ERROR 1564 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1565 1566 if (!dpu_enc->frame_busy_mask[0]) { 1567 /** 1568 * suppress frame_done without waiter, 1569 * likely autorefresh 1570 */ 1571 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1572 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1573 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1574 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1575 return; 1576 } 1577 1578 /* One of the physical encoders has become idle */ 1579 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1580 if (dpu_enc->phys_encs[i] == ready_phys) { 1581 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1582 dpu_enc->frame_busy_mask[0]); 1583 clear_bit(i, dpu_enc->frame_busy_mask); 1584 } 1585 } 1586 1587 if (!dpu_enc->frame_busy_mask[0]) { 1588 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1589 timer_delete(&dpu_enc->frame_done_timer); 1590 1591 dpu_encoder_resource_control(drm_enc, 1592 DPU_ENC_RC_EVENT_FRAME_DONE); 1593 1594 if (dpu_enc->crtc) 1595 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1596 } 1597 } else { 1598 if (dpu_enc->crtc) 1599 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1600 } 1601 } 1602 1603 static void dpu_encoder_off_work(struct work_struct *work) 1604 { 1605 struct dpu_encoder_virt *dpu_enc = container_of(work, 1606 struct dpu_encoder_virt, delayed_off_work.work); 1607 1608 dpu_encoder_resource_control(&dpu_enc->base, 1609 DPU_ENC_RC_EVENT_ENTER_IDLE); 1610 1611 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1612 DPU_ENCODER_FRAME_EVENT_IDLE); 1613 } 1614 1615 /** 1616 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1617 * @drm_enc: Pointer to drm encoder structure 1618 * @phys: Pointer to physical encoder structure 1619 * @extra_flush_bits: Additional bit mask to include in flush trigger 1620 */ 1621 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1622 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1623 { 1624 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1625 struct dpu_hw_ctl *ctl; 1626 int pending_kickoff_cnt; 1627 u32 ret = UINT_MAX; 1628 1629 if (!phys->hw_pp) { 1630 DPU_ERROR("invalid pingpong hw\n"); 1631 return; 1632 } 1633 1634 ctl = phys->hw_ctl; 1635 if (!ctl->ops.trigger_flush) { 1636 DPU_ERROR("missing trigger cb\n"); 1637 return; 1638 } 1639 1640 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1641 1642 /* Return early if encoder is writeback and in clone mode */ 1643 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL && 1644 dpu_enc->cwb_mask) { 1645 DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n", 1646 DRMID(drm_enc)); 1647 return; 1648 } 1649 1650 1651 if (extra_flush_bits && ctl->ops.update_pending_flush) 1652 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1653 1654 ctl->ops.trigger_flush(ctl); 1655 1656 if (ctl->ops.get_pending_flush) 1657 ret = ctl->ops.get_pending_flush(ctl); 1658 1659 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1660 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1661 phys->hw_intf ? phys->hw_intf->idx : -1, 1662 phys->hw_wb ? phys->hw_wb->idx : -1, 1663 pending_kickoff_cnt, ctl->idx, 1664 extra_flush_bits, ret); 1665 } 1666 1667 /** 1668 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1669 * @phys: Pointer to physical encoder structure 1670 */ 1671 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1672 { 1673 struct dpu_encoder_virt *dpu_enc; 1674 1675 if (!phys) { 1676 DPU_ERROR("invalid argument(s)\n"); 1677 return; 1678 } 1679 1680 if (!phys->hw_pp) { 1681 DPU_ERROR("invalid pingpong hw\n"); 1682 return; 1683 } 1684 1685 dpu_enc = to_dpu_encoder_virt(phys->parent); 1686 1687 if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL && 1688 dpu_enc->cwb_mask) { 1689 DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent)); 1690 return; 1691 } 1692 1693 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1694 phys->ops.trigger_start(phys); 1695 } 1696 1697 /** 1698 * dpu_encoder_helper_trigger_start - control start helper function 1699 * This helper function may be optionally specified by physical 1700 * encoders if they require ctl_start triggering. 1701 * @phys_enc: Pointer to physical encoder structure 1702 */ 1703 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1704 { 1705 struct dpu_hw_ctl *ctl; 1706 1707 ctl = phys_enc->hw_ctl; 1708 if (ctl->ops.trigger_start) { 1709 ctl->ops.trigger_start(ctl); 1710 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1711 } 1712 } 1713 1714 static int dpu_encoder_helper_wait_event_timeout( 1715 int32_t drm_id, 1716 unsigned int irq_idx, 1717 struct dpu_encoder_wait_info *info) 1718 { 1719 int rc = 0; 1720 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1721 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1722 s64 time; 1723 1724 do { 1725 rc = wait_event_timeout(*(info->wq), 1726 atomic_read(info->atomic_cnt) == 0, jiffies); 1727 time = ktime_to_ms(ktime_get()); 1728 1729 trace_dpu_enc_wait_event_timeout(drm_id, 1730 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1731 rc, time, 1732 expected_time, 1733 atomic_read(info->atomic_cnt)); 1734 /* If we timed out, counter is valid and time is less, wait again */ 1735 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1736 (time < expected_time)); 1737 1738 return rc; 1739 } 1740 1741 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1742 { 1743 struct dpu_encoder_virt *dpu_enc; 1744 struct dpu_hw_ctl *ctl; 1745 int rc; 1746 struct drm_encoder *drm_enc; 1747 1748 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1749 ctl = phys_enc->hw_ctl; 1750 drm_enc = phys_enc->parent; 1751 1752 if (!ctl->ops.reset) 1753 return; 1754 1755 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1756 ctl->idx); 1757 1758 rc = ctl->ops.reset(ctl); 1759 if (rc) { 1760 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1761 msm_disp_snapshot_state(drm_enc->dev); 1762 } 1763 1764 phys_enc->enable_state = DPU_ENC_ENABLED; 1765 } 1766 1767 /** 1768 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1769 * Iterate through the physical encoders and perform consolidated flush 1770 * and/or control start triggering as needed. This is done in the virtual 1771 * encoder rather than the individual physical ones in order to handle 1772 * use cases that require visibility into multiple physical encoders at 1773 * a time. 1774 * @dpu_enc: Pointer to virtual encoder structure 1775 */ 1776 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1777 { 1778 struct dpu_hw_ctl *ctl; 1779 uint32_t i, pending_flush; 1780 unsigned long lock_flags; 1781 1782 pending_flush = 0x0; 1783 1784 /* update pending counts and trigger kickoff ctl flush atomically */ 1785 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1786 1787 /* don't perform flush/start operations for slave encoders */ 1788 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1789 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1790 1791 if (phys->enable_state == DPU_ENC_DISABLED) 1792 continue; 1793 1794 ctl = phys->hw_ctl; 1795 1796 /* 1797 * This is cleared in frame_done worker, which isn't invoked 1798 * for async commits. So don't set this for async, since it'll 1799 * roll over to the next commit. 1800 */ 1801 if (phys->split_role != ENC_ROLE_SLAVE) 1802 set_bit(i, dpu_enc->frame_busy_mask); 1803 1804 if (!phys->ops.needs_single_flush || 1805 !phys->ops.needs_single_flush(phys)) 1806 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1807 else if (ctl->ops.get_pending_flush) 1808 pending_flush |= ctl->ops.get_pending_flush(ctl); 1809 } 1810 1811 /* for split flush, combine pending flush masks and send to master */ 1812 if (pending_flush && dpu_enc->cur_master) { 1813 _dpu_encoder_trigger_flush( 1814 &dpu_enc->base, 1815 dpu_enc->cur_master, 1816 pending_flush); 1817 } 1818 1819 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1820 1821 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1822 } 1823 1824 /** 1825 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 1826 * kickoff and trigger the ctl prepare progress for command mode display. 1827 * @drm_enc: encoder pointer 1828 */ 1829 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1830 { 1831 struct dpu_encoder_virt *dpu_enc; 1832 struct dpu_encoder_phys *phys; 1833 unsigned int i; 1834 struct dpu_hw_ctl *ctl; 1835 struct msm_display_info *disp_info; 1836 1837 if (!drm_enc) { 1838 DPU_ERROR("invalid encoder\n"); 1839 return; 1840 } 1841 dpu_enc = to_dpu_encoder_virt(drm_enc); 1842 disp_info = &dpu_enc->disp_info; 1843 1844 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1845 phys = dpu_enc->phys_encs[i]; 1846 1847 ctl = phys->hw_ctl; 1848 ctl->ops.clear_pending_flush(ctl); 1849 1850 /* update only for command mode primary ctl */ 1851 if ((phys == dpu_enc->cur_master) && 1852 disp_info->is_cmd_mode 1853 && ctl->ops.trigger_pending) 1854 ctl->ops.trigger_pending(ctl); 1855 } 1856 } 1857 1858 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1859 struct drm_display_mode *mode) 1860 { 1861 u64 pclk_rate; 1862 u32 pclk_period; 1863 u32 line_time; 1864 1865 /* 1866 * For linetime calculation, only operate on master encoder. 1867 */ 1868 if (!dpu_enc->cur_master) 1869 return 0; 1870 1871 if (!dpu_enc->cur_master->ops.get_line_count) { 1872 DPU_ERROR("get_line_count function not defined\n"); 1873 return 0; 1874 } 1875 1876 pclk_rate = mode->clock; /* pixel clock in kHz */ 1877 if (pclk_rate == 0) { 1878 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1879 return 0; 1880 } 1881 1882 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1883 if (pclk_period == 0) { 1884 DPU_ERROR("pclk period is 0\n"); 1885 return 0; 1886 } 1887 1888 /* 1889 * Line time calculation based on Pixel clock and HTOTAL. 1890 * Final unit is in ns. 1891 */ 1892 line_time = (pclk_period * mode->htotal) / 1000; 1893 if (line_time == 0) { 1894 DPU_ERROR("line time calculation is 0\n"); 1895 return 0; 1896 } 1897 1898 DPU_DEBUG_ENC(dpu_enc, 1899 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1900 pclk_rate, pclk_period, line_time); 1901 1902 return line_time; 1903 } 1904 1905 /** 1906 * dpu_encoder_vsync_time - get the time of the next vsync 1907 * @drm_enc: encoder pointer 1908 * @wakeup_time: pointer to ktime_t to write the vsync time to 1909 */ 1910 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1911 { 1912 struct drm_display_mode *mode; 1913 struct dpu_encoder_virt *dpu_enc; 1914 u32 cur_line; 1915 u32 line_time; 1916 u32 vtotal, time_to_vsync; 1917 ktime_t cur_time; 1918 1919 dpu_enc = to_dpu_encoder_virt(drm_enc); 1920 1921 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1922 DPU_ERROR("crtc/crtc state object is NULL\n"); 1923 return -EINVAL; 1924 } 1925 mode = &drm_enc->crtc->state->adjusted_mode; 1926 1927 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1928 if (!line_time) 1929 return -EINVAL; 1930 1931 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1932 1933 vtotal = mode->vtotal; 1934 if (cur_line >= vtotal) 1935 time_to_vsync = line_time * vtotal; 1936 else 1937 time_to_vsync = line_time * (vtotal - cur_line); 1938 1939 if (time_to_vsync == 0) { 1940 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1941 vtotal); 1942 return -EINVAL; 1943 } 1944 1945 cur_time = ktime_get(); 1946 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1947 1948 DPU_DEBUG_ENC(dpu_enc, 1949 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1950 cur_line, vtotal, time_to_vsync, 1951 ktime_to_ms(cur_time), 1952 ktime_to_ms(*wakeup_time)); 1953 return 0; 1954 } 1955 1956 static u32 1957 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1958 u32 enc_ip_width) 1959 { 1960 int ssm_delay, total_pixels, soft_slice_per_enc; 1961 1962 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1963 1964 /* 1965 * minimum number of initial line pixels is a sum of: 1966 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1967 * 91 for 10 bpc) * 3 1968 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1969 * 3. the initial xmit delay 1970 * 4. total pipeline delay through the "lock step" of encoder (47) 1971 * 5. 6 additional pixels as the output of the rate buffer is 1972 * 48 bits wide 1973 */ 1974 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1975 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1976 if (soft_slice_per_enc > 1) 1977 total_pixels += (ssm_delay * 3); 1978 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1979 } 1980 1981 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1982 struct dpu_hw_dsc *hw_dsc, 1983 struct dpu_hw_pingpong *hw_pp, 1984 struct drm_dsc_config *dsc, 1985 u32 common_mode, 1986 u32 initial_lines) 1987 { 1988 if (hw_dsc->ops.dsc_config) 1989 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1990 1991 if (hw_dsc->ops.dsc_config_thresh) 1992 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 1993 1994 if (hw_pp->ops.setup_dsc) 1995 hw_pp->ops.setup_dsc(hw_pp); 1996 1997 if (hw_dsc->ops.dsc_bind_pingpong_blk) 1998 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 1999 2000 if (hw_pp->ops.enable_dsc) 2001 hw_pp->ops.enable_dsc(hw_pp); 2002 2003 if (ctl->ops.update_pending_flush_dsc) 2004 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2005 } 2006 2007 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 2008 struct drm_dsc_config *dsc) 2009 { 2010 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2011 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2012 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2013 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2014 int this_frame_slices; 2015 int intf_ip_w, enc_ip_w; 2016 int dsc_common_mode; 2017 int pic_width; 2018 u32 initial_lines; 2019 int num_dsc = 0; 2020 int i; 2021 2022 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2023 hw_pp[i] = dpu_enc->hw_pp[i]; 2024 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2025 2026 if (!hw_pp[i] || !hw_dsc[i]) 2027 break; 2028 2029 num_dsc++; 2030 } 2031 2032 pic_width = dsc->pic_width; 2033 2034 dsc_common_mode = 0; 2035 if (num_dsc > 1) 2036 dsc_common_mode |= DSC_MODE_SPLIT_PANEL; 2037 if (dpu_encoder_use_dsc_merge(enc_master->parent)) 2038 dsc_common_mode |= DSC_MODE_MULTIPLEX; 2039 if (enc_master->intf_mode == INTF_MODE_VIDEO) 2040 dsc_common_mode |= DSC_MODE_VIDEO; 2041 2042 this_frame_slices = pic_width / dsc->slice_width; 2043 intf_ip_w = this_frame_slices * dsc->slice_width; 2044 2045 enc_ip_w = intf_ip_w / num_dsc; 2046 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 2047 2048 for (i = 0; i < num_dsc; i++) 2049 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 2050 dsc, dsc_common_mode, initial_lines); 2051 } 2052 2053 /** 2054 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 2055 * path (i.e. ctl flush and start) at next appropriate time. 2056 * Immediately: if no previous commit is outstanding. 2057 * Delayed: Block until next trigger can be issued. 2058 * @drm_enc: encoder pointer 2059 */ 2060 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 2061 { 2062 struct dpu_encoder_virt *dpu_enc; 2063 struct dpu_encoder_phys *phys; 2064 bool needs_hw_reset = false; 2065 unsigned int i; 2066 2067 dpu_enc = to_dpu_encoder_virt(drm_enc); 2068 2069 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 2070 2071 /* prepare for next kickoff, may include waiting on previous kickoff */ 2072 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 2073 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2074 phys = dpu_enc->phys_encs[i]; 2075 if (phys->ops.prepare_for_kickoff) 2076 phys->ops.prepare_for_kickoff(phys); 2077 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 2078 needs_hw_reset = true; 2079 } 2080 DPU_ATRACE_END("enc_prepare_for_kickoff"); 2081 2082 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 2083 2084 /* if any phys needs reset, reset all phys, in-order */ 2085 if (needs_hw_reset) { 2086 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 2087 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2088 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 2089 } 2090 } 2091 2092 if (dpu_enc->dsc) 2093 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 2094 } 2095 2096 /** 2097 * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 2098 * @drm_enc: Pointer to drm encoder structure 2099 */ 2100 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 2101 { 2102 struct dpu_encoder_virt *dpu_enc; 2103 unsigned int i; 2104 struct dpu_encoder_phys *phys; 2105 2106 dpu_enc = to_dpu_encoder_virt(drm_enc); 2107 2108 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 2109 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2110 phys = dpu_enc->phys_encs[i]; 2111 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 2112 DPU_DEBUG("invalid FB not kicking off\n"); 2113 return false; 2114 } 2115 } 2116 } 2117 2118 return true; 2119 } 2120 2121 /** 2122 * dpu_encoder_start_frame_done_timer - Start the encoder frame done timer 2123 * @drm_enc: Pointer to drm encoder structure 2124 */ 2125 void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc) 2126 { 2127 struct dpu_encoder_virt *dpu_enc; 2128 unsigned long timeout_ms; 2129 2130 dpu_enc = to_dpu_encoder_virt(drm_enc); 2131 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 2132 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 2133 2134 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 2135 mod_timer(&dpu_enc->frame_done_timer, 2136 jiffies + msecs_to_jiffies(timeout_ms)); 2137 2138 } 2139 2140 /** 2141 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 2142 * (i.e. ctl flush and start) immediately. 2143 * @drm_enc: encoder pointer 2144 */ 2145 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 2146 { 2147 struct dpu_encoder_virt *dpu_enc; 2148 struct dpu_encoder_phys *phys; 2149 unsigned int i; 2150 2151 DPU_ATRACE_BEGIN("encoder_kickoff"); 2152 dpu_enc = to_dpu_encoder_virt(drm_enc); 2153 2154 trace_dpu_enc_kickoff(DRMID(drm_enc)); 2155 2156 /* All phys encs are ready to go, trigger the kickoff */ 2157 _dpu_encoder_kickoff_phys(dpu_enc); 2158 2159 /* allow phys encs to handle any post-kickoff business */ 2160 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2161 phys = dpu_enc->phys_encs[i]; 2162 if (phys->ops.handle_post_kickoff) 2163 phys->ops.handle_post_kickoff(phys); 2164 } 2165 2166 DPU_ATRACE_END("encoder_kickoff"); 2167 } 2168 2169 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 2170 { 2171 struct dpu_hw_mixer_cfg mixer; 2172 int i, num_lm; 2173 struct dpu_global_state *global_state; 2174 struct dpu_hw_blk *hw_lm[2]; 2175 struct dpu_hw_mixer *hw_mixer[2]; 2176 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2177 2178 memset(&mixer, 0, sizeof(mixer)); 2179 2180 /* reset all mixers for this encoder */ 2181 if (ctl->ops.clear_all_blendstages) 2182 ctl->ops.clear_all_blendstages(ctl); 2183 2184 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 2185 2186 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 2187 phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 2188 2189 for (i = 0; i < num_lm; i++) { 2190 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 2191 if (ctl->ops.update_pending_flush_mixer) 2192 ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 2193 2194 /* clear all blendstages */ 2195 if (ctl->ops.setup_blendstage) 2196 ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 2197 2198 if (ctl->ops.set_active_fetch_pipes) 2199 ctl->ops.set_active_fetch_pipes(ctl, NULL); 2200 } 2201 } 2202 2203 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 2204 struct dpu_hw_dsc *hw_dsc, 2205 struct dpu_hw_pingpong *hw_pp) 2206 { 2207 if (hw_dsc->ops.dsc_disable) 2208 hw_dsc->ops.dsc_disable(hw_dsc); 2209 2210 if (hw_pp->ops.disable_dsc) 2211 hw_pp->ops.disable_dsc(hw_pp); 2212 2213 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2214 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2215 2216 if (ctl->ops.update_pending_flush_dsc) 2217 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2218 } 2219 2220 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2221 { 2222 /* coding only for 2LM, 2enc, 1 dsc config */ 2223 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2224 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2225 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2226 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2227 int i; 2228 2229 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2230 hw_pp[i] = dpu_enc->hw_pp[i]; 2231 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2232 2233 if (hw_pp[i] && hw_dsc[i]) 2234 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2235 } 2236 } 2237 2238 /** 2239 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 2240 * @phys_enc: Pointer to physical encoder structure 2241 */ 2242 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2243 { 2244 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2245 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2246 int i; 2247 struct dpu_encoder_virt *dpu_enc; 2248 2249 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2250 2251 ctl->ops.reset(ctl); 2252 2253 dpu_encoder_helper_reset_mixers(phys_enc); 2254 2255 /* 2256 * TODO: move the once-only operation like CTL flush/trigger 2257 * into dpu_encoder_virt_disable() and all operations which need 2258 * to be done per phys encoder into the phys_disable() op. 2259 */ 2260 if (phys_enc->hw_wb) { 2261 /* disable the PP block */ 2262 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2263 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2264 2265 /* mark WB flush as pending */ 2266 if (ctl->ops.update_pending_flush_wb) 2267 ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2268 } else { 2269 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2270 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2271 phys_enc->hw_intf->ops.bind_pingpong_blk( 2272 dpu_enc->phys_encs[i]->hw_intf, 2273 PINGPONG_NONE); 2274 2275 /* mark INTF flush as pending */ 2276 if (ctl->ops.update_pending_flush_intf) 2277 ctl->ops.update_pending_flush_intf(ctl, 2278 dpu_enc->phys_encs[i]->hw_intf->idx); 2279 } 2280 } 2281 2282 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither) 2283 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL); 2284 2285 if (dpu_enc->cwb_mask) 2286 dpu_encoder_helper_phys_setup_cwb(phys_enc, false); 2287 2288 /* reset the merge 3D HW block */ 2289 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { 2290 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2291 BLEND_3D_NONE); 2292 if (ctl->ops.update_pending_flush_merge_3d) 2293 ctl->ops.update_pending_flush_merge_3d(ctl, 2294 phys_enc->hw_pp->merge_3d->idx); 2295 } 2296 2297 if (phys_enc->hw_cdm) { 2298 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) 2299 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, 2300 PINGPONG_NONE); 2301 if (ctl->ops.update_pending_flush_cdm) 2302 ctl->ops.update_pending_flush_cdm(ctl, 2303 phys_enc->hw_cdm->idx); 2304 } 2305 2306 if (dpu_enc->dsc) { 2307 dpu_encoder_unprep_dsc(dpu_enc); 2308 dpu_enc->dsc = NULL; 2309 } 2310 2311 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2312 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2313 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2314 intf_cfg.cwb = dpu_enc->cwb_mask; 2315 2316 if (phys_enc->hw_intf) 2317 intf_cfg.intf = phys_enc->hw_intf->idx; 2318 if (phys_enc->hw_wb) 2319 intf_cfg.wb = phys_enc->hw_wb->idx; 2320 2321 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) 2322 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2323 2324 if (ctl->ops.reset_intf_cfg) 2325 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2326 2327 ctl->ops.trigger_flush(ctl); 2328 ctl->ops.trigger_start(ctl); 2329 ctl->ops.clear_pending_flush(ctl); 2330 } 2331 2332 void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc, 2333 bool enable) 2334 { 2335 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2336 struct dpu_hw_cwb *hw_cwb; 2337 struct dpu_hw_ctl *hw_ctl; 2338 struct dpu_hw_cwb_setup_cfg cwb_cfg; 2339 2340 struct dpu_kms *dpu_kms; 2341 struct dpu_global_state *global_state; 2342 struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC]; 2343 int num_pp; 2344 2345 if (!phys_enc->hw_wb) 2346 return; 2347 2348 hw_ctl = phys_enc->hw_ctl; 2349 2350 if (!phys_enc->hw_ctl) { 2351 DPU_DEBUG("[wb:%d] no ctl assigned\n", 2352 phys_enc->hw_wb->idx - WB_0); 2353 return; 2354 } 2355 2356 dpu_kms = phys_enc->dpu_kms; 2357 global_state = dpu_kms_get_existing_global_state(dpu_kms); 2358 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 2359 phys_enc->parent->crtc, 2360 DPU_HW_BLK_PINGPONG, rt_pp_list, 2361 ARRAY_SIZE(rt_pp_list)); 2362 2363 if (num_pp == 0 || num_pp > MAX_CHANNELS_PER_ENC) { 2364 DPU_DEBUG_ENC(dpu_enc, "invalid num_pp %d\n", num_pp); 2365 return; 2366 } 2367 2368 /* 2369 * The CWB mux supports using LM or DSPP as tap points. For now, 2370 * always use LM tap point 2371 */ 2372 cwb_cfg.input = INPUT_MODE_LM_OUT; 2373 2374 for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2375 hw_cwb = dpu_enc->hw_cwb[i]; 2376 if (!hw_cwb) 2377 continue; 2378 2379 if (enable) { 2380 struct dpu_hw_pingpong *hw_pp = 2381 to_dpu_hw_pingpong(rt_pp_list[i]); 2382 cwb_cfg.pp_idx = hw_pp->idx; 2383 } else { 2384 cwb_cfg.pp_idx = PINGPONG_NONE; 2385 } 2386 2387 hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg); 2388 2389 if (hw_ctl->ops.update_pending_flush_cwb) 2390 hw_ctl->ops.update_pending_flush_cwb(hw_ctl, hw_cwb->idx); 2391 } 2392 } 2393 2394 /** 2395 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 2396 * @phys_enc: Pointer to physical encoder 2397 * @dpu_fmt: Pinter to the format description 2398 * @output_type: HDMI/WB 2399 */ 2400 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 2401 const struct msm_format *dpu_fmt, 2402 u32 output_type) 2403 { 2404 struct dpu_hw_cdm *hw_cdm; 2405 struct dpu_hw_cdm_cfg *cdm_cfg; 2406 struct dpu_hw_pingpong *hw_pp; 2407 int ret; 2408 2409 if (!phys_enc) 2410 return; 2411 2412 cdm_cfg = &phys_enc->cdm_cfg; 2413 hw_pp = phys_enc->hw_pp; 2414 hw_cdm = phys_enc->hw_cdm; 2415 2416 if (!hw_cdm) 2417 return; 2418 2419 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) { 2420 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), 2421 &dpu_fmt->pixel_format); 2422 if (hw_cdm->ops.bind_pingpong_blk) 2423 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); 2424 2425 return; 2426 } 2427 2428 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); 2429 2430 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; 2431 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; 2432 cdm_cfg->output_fmt = dpu_fmt; 2433 cdm_cfg->output_type = output_type; 2434 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ? 2435 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; 2436 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; 2437 2438 /* enable 10 bit logic */ 2439 switch (cdm_cfg->output_fmt->chroma_sample) { 2440 case CHROMA_FULL: 2441 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2442 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2443 break; 2444 case CHROMA_H2V1: 2445 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2446 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2447 break; 2448 case CHROMA_420: 2449 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2450 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; 2451 break; 2452 case CHROMA_H1V2: 2453 default: 2454 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", 2455 DRMID(phys_enc->parent)); 2456 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2457 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2458 break; 2459 } 2460 2461 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n", 2462 DRMID(phys_enc->parent), cdm_cfg->output_width, 2463 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format, 2464 cdm_cfg->output_type, cdm_cfg->output_bit_depth, 2465 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); 2466 2467 if (hw_cdm->ops.enable) { 2468 cdm_cfg->pp_id = hw_pp->idx; 2469 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg); 2470 if (ret < 0) { 2471 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n", 2472 DRMID(phys_enc->parent), ret); 2473 return; 2474 } 2475 } 2476 } 2477 2478 #ifdef CONFIG_DEBUG_FS 2479 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2480 { 2481 struct drm_encoder *drm_enc = s->private; 2482 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2483 int i; 2484 2485 mutex_lock(&dpu_enc->enc_lock); 2486 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2487 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2488 2489 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d", 2490 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2491 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2492 atomic_read(&phys->vsync_cnt), 2493 atomic_read(&phys->underrun_cnt), 2494 atomic_read(&dpu_enc->frame_done_timeout_cnt)); 2495 2496 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2497 } 2498 mutex_unlock(&dpu_enc->enc_lock); 2499 2500 return 0; 2501 } 2502 2503 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2504 2505 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root) 2506 { 2507 /* don't error check these */ 2508 debugfs_create_file("status", 0600, 2509 root, drm_enc, &_dpu_encoder_status_fops); 2510 } 2511 #else 2512 #define dpu_encoder_debugfs_init NULL 2513 #endif 2514 2515 static int dpu_encoder_virt_add_phys_encs( 2516 struct drm_device *dev, 2517 struct msm_display_info *disp_info, 2518 struct dpu_encoder_virt *dpu_enc, 2519 struct dpu_enc_phys_init_params *params) 2520 { 2521 struct dpu_encoder_phys *enc = NULL; 2522 2523 DPU_DEBUG_ENC(dpu_enc, "\n"); 2524 2525 /* 2526 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2527 * in this function, check up-front. 2528 */ 2529 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2530 ARRAY_SIZE(dpu_enc->phys_encs)) { 2531 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2532 dpu_enc->num_phys_encs); 2533 return -EINVAL; 2534 } 2535 2536 2537 if (disp_info->intf_type == INTF_WB) { 2538 enc = dpu_encoder_phys_wb_init(dev, params); 2539 2540 if (IS_ERR(enc)) { 2541 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2542 PTR_ERR(enc)); 2543 return PTR_ERR(enc); 2544 } 2545 2546 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2547 ++dpu_enc->num_phys_encs; 2548 } else if (disp_info->is_cmd_mode) { 2549 enc = dpu_encoder_phys_cmd_init(dev, params); 2550 2551 if (IS_ERR(enc)) { 2552 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2553 PTR_ERR(enc)); 2554 return PTR_ERR(enc); 2555 } 2556 2557 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2558 ++dpu_enc->num_phys_encs; 2559 } else { 2560 enc = dpu_encoder_phys_vid_init(dev, params); 2561 2562 if (IS_ERR(enc)) { 2563 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2564 PTR_ERR(enc)); 2565 return PTR_ERR(enc); 2566 } 2567 2568 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2569 ++dpu_enc->num_phys_encs; 2570 } 2571 2572 if (params->split_role == ENC_ROLE_SLAVE) 2573 dpu_enc->cur_slave = enc; 2574 else 2575 dpu_enc->cur_master = enc; 2576 2577 return 0; 2578 } 2579 2580 /** 2581 * dpu_encoder_get_clones - Calculate the possible_clones for DPU encoder 2582 * @drm_enc: DRM encoder pointer 2583 * Returns: possible_clones mask 2584 */ 2585 uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc) 2586 { 2587 struct drm_encoder *curr; 2588 int type = drm_enc->encoder_type; 2589 uint32_t clone_mask = drm_encoder_mask(drm_enc); 2590 2591 /* 2592 * Set writeback as possible clones of real-time DSI encoders and vice 2593 * versa 2594 * 2595 * Writeback encoders can't be clones of each other and DSI 2596 * encoders can't be clones of each other. 2597 * 2598 * TODO: Add DP encoders as valid possible clones for writeback encoders 2599 * (and vice versa) once concurrent writeback has been validated for DP 2600 */ 2601 drm_for_each_encoder(curr, drm_enc->dev) { 2602 if ((type == DRM_MODE_ENCODER_VIRTUAL && 2603 curr->encoder_type == DRM_MODE_ENCODER_DSI) || 2604 (type == DRM_MODE_ENCODER_DSI && 2605 curr->encoder_type == DRM_MODE_ENCODER_VIRTUAL)) 2606 clone_mask |= drm_encoder_mask(curr); 2607 } 2608 2609 return clone_mask; 2610 } 2611 2612 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2613 struct dpu_kms *dpu_kms, 2614 struct msm_display_info *disp_info) 2615 { 2616 int ret = 0; 2617 int i = 0; 2618 struct dpu_enc_phys_init_params phys_params; 2619 2620 if (!dpu_enc) { 2621 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2622 return -EINVAL; 2623 } 2624 2625 dpu_enc->cur_master = NULL; 2626 2627 memset(&phys_params, 0, sizeof(phys_params)); 2628 phys_params.dpu_kms = dpu_kms; 2629 phys_params.parent = &dpu_enc->base; 2630 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2631 2632 WARN_ON(disp_info->num_of_h_tiles < 1); 2633 2634 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2635 2636 if (disp_info->intf_type != INTF_WB) 2637 dpu_enc->idle_pc_supported = 2638 dpu_kms->catalog->caps->has_idle_pc; 2639 2640 mutex_lock(&dpu_enc->enc_lock); 2641 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2642 /* 2643 * Left-most tile is at index 0, content is controller id 2644 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2645 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2646 */ 2647 u32 controller_id = disp_info->h_tile_instance[i]; 2648 2649 if (disp_info->num_of_h_tiles > 1) { 2650 if (i == 0) 2651 phys_params.split_role = ENC_ROLE_MASTER; 2652 else 2653 phys_params.split_role = ENC_ROLE_SLAVE; 2654 } else { 2655 phys_params.split_role = ENC_ROLE_SOLO; 2656 } 2657 2658 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2659 i, controller_id, phys_params.split_role); 2660 2661 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2662 disp_info->intf_type, 2663 controller_id); 2664 2665 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2666 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2667 2668 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2669 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2670 ret = -EINVAL; 2671 break; 2672 } 2673 2674 if (phys_params.hw_intf && phys_params.hw_wb) { 2675 DPU_ERROR_ENC(dpu_enc, 2676 "invalid phys both intf and wb block at idx: %d\n", i); 2677 ret = -EINVAL; 2678 break; 2679 } 2680 2681 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, 2682 dpu_enc, &phys_params); 2683 if (ret) { 2684 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2685 break; 2686 } 2687 } 2688 2689 mutex_unlock(&dpu_enc->enc_lock); 2690 2691 return ret; 2692 } 2693 2694 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2695 { 2696 struct dpu_encoder_virt *dpu_enc = timer_container_of(dpu_enc, t, 2697 frame_done_timer); 2698 struct drm_encoder *drm_enc = &dpu_enc->base; 2699 u32 event; 2700 2701 if (!drm_enc->dev) { 2702 DPU_ERROR("invalid parameters\n"); 2703 return; 2704 } 2705 2706 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) { 2707 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2708 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2709 return; 2710 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2711 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2712 return; 2713 } 2714 2715 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n"); 2716 2717 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1) 2718 msm_disp_snapshot_state(drm_enc->dev); 2719 2720 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2721 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2722 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 2723 } 2724 2725 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2726 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2727 .atomic_disable = dpu_encoder_virt_atomic_disable, 2728 .atomic_enable = dpu_encoder_virt_atomic_enable, 2729 }; 2730 2731 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2732 .debugfs_init = dpu_encoder_debugfs_init, 2733 }; 2734 2735 /** 2736 * dpu_encoder_init - initialize virtual encoder object 2737 * @dev: Pointer to drm device structure 2738 * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 2739 * @disp_info: Pointer to display information structure 2740 * Returns: Pointer to newly created drm encoder 2741 */ 2742 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2743 int drm_enc_mode, 2744 struct msm_display_info *disp_info) 2745 { 2746 struct msm_drm_private *priv = dev->dev_private; 2747 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2748 struct dpu_encoder_virt *dpu_enc; 2749 int ret; 2750 2751 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base, 2752 &dpu_encoder_funcs, drm_enc_mode, NULL); 2753 if (IS_ERR(dpu_enc)) 2754 return ERR_CAST(dpu_enc); 2755 2756 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2757 2758 spin_lock_init(&dpu_enc->enc_spinlock); 2759 dpu_enc->enabled = false; 2760 mutex_init(&dpu_enc->enc_lock); 2761 mutex_init(&dpu_enc->rc_lock); 2762 2763 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2764 if (ret) { 2765 DPU_ERROR("failed to setup encoder\n"); 2766 return ERR_PTR(-ENOMEM); 2767 } 2768 2769 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2770 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 2771 timer_setup(&dpu_enc->frame_done_timer, 2772 dpu_encoder_frame_done_timeout, 0); 2773 2774 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2775 dpu_encoder_off_work); 2776 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2777 2778 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2779 2780 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2781 2782 return &dpu_enc->base; 2783 } 2784 2785 /** 2786 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state 2787 * @drm_enc: encoder pointer 2788 * 2789 * Wait for hardware to have flushed the current pending changes to hardware at 2790 * a vblank or CTL_START. Physical encoders will map this differently depending 2791 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. 2792 * 2793 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2794 */ 2795 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) 2796 { 2797 struct dpu_encoder_virt *dpu_enc = NULL; 2798 int i, ret = 0; 2799 2800 if (!drm_enc) { 2801 DPU_ERROR("invalid encoder\n"); 2802 return -EINVAL; 2803 } 2804 dpu_enc = to_dpu_encoder_virt(drm_enc); 2805 DPU_DEBUG_ENC(dpu_enc, "\n"); 2806 2807 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2808 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2809 2810 if (phys->ops.wait_for_commit_done) { 2811 DPU_ATRACE_BEGIN("wait_for_commit_done"); 2812 ret = phys->ops.wait_for_commit_done(phys); 2813 DPU_ATRACE_END("wait_for_commit_done"); 2814 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { 2815 dpu_enc->commit_done_timedout = true; 2816 msm_disp_snapshot_state(drm_enc->dev); 2817 } 2818 if (ret) 2819 return ret; 2820 } 2821 } 2822 2823 return ret; 2824 } 2825 2826 /** 2827 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel 2828 * @drm_enc: encoder pointer 2829 * 2830 * Wait for the hardware to transfer all the pixels to the panel. Physical 2831 * encoders will map this differently depending on the type: vid mode -> vsync_irq, 2832 * cmd mode -> pp_done. 2833 * 2834 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2835 */ 2836 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) 2837 { 2838 struct dpu_encoder_virt *dpu_enc = NULL; 2839 int i, ret = 0; 2840 2841 if (!drm_enc) { 2842 DPU_ERROR("invalid encoder\n"); 2843 return -EINVAL; 2844 } 2845 dpu_enc = to_dpu_encoder_virt(drm_enc); 2846 DPU_DEBUG_ENC(dpu_enc, "\n"); 2847 2848 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2849 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2850 2851 if (phys->ops.wait_for_tx_complete) { 2852 DPU_ATRACE_BEGIN("wait_for_tx_complete"); 2853 ret = phys->ops.wait_for_tx_complete(phys); 2854 DPU_ATRACE_END("wait_for_tx_complete"); 2855 if (ret) 2856 return ret; 2857 } 2858 } 2859 2860 return ret; 2861 } 2862 2863 /** 2864 * dpu_encoder_get_intf_mode - get interface mode of the given encoder 2865 * @encoder: Pointer to drm encoder object 2866 */ 2867 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2868 { 2869 struct dpu_encoder_virt *dpu_enc = NULL; 2870 2871 if (!encoder) { 2872 DPU_ERROR("invalid encoder\n"); 2873 return INTF_MODE_NONE; 2874 } 2875 dpu_enc = to_dpu_encoder_virt(encoder); 2876 2877 if (dpu_enc->cur_master) 2878 return dpu_enc->cur_master->intf_mode; 2879 2880 if (dpu_enc->num_phys_encs) 2881 return dpu_enc->phys_encs[0]->intf_mode; 2882 2883 return INTF_MODE_NONE; 2884 } 2885 2886 /** 2887 * dpu_encoder_helper_get_cwb_mask - get CWB blocks mask for the DPU encoder 2888 * @phys_enc: Pointer to physical encoder structure 2889 */ 2890 unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc) 2891 { 2892 struct drm_encoder *encoder = phys_enc->parent; 2893 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2894 2895 return dpu_enc->cwb_mask; 2896 } 2897 2898 /** 2899 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 2900 * This helper function is used by physical encoder to get DSC blocks mask 2901 * used for this encoder. 2902 * @phys_enc: Pointer to physical encoder structure 2903 */ 2904 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2905 { 2906 struct drm_encoder *encoder = phys_enc->parent; 2907 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2908 2909 return dpu_enc->dsc_mask; 2910 } 2911 2912 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2913 struct dpu_enc_phys_init_params *p) 2914 { 2915 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2916 phys_enc->hw_intf = p->hw_intf; 2917 phys_enc->hw_wb = p->hw_wb; 2918 phys_enc->parent = p->parent; 2919 phys_enc->dpu_kms = p->dpu_kms; 2920 phys_enc->split_role = p->split_role; 2921 phys_enc->enc_spinlock = p->enc_spinlock; 2922 phys_enc->enable_state = DPU_ENC_DISABLED; 2923 2924 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2925 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2926 2927 atomic_set(&phys_enc->vsync_cnt, 0); 2928 atomic_set(&phys_enc->underrun_cnt, 0); 2929 2930 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2931 } 2932