1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_framebuffer.h> 20 21 #include "msm_drv.h" 22 #include "dpu_kms.h" 23 #include "dpu_hwio.h" 24 #include "dpu_hw_catalog.h" 25 #include "dpu_hw_intf.h" 26 #include "dpu_hw_ctl.h" 27 #include "dpu_hw_dspp.h" 28 #include "dpu_hw_dsc.h" 29 #include "dpu_hw_merge3d.h" 30 #include "dpu_hw_cdm.h" 31 #include "dpu_formats.h" 32 #include "dpu_encoder_phys.h" 33 #include "dpu_crtc.h" 34 #include "dpu_trace.h" 35 #include "dpu_core_irq.h" 36 #include "disp/msm_disp_snapshot.h" 37 38 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 40 41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 43 44 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\ 45 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 46 47 /* 48 * Two to anticipate panels that can do cmd/vid dynamic switching 49 * plan is to create all possible physical encoder types, and switch between 50 * them at runtime 51 */ 52 #define NUM_PHYS_ENCODER_TYPES 2 53 54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 56 57 #define MAX_CHANNELS_PER_ENC 2 58 59 #define IDLE_SHORT_TIMEOUT 1 60 61 #define MAX_HDISPLAY_SPLIT 1080 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @enabled: True if the encoder is active, protected by enc_lock 129 * @num_phys_encs: Actual number of physical encoders contained. 130 * @phys_encs: Container of physical encoders managed. 131 * @cur_master: Pointer to the current master in this mode. Optimization 132 * Only valid after enable. Cleared as disable. 133 * @cur_slave: As above but for the slave encoder. 134 * @hw_pp: Handle to the pingpong blocks used for the display. No. 135 * pingpong blocks can be different than num_phys_encs. 136 * @hw_dsc: Handle to the DSC blocks used for the display. 137 * @dsc_mask: Bitmask of used DSC blocks. 138 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 139 * for partial update right-only cases, such as pingpong 140 * split where virtual pingpong does not generate IRQs 141 * @crtc: Pointer to the currently assigned crtc. Normally you 142 * would use crtc->state->encoder_mask to determine the 143 * link between encoder/crtc. However in this case we need 144 * to track crtc in the disable() hook which is called 145 * _after_ encoder_mask is cleared. 146 * @connector: If a mode is set, cached pointer to the active connector 147 * @enc_lock: Lock around physical encoder 148 * create/destroy/enable/disable 149 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 150 * busy processing current command. 151 * Bit0 = phys_encs[0] etc. 152 * @crtc_frame_event_cb: callback handler for frame event 153 * @crtc_frame_event_cb_data: callback handler private data 154 * @frame_done_timeout_ms: frame done timeout in ms 155 * @frame_done_timeout_cnt: atomic counter tracking the number of frame 156 * done timeouts 157 * @frame_done_timer: watchdog timer for frame done event 158 * @disp_info: local copy of msm_display_info struct 159 * @idle_pc_supported: indicate if idle power collaps is supported 160 * @rc_lock: resource control mutex lock to protect 161 * virt encoder over various state changes 162 * @rc_state: resource controller state 163 * @delayed_off_work: delayed worker to schedule disabling of 164 * clks and resources after IDLE_TIMEOUT time. 165 * @topology: topology of the display 166 * @idle_timeout: idle timeout duration in milliseconds 167 * @wide_bus_en: wide bus is enabled on this interface 168 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 169 */ 170 struct dpu_encoder_virt { 171 struct drm_encoder base; 172 spinlock_t enc_spinlock; 173 174 bool enabled; 175 176 unsigned int num_phys_encs; 177 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 178 struct dpu_encoder_phys *cur_master; 179 struct dpu_encoder_phys *cur_slave; 180 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 181 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 182 183 unsigned int dsc_mask; 184 185 bool intfs_swapped; 186 187 struct drm_crtc *crtc; 188 struct drm_connector *connector; 189 190 struct mutex enc_lock; 191 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 192 void (*crtc_frame_event_cb)(void *, u32 event); 193 void *crtc_frame_event_cb_data; 194 195 atomic_t frame_done_timeout_ms; 196 atomic_t frame_done_timeout_cnt; 197 struct timer_list frame_done_timer; 198 199 struct msm_display_info disp_info; 200 201 bool idle_pc_supported; 202 struct mutex rc_lock; 203 enum dpu_enc_rc_states rc_state; 204 struct delayed_work delayed_off_work; 205 struct msm_display_topology topology; 206 207 u32 idle_timeout; 208 209 bool wide_bus_en; 210 211 /* DSC configuration */ 212 struct drm_dsc_config *dsc; 213 }; 214 215 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 216 217 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 218 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 219 }; 220 221 222 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 223 { 224 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 225 226 return dpu_enc->wide_bus_en; 227 } 228 229 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 230 { 231 struct dpu_encoder_virt *dpu_enc; 232 int i, num_intf = 0; 233 234 dpu_enc = to_dpu_encoder_virt(drm_enc); 235 236 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 237 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 238 239 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 240 && phys->hw_intf->ops.collect_misr) 241 num_intf++; 242 } 243 244 return num_intf; 245 } 246 247 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 248 { 249 struct dpu_encoder_virt *dpu_enc; 250 251 int i; 252 253 dpu_enc = to_dpu_encoder_virt(drm_enc); 254 255 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 256 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 257 258 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 259 continue; 260 261 phys->hw_intf->ops.setup_misr(phys->hw_intf); 262 } 263 } 264 265 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 266 { 267 struct dpu_encoder_virt *dpu_enc; 268 269 int i, rc = 0, entries_added = 0; 270 271 if (!drm_enc->crtc) { 272 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 273 return -EINVAL; 274 } 275 276 dpu_enc = to_dpu_encoder_virt(drm_enc); 277 278 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 279 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 280 281 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 282 continue; 283 284 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 285 if (rc) 286 return rc; 287 entries_added++; 288 } 289 290 return entries_added; 291 } 292 293 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 294 { 295 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 296 297 if (!hw_pp->ops.setup_dither) 298 return; 299 300 switch (bpc) { 301 case 6: 302 dither_cfg.c0_bitdepth = 6; 303 dither_cfg.c1_bitdepth = 6; 304 dither_cfg.c2_bitdepth = 6; 305 dither_cfg.c3_bitdepth = 6; 306 dither_cfg.temporal_en = 0; 307 break; 308 default: 309 hw_pp->ops.setup_dither(hw_pp, NULL); 310 return; 311 } 312 313 memcpy(&dither_cfg.matrix, dither_matrix, 314 sizeof(u32) * DITHER_MATRIX_SZ); 315 316 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 317 } 318 319 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 320 { 321 switch (intf_mode) { 322 case INTF_MODE_VIDEO: 323 return "INTF_MODE_VIDEO"; 324 case INTF_MODE_CMD: 325 return "INTF_MODE_CMD"; 326 case INTF_MODE_WB_BLOCK: 327 return "INTF_MODE_WB_BLOCK"; 328 case INTF_MODE_WB_LINE: 329 return "INTF_MODE_WB_LINE"; 330 default: 331 return "INTF_MODE_UNKNOWN"; 332 } 333 } 334 335 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 336 enum dpu_intr_idx intr_idx) 337 { 338 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 339 DRMID(phys_enc->parent), 340 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 341 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 342 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 343 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 344 345 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 346 DPU_ENCODER_FRAME_EVENT_ERROR); 347 } 348 349 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 350 u32 irq_idx, struct dpu_encoder_wait_info *info); 351 352 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 353 unsigned int irq_idx, 354 void (*func)(void *arg), 355 struct dpu_encoder_wait_info *wait_info) 356 { 357 u32 irq_status; 358 int ret; 359 360 if (!wait_info) { 361 DPU_ERROR("invalid params\n"); 362 return -EINVAL; 363 } 364 /* note: do master / slave checking outside */ 365 366 /* return EWOULDBLOCK since we know the wait isn't necessary */ 367 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 368 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 369 DRMID(phys_enc->parent), func, 370 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 371 return -EWOULDBLOCK; 372 } 373 374 if (irq_idx < 0) { 375 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 376 DRMID(phys_enc->parent), func); 377 return 0; 378 } 379 380 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 381 DRMID(phys_enc->parent), func, 382 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 383 atomic_read(wait_info->atomic_cnt)); 384 385 ret = dpu_encoder_helper_wait_event_timeout( 386 DRMID(phys_enc->parent), 387 irq_idx, 388 wait_info); 389 390 if (ret <= 0) { 391 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 392 if (irq_status) { 393 unsigned long flags; 394 395 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 396 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 397 DRMID(phys_enc->parent), func, 398 phys_enc->hw_pp->idx - PINGPONG_0, 399 atomic_read(wait_info->atomic_cnt)); 400 local_irq_save(flags); 401 func(phys_enc); 402 local_irq_restore(flags); 403 ret = 0; 404 } else { 405 ret = -ETIMEDOUT; 406 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 407 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 408 DRMID(phys_enc->parent), func, 409 phys_enc->hw_pp->idx - PINGPONG_0, 410 atomic_read(wait_info->atomic_cnt)); 411 } 412 } else { 413 ret = 0; 414 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 415 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 416 phys_enc->hw_pp->idx - PINGPONG_0, 417 atomic_read(wait_info->atomic_cnt)); 418 } 419 420 return ret; 421 } 422 423 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 424 { 425 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 426 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 427 return phys ? atomic_read(&phys->vsync_cnt) : 0; 428 } 429 430 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 431 { 432 struct dpu_encoder_virt *dpu_enc; 433 struct dpu_encoder_phys *phys; 434 int linecount = 0; 435 436 dpu_enc = to_dpu_encoder_virt(drm_enc); 437 phys = dpu_enc ? dpu_enc->cur_master : NULL; 438 439 if (phys && phys->ops.get_line_count) 440 linecount = phys->ops.get_line_count(phys); 441 442 return linecount; 443 } 444 445 void dpu_encoder_helper_split_config( 446 struct dpu_encoder_phys *phys_enc, 447 enum dpu_intf interface) 448 { 449 struct dpu_encoder_virt *dpu_enc; 450 struct split_pipe_cfg cfg = { 0 }; 451 struct dpu_hw_mdp *hw_mdptop; 452 struct msm_display_info *disp_info; 453 454 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 455 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 456 return; 457 } 458 459 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 460 hw_mdptop = phys_enc->hw_mdptop; 461 disp_info = &dpu_enc->disp_info; 462 463 if (disp_info->intf_type != INTF_DSI) 464 return; 465 466 /** 467 * disable split modes since encoder will be operating in as the only 468 * encoder, either for the entire use case in the case of, for example, 469 * single DSI, or for this frame in the case of left/right only partial 470 * update. 471 */ 472 if (phys_enc->split_role == ENC_ROLE_SOLO) { 473 if (hw_mdptop->ops.setup_split_pipe) 474 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 475 return; 476 } 477 478 cfg.en = true; 479 cfg.mode = phys_enc->intf_mode; 480 cfg.intf = interface; 481 482 if (cfg.en && phys_enc->ops.needs_single_flush && 483 phys_enc->ops.needs_single_flush(phys_enc)) 484 cfg.split_flush_en = true; 485 486 if (phys_enc->split_role == ENC_ROLE_MASTER) { 487 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 488 489 if (hw_mdptop->ops.setup_split_pipe) 490 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 491 } 492 } 493 494 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 495 { 496 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 497 int i, intf_count = 0, num_dsc = 0; 498 499 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 500 if (dpu_enc->phys_encs[i]) 501 intf_count++; 502 503 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ 504 if (dpu_enc->dsc) 505 num_dsc = 2; 506 507 return (num_dsc > 0) && (num_dsc > intf_count); 508 } 509 510 static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 511 { 512 struct msm_drm_private *priv = drm_enc->dev->dev_private; 513 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 514 int index = dpu_enc->disp_info.h_tile_instance[0]; 515 516 if (dpu_enc->disp_info.intf_type == INTF_DSI) 517 return msm_dsi_get_dsc_config(priv->dsi[index]); 518 519 return NULL; 520 } 521 522 static struct msm_display_topology dpu_encoder_get_topology( 523 struct dpu_encoder_virt *dpu_enc, 524 struct dpu_kms *dpu_kms, 525 struct drm_display_mode *mode, 526 struct drm_crtc_state *crtc_state, 527 struct drm_dsc_config *dsc) 528 { 529 struct msm_display_topology topology = {0}; 530 int i, intf_count = 0; 531 532 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 533 if (dpu_enc->phys_encs[i]) 534 intf_count++; 535 536 /* Datapath topology selection 537 * 538 * Dual display 539 * 2 LM, 2 INTF ( Split display using 2 interfaces) 540 * 541 * Single display 542 * 1 LM, 1 INTF 543 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 544 * 545 * Add dspps to the reservation requirements if ctm is requested 546 */ 547 if (intf_count == 2) 548 topology.num_lm = 2; 549 else if (!dpu_kms->catalog->caps->has_3d_merge) 550 topology.num_lm = 1; 551 else 552 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 553 554 if (crtc_state->ctm) 555 topology.num_dspp = topology.num_lm; 556 557 topology.num_intf = intf_count; 558 559 if (dsc) { 560 /* 561 * In case of Display Stream Compression (DSC), we would use 562 * 2 DSC encoders, 2 layer mixers and 1 interface 563 * this is power optimal and can drive up to (including) 4k 564 * screens 565 */ 566 topology.num_dsc = 2; 567 topology.num_lm = 2; 568 topology.num_intf = 1; 569 } 570 571 return topology; 572 } 573 574 static int dpu_encoder_virt_atomic_check( 575 struct drm_encoder *drm_enc, 576 struct drm_crtc_state *crtc_state, 577 struct drm_connector_state *conn_state) 578 { 579 struct dpu_encoder_virt *dpu_enc; 580 struct msm_drm_private *priv; 581 struct dpu_kms *dpu_kms; 582 struct drm_display_mode *adj_mode; 583 struct msm_display_topology topology; 584 struct dpu_global_state *global_state; 585 struct drm_framebuffer *fb; 586 struct drm_dsc_config *dsc; 587 int i = 0; 588 int ret = 0; 589 590 if (!drm_enc || !crtc_state || !conn_state) { 591 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 592 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 593 return -EINVAL; 594 } 595 596 dpu_enc = to_dpu_encoder_virt(drm_enc); 597 DPU_DEBUG_ENC(dpu_enc, "\n"); 598 599 priv = drm_enc->dev->dev_private; 600 dpu_kms = to_dpu_kms(priv->kms); 601 adj_mode = &crtc_state->adjusted_mode; 602 global_state = dpu_kms_get_global_state(crtc_state->state); 603 if (IS_ERR(global_state)) 604 return PTR_ERR(global_state); 605 606 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 607 608 /* perform atomic check on the first physical encoder (master) */ 609 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 610 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 611 612 if (phys->ops.atomic_check) 613 ret = phys->ops.atomic_check(phys, crtc_state, 614 conn_state); 615 if (ret) { 616 DPU_ERROR_ENC(dpu_enc, 617 "mode unsupported, phys idx %d\n", i); 618 return ret; 619 } 620 } 621 622 dsc = dpu_encoder_get_dsc_config(drm_enc); 623 624 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); 625 626 /* 627 * Use CDM only for writeback at the moment as other interfaces cannot handle it. 628 * if writeback itself cannot handle cdm for some reason it will fail in its atomic_check() 629 * earlier. 630 */ 631 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 632 fb = conn_state->writeback_job->fb; 633 634 if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb)))) 635 topology.needs_cdm = true; 636 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) 637 crtc_state->mode_changed = true; 638 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) 639 crtc_state->mode_changed = true; 640 } 641 642 /* 643 * Release and Allocate resources on every modeset 644 * Dont allocate when active is false. 645 */ 646 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 647 dpu_rm_release(global_state, drm_enc); 648 649 if (!crtc_state->active_changed || crtc_state->enable) 650 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 651 drm_enc, crtc_state, topology); 652 } 653 654 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 655 656 return ret; 657 } 658 659 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 660 struct msm_display_info *disp_info) 661 { 662 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 663 struct msm_drm_private *priv; 664 struct dpu_kms *dpu_kms; 665 struct dpu_hw_mdp *hw_mdptop; 666 struct drm_encoder *drm_enc; 667 struct dpu_encoder_phys *phys_enc; 668 int i; 669 670 if (!dpu_enc || !disp_info) { 671 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 672 dpu_enc != NULL, disp_info != NULL); 673 return; 674 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 675 DPU_ERROR("invalid num phys enc %d/%d\n", 676 dpu_enc->num_phys_encs, 677 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 678 return; 679 } 680 681 drm_enc = &dpu_enc->base; 682 /* this pointers are checked in virt_enable_helper */ 683 priv = drm_enc->dev->dev_private; 684 685 dpu_kms = to_dpu_kms(priv->kms); 686 hw_mdptop = dpu_kms->hw_mdp; 687 if (!hw_mdptop) { 688 DPU_ERROR("invalid mdptop\n"); 689 return; 690 } 691 692 if (hw_mdptop->ops.setup_vsync_source && 693 disp_info->is_cmd_mode) { 694 for (i = 0; i < dpu_enc->num_phys_encs; i++) 695 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 696 697 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 698 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 699 700 if (disp_info->is_te_using_watchdog_timer) 701 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 702 else 703 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 704 705 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 706 707 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 708 phys_enc = dpu_enc->phys_encs[i]; 709 710 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 711 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 712 vsync_cfg.vsync_source); 713 } 714 } 715 } 716 717 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 718 { 719 struct dpu_encoder_virt *dpu_enc; 720 int i; 721 722 if (!drm_enc) { 723 DPU_ERROR("invalid encoder\n"); 724 return; 725 } 726 727 dpu_enc = to_dpu_encoder_virt(drm_enc); 728 729 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 730 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 731 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 732 733 if (phys->ops.irq_control) 734 phys->ops.irq_control(phys, enable); 735 } 736 737 } 738 739 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 740 bool enable) 741 { 742 struct msm_drm_private *priv; 743 struct dpu_kms *dpu_kms; 744 struct dpu_encoder_virt *dpu_enc; 745 746 dpu_enc = to_dpu_encoder_virt(drm_enc); 747 priv = drm_enc->dev->dev_private; 748 dpu_kms = to_dpu_kms(priv->kms); 749 750 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 751 752 if (!dpu_enc->cur_master) { 753 DPU_ERROR("encoder master not set\n"); 754 return; 755 } 756 757 if (enable) { 758 /* enable DPU core clks */ 759 pm_runtime_get_sync(&dpu_kms->pdev->dev); 760 761 /* enable all the irq */ 762 _dpu_encoder_irq_control(drm_enc, true); 763 764 } else { 765 /* disable all the irq */ 766 _dpu_encoder_irq_control(drm_enc, false); 767 768 /* disable DPU core clks */ 769 pm_runtime_put_sync(&dpu_kms->pdev->dev); 770 } 771 772 } 773 774 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 775 u32 sw_event) 776 { 777 struct dpu_encoder_virt *dpu_enc; 778 struct msm_drm_private *priv; 779 bool is_vid_mode = false; 780 781 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 782 DPU_ERROR("invalid parameters\n"); 783 return -EINVAL; 784 } 785 dpu_enc = to_dpu_encoder_virt(drm_enc); 786 priv = drm_enc->dev->dev_private; 787 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 788 789 /* 790 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 791 * events and return early for other events (ie wb display). 792 */ 793 if (!dpu_enc->idle_pc_supported && 794 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 795 sw_event != DPU_ENC_RC_EVENT_STOP && 796 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 797 return 0; 798 799 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 800 dpu_enc->rc_state, "begin"); 801 802 switch (sw_event) { 803 case DPU_ENC_RC_EVENT_KICKOFF: 804 /* cancel delayed off work, if any */ 805 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 806 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 807 sw_event); 808 809 mutex_lock(&dpu_enc->rc_lock); 810 811 /* return if the resource control is already in ON state */ 812 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 813 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 814 DRMID(drm_enc), sw_event); 815 mutex_unlock(&dpu_enc->rc_lock); 816 return 0; 817 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 818 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 819 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 820 DRMID(drm_enc), sw_event, 821 dpu_enc->rc_state); 822 mutex_unlock(&dpu_enc->rc_lock); 823 return -EINVAL; 824 } 825 826 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 827 _dpu_encoder_irq_control(drm_enc, true); 828 else 829 _dpu_encoder_resource_control_helper(drm_enc, true); 830 831 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 832 833 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 834 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 835 "kickoff"); 836 837 mutex_unlock(&dpu_enc->rc_lock); 838 break; 839 840 case DPU_ENC_RC_EVENT_FRAME_DONE: 841 /* 842 * mutex lock is not used as this event happens at interrupt 843 * context. And locking is not required as, the other events 844 * like KICKOFF and STOP does a wait-for-idle before executing 845 * the resource_control 846 */ 847 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 848 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 849 DRMID(drm_enc), sw_event, 850 dpu_enc->rc_state); 851 return -EINVAL; 852 } 853 854 /* 855 * schedule off work item only when there are no 856 * frames pending 857 */ 858 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 859 DRM_DEBUG_KMS("id:%d skip schedule work\n", 860 DRMID(drm_enc)); 861 return 0; 862 } 863 864 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 865 msecs_to_jiffies(dpu_enc->idle_timeout)); 866 867 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 868 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 869 "frame done"); 870 break; 871 872 case DPU_ENC_RC_EVENT_PRE_STOP: 873 /* cancel delayed off work, if any */ 874 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 875 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 876 sw_event); 877 878 mutex_lock(&dpu_enc->rc_lock); 879 880 if (is_vid_mode && 881 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 882 _dpu_encoder_irq_control(drm_enc, true); 883 } 884 /* skip if is already OFF or IDLE, resources are off already */ 885 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 886 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 887 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 888 DRMID(drm_enc), sw_event, 889 dpu_enc->rc_state); 890 mutex_unlock(&dpu_enc->rc_lock); 891 return 0; 892 } 893 894 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 895 896 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 897 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 898 "pre stop"); 899 900 mutex_unlock(&dpu_enc->rc_lock); 901 break; 902 903 case DPU_ENC_RC_EVENT_STOP: 904 mutex_lock(&dpu_enc->rc_lock); 905 906 /* return if the resource control is already in OFF state */ 907 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 908 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 909 DRMID(drm_enc), sw_event); 910 mutex_unlock(&dpu_enc->rc_lock); 911 return 0; 912 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 913 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 914 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 915 mutex_unlock(&dpu_enc->rc_lock); 916 return -EINVAL; 917 } 918 919 /** 920 * expect to arrive here only if in either idle state or pre-off 921 * and in IDLE state the resources are already disabled 922 */ 923 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 924 _dpu_encoder_resource_control_helper(drm_enc, false); 925 926 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 927 928 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 929 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 930 "stop"); 931 932 mutex_unlock(&dpu_enc->rc_lock); 933 break; 934 935 case DPU_ENC_RC_EVENT_ENTER_IDLE: 936 mutex_lock(&dpu_enc->rc_lock); 937 938 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 939 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 940 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 941 mutex_unlock(&dpu_enc->rc_lock); 942 return 0; 943 } 944 945 /* 946 * if we are in ON but a frame was just kicked off, 947 * ignore the IDLE event, it's probably a stale timer event 948 */ 949 if (dpu_enc->frame_busy_mask[0]) { 950 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 951 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 952 mutex_unlock(&dpu_enc->rc_lock); 953 return 0; 954 } 955 956 if (is_vid_mode) 957 _dpu_encoder_irq_control(drm_enc, false); 958 else 959 _dpu_encoder_resource_control_helper(drm_enc, false); 960 961 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 962 963 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 964 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 965 "idle"); 966 967 mutex_unlock(&dpu_enc->rc_lock); 968 break; 969 970 default: 971 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 972 sw_event); 973 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 974 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 975 "error"); 976 break; 977 } 978 979 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 980 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 981 "end"); 982 return 0; 983 } 984 985 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 986 struct drm_writeback_job *job) 987 { 988 struct dpu_encoder_virt *dpu_enc; 989 int i; 990 991 dpu_enc = to_dpu_encoder_virt(drm_enc); 992 993 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 994 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 995 996 if (phys->ops.prepare_wb_job) 997 phys->ops.prepare_wb_job(phys, job); 998 999 } 1000 } 1001 1002 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1003 struct drm_writeback_job *job) 1004 { 1005 struct dpu_encoder_virt *dpu_enc; 1006 int i; 1007 1008 dpu_enc = to_dpu_encoder_virt(drm_enc); 1009 1010 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1011 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1012 1013 if (phys->ops.cleanup_wb_job) 1014 phys->ops.cleanup_wb_job(phys, job); 1015 1016 } 1017 } 1018 1019 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1020 struct drm_crtc_state *crtc_state, 1021 struct drm_connector_state *conn_state) 1022 { 1023 struct dpu_encoder_virt *dpu_enc; 1024 struct msm_drm_private *priv; 1025 struct dpu_kms *dpu_kms; 1026 struct dpu_crtc_state *cstate; 1027 struct dpu_global_state *global_state; 1028 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1029 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1030 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 1031 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 1032 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1033 int num_lm, num_ctl, num_pp, num_dsc; 1034 unsigned int dsc_mask = 0; 1035 int i; 1036 1037 if (!drm_enc) { 1038 DPU_ERROR("invalid encoder\n"); 1039 return; 1040 } 1041 1042 dpu_enc = to_dpu_encoder_virt(drm_enc); 1043 DPU_DEBUG_ENC(dpu_enc, "\n"); 1044 1045 priv = drm_enc->dev->dev_private; 1046 dpu_kms = to_dpu_kms(priv->kms); 1047 1048 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1049 if (IS_ERR_OR_NULL(global_state)) { 1050 DPU_ERROR("Failed to get global state"); 1051 return; 1052 } 1053 1054 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1055 1056 /* Query resource that have been reserved in atomic check step. */ 1057 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1058 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1059 ARRAY_SIZE(hw_pp)); 1060 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1061 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1062 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1063 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1064 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1065 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 1066 ARRAY_SIZE(hw_dspp)); 1067 1068 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1069 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1070 : NULL; 1071 1072 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1073 drm_enc->base.id, DPU_HW_BLK_DSC, 1074 hw_dsc, ARRAY_SIZE(hw_dsc)); 1075 for (i = 0; i < num_dsc; i++) { 1076 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1077 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1078 } 1079 1080 dpu_enc->dsc_mask = dsc_mask; 1081 1082 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 1083 struct dpu_hw_blk *hw_cdm = NULL; 1084 1085 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1086 drm_enc->base.id, DPU_HW_BLK_CDM, 1087 &hw_cdm, 1); 1088 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1089 } 1090 1091 cstate = to_dpu_crtc_state(crtc_state); 1092 1093 for (i = 0; i < num_lm; i++) { 1094 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1095 1096 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1097 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1098 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1099 } 1100 1101 cstate->num_mixers = num_lm; 1102 1103 dpu_enc->connector = conn_state->connector; 1104 1105 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1106 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1107 1108 if (!dpu_enc->hw_pp[i]) { 1109 DPU_ERROR_ENC(dpu_enc, 1110 "no pp block assigned at idx: %d\n", i); 1111 return; 1112 } 1113 1114 if (!hw_ctl[i]) { 1115 DPU_ERROR_ENC(dpu_enc, 1116 "no ctl block assigned at idx: %d\n", i); 1117 return; 1118 } 1119 1120 phys->hw_pp = dpu_enc->hw_pp[i]; 1121 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1122 1123 phys->cached_mode = crtc_state->adjusted_mode; 1124 if (phys->ops.atomic_mode_set) 1125 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1126 } 1127 } 1128 1129 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1130 { 1131 struct dpu_encoder_virt *dpu_enc = NULL; 1132 int i; 1133 1134 if (!drm_enc || !drm_enc->dev) { 1135 DPU_ERROR("invalid parameters\n"); 1136 return; 1137 } 1138 1139 dpu_enc = to_dpu_encoder_virt(drm_enc); 1140 if (!dpu_enc || !dpu_enc->cur_master) { 1141 DPU_ERROR("invalid dpu encoder/master\n"); 1142 return; 1143 } 1144 1145 1146 if (dpu_enc->disp_info.intf_type == INTF_DP && 1147 dpu_enc->cur_master->hw_mdptop && 1148 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1149 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1150 dpu_enc->cur_master->hw_mdptop); 1151 1152 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1153 1154 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1155 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1156 unsigned bpc = dpu_enc->connector->display_info.bpc; 1157 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1158 if (!dpu_enc->hw_pp[i]) 1159 continue; 1160 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1161 } 1162 } 1163 } 1164 1165 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1166 { 1167 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1168 1169 mutex_lock(&dpu_enc->enc_lock); 1170 1171 if (!dpu_enc->enabled) 1172 goto out; 1173 1174 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1175 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1176 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1177 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1178 1179 _dpu_encoder_virt_enable_helper(drm_enc); 1180 1181 out: 1182 mutex_unlock(&dpu_enc->enc_lock); 1183 } 1184 1185 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1186 struct drm_atomic_state *state) 1187 { 1188 struct dpu_encoder_virt *dpu_enc = NULL; 1189 int ret = 0; 1190 struct drm_display_mode *cur_mode = NULL; 1191 struct msm_drm_private *priv = drm_enc->dev->dev_private; 1192 struct msm_display_info *disp_info; 1193 int index; 1194 1195 dpu_enc = to_dpu_encoder_virt(drm_enc); 1196 disp_info = &dpu_enc->disp_info; 1197 index = disp_info->h_tile_instance[0]; 1198 1199 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1200 1201 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 1202 1203 if (disp_info->intf_type == INTF_DP) 1204 dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]); 1205 else if (disp_info->intf_type == INTF_DSI) 1206 dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]); 1207 1208 mutex_lock(&dpu_enc->enc_lock); 1209 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1210 1211 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1212 cur_mode->vdisplay); 1213 1214 /* always enable slave encoder before master */ 1215 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1216 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1217 1218 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1219 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1220 1221 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1222 if (ret) { 1223 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1224 ret); 1225 goto out; 1226 } 1227 1228 _dpu_encoder_virt_enable_helper(drm_enc); 1229 1230 dpu_enc->enabled = true; 1231 1232 out: 1233 mutex_unlock(&dpu_enc->enc_lock); 1234 } 1235 1236 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1237 struct drm_atomic_state *state) 1238 { 1239 struct dpu_encoder_virt *dpu_enc = NULL; 1240 struct drm_crtc *crtc; 1241 struct drm_crtc_state *old_state = NULL; 1242 int i = 0; 1243 1244 dpu_enc = to_dpu_encoder_virt(drm_enc); 1245 DPU_DEBUG_ENC(dpu_enc, "\n"); 1246 1247 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1248 if (crtc) 1249 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1250 1251 /* 1252 * The encoder is already disabled if self refresh mode was set earlier, 1253 * in the old_state for the corresponding crtc. 1254 */ 1255 if (old_state && old_state->self_refresh_active) 1256 return; 1257 1258 mutex_lock(&dpu_enc->enc_lock); 1259 dpu_enc->enabled = false; 1260 1261 trace_dpu_enc_disable(DRMID(drm_enc)); 1262 1263 /* wait for idle */ 1264 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1265 1266 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1267 1268 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1269 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1270 1271 if (phys->ops.disable) 1272 phys->ops.disable(phys); 1273 } 1274 1275 1276 /* after phys waits for frame-done, should be no more frames pending */ 1277 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1278 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1279 del_timer_sync(&dpu_enc->frame_done_timer); 1280 } 1281 1282 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1283 1284 dpu_enc->connector = NULL; 1285 1286 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1287 1288 mutex_unlock(&dpu_enc->enc_lock); 1289 } 1290 1291 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1292 struct dpu_rm *dpu_rm, 1293 enum dpu_intf_type type, u32 controller_id) 1294 { 1295 int i = 0; 1296 1297 if (type == INTF_WB) 1298 return NULL; 1299 1300 for (i = 0; i < catalog->intf_count; i++) { 1301 if (catalog->intf[i].type == type 1302 && catalog->intf[i].controller_id == controller_id) { 1303 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1304 } 1305 } 1306 1307 return NULL; 1308 } 1309 1310 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1311 struct dpu_encoder_phys *phy_enc) 1312 { 1313 struct dpu_encoder_virt *dpu_enc = NULL; 1314 unsigned long lock_flags; 1315 1316 if (!drm_enc || !phy_enc) 1317 return; 1318 1319 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1320 dpu_enc = to_dpu_encoder_virt(drm_enc); 1321 1322 atomic_inc(&phy_enc->vsync_cnt); 1323 1324 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1325 if (dpu_enc->crtc) 1326 dpu_crtc_vblank_callback(dpu_enc->crtc); 1327 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1328 1329 DPU_ATRACE_END("encoder_vblank_callback"); 1330 } 1331 1332 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1333 struct dpu_encoder_phys *phy_enc) 1334 { 1335 if (!phy_enc) 1336 return; 1337 1338 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1339 atomic_inc(&phy_enc->underrun_cnt); 1340 1341 /* trigger dump only on the first underrun */ 1342 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1343 msm_disp_snapshot_state(drm_enc->dev); 1344 1345 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1346 atomic_read(&phy_enc->underrun_cnt)); 1347 DPU_ATRACE_END("encoder_underrun_callback"); 1348 } 1349 1350 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1351 { 1352 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1353 unsigned long lock_flags; 1354 1355 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1356 /* crtc should always be cleared before re-assigning */ 1357 WARN_ON(crtc && dpu_enc->crtc); 1358 dpu_enc->crtc = crtc; 1359 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1360 } 1361 1362 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1363 struct drm_crtc *crtc, bool enable) 1364 { 1365 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1366 unsigned long lock_flags; 1367 int i; 1368 1369 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1370 1371 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1372 if (dpu_enc->crtc != crtc) { 1373 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1374 return; 1375 } 1376 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1377 1378 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1379 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1380 1381 if (phys->ops.control_vblank_irq) 1382 phys->ops.control_vblank_irq(phys, enable); 1383 } 1384 } 1385 1386 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1387 void (*frame_event_cb)(void *, u32 event), 1388 void *frame_event_cb_data) 1389 { 1390 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1391 unsigned long lock_flags; 1392 bool enable; 1393 1394 enable = frame_event_cb ? true : false; 1395 1396 if (!drm_enc) { 1397 DPU_ERROR("invalid encoder\n"); 1398 return; 1399 } 1400 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1401 1402 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1403 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1404 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1405 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1406 } 1407 1408 void dpu_encoder_frame_done_callback( 1409 struct drm_encoder *drm_enc, 1410 struct dpu_encoder_phys *ready_phys, u32 event) 1411 { 1412 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1413 unsigned int i; 1414 1415 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1416 | DPU_ENCODER_FRAME_EVENT_ERROR 1417 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1418 1419 if (!dpu_enc->frame_busy_mask[0]) { 1420 /** 1421 * suppress frame_done without waiter, 1422 * likely autorefresh 1423 */ 1424 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1425 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1426 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1427 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1428 return; 1429 } 1430 1431 /* One of the physical encoders has become idle */ 1432 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1433 if (dpu_enc->phys_encs[i] == ready_phys) { 1434 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1435 dpu_enc->frame_busy_mask[0]); 1436 clear_bit(i, dpu_enc->frame_busy_mask); 1437 } 1438 } 1439 1440 if (!dpu_enc->frame_busy_mask[0]) { 1441 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1442 del_timer(&dpu_enc->frame_done_timer); 1443 1444 dpu_encoder_resource_control(drm_enc, 1445 DPU_ENC_RC_EVENT_FRAME_DONE); 1446 1447 if (dpu_enc->crtc_frame_event_cb) 1448 dpu_enc->crtc_frame_event_cb( 1449 dpu_enc->crtc_frame_event_cb_data, 1450 event); 1451 } 1452 } else { 1453 if (dpu_enc->crtc_frame_event_cb) 1454 dpu_enc->crtc_frame_event_cb( 1455 dpu_enc->crtc_frame_event_cb_data, event); 1456 } 1457 } 1458 1459 static void dpu_encoder_off_work(struct work_struct *work) 1460 { 1461 struct dpu_encoder_virt *dpu_enc = container_of(work, 1462 struct dpu_encoder_virt, delayed_off_work.work); 1463 1464 dpu_encoder_resource_control(&dpu_enc->base, 1465 DPU_ENC_RC_EVENT_ENTER_IDLE); 1466 1467 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1468 DPU_ENCODER_FRAME_EVENT_IDLE); 1469 } 1470 1471 /** 1472 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1473 * @drm_enc: Pointer to drm encoder structure 1474 * @phys: Pointer to physical encoder structure 1475 * @extra_flush_bits: Additional bit mask to include in flush trigger 1476 */ 1477 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1478 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1479 { 1480 struct dpu_hw_ctl *ctl; 1481 int pending_kickoff_cnt; 1482 u32 ret = UINT_MAX; 1483 1484 if (!phys->hw_pp) { 1485 DPU_ERROR("invalid pingpong hw\n"); 1486 return; 1487 } 1488 1489 ctl = phys->hw_ctl; 1490 if (!ctl->ops.trigger_flush) { 1491 DPU_ERROR("missing trigger cb\n"); 1492 return; 1493 } 1494 1495 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1496 1497 if (extra_flush_bits && ctl->ops.update_pending_flush) 1498 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1499 1500 ctl->ops.trigger_flush(ctl); 1501 1502 if (ctl->ops.get_pending_flush) 1503 ret = ctl->ops.get_pending_flush(ctl); 1504 1505 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1506 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1507 phys->hw_intf ? phys->hw_intf->idx : -1, 1508 phys->hw_wb ? phys->hw_wb->idx : -1, 1509 pending_kickoff_cnt, ctl->idx, 1510 extra_flush_bits, ret); 1511 } 1512 1513 /** 1514 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1515 * @phys: Pointer to physical encoder structure 1516 */ 1517 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1518 { 1519 if (!phys) { 1520 DPU_ERROR("invalid argument(s)\n"); 1521 return; 1522 } 1523 1524 if (!phys->hw_pp) { 1525 DPU_ERROR("invalid pingpong hw\n"); 1526 return; 1527 } 1528 1529 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1530 phys->ops.trigger_start(phys); 1531 } 1532 1533 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1534 { 1535 struct dpu_hw_ctl *ctl; 1536 1537 ctl = phys_enc->hw_ctl; 1538 if (ctl->ops.trigger_start) { 1539 ctl->ops.trigger_start(ctl); 1540 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1541 } 1542 } 1543 1544 static int dpu_encoder_helper_wait_event_timeout( 1545 int32_t drm_id, 1546 unsigned int irq_idx, 1547 struct dpu_encoder_wait_info *info) 1548 { 1549 int rc = 0; 1550 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1551 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1552 s64 time; 1553 1554 do { 1555 rc = wait_event_timeout(*(info->wq), 1556 atomic_read(info->atomic_cnt) == 0, jiffies); 1557 time = ktime_to_ms(ktime_get()); 1558 1559 trace_dpu_enc_wait_event_timeout(drm_id, 1560 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1561 rc, time, 1562 expected_time, 1563 atomic_read(info->atomic_cnt)); 1564 /* If we timed out, counter is valid and time is less, wait again */ 1565 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1566 (time < expected_time)); 1567 1568 return rc; 1569 } 1570 1571 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1572 { 1573 struct dpu_encoder_virt *dpu_enc; 1574 struct dpu_hw_ctl *ctl; 1575 int rc; 1576 struct drm_encoder *drm_enc; 1577 1578 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1579 ctl = phys_enc->hw_ctl; 1580 drm_enc = phys_enc->parent; 1581 1582 if (!ctl->ops.reset) 1583 return; 1584 1585 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1586 ctl->idx); 1587 1588 rc = ctl->ops.reset(ctl); 1589 if (rc) { 1590 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1591 msm_disp_snapshot_state(drm_enc->dev); 1592 } 1593 1594 phys_enc->enable_state = DPU_ENC_ENABLED; 1595 } 1596 1597 /** 1598 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1599 * Iterate through the physical encoders and perform consolidated flush 1600 * and/or control start triggering as needed. This is done in the virtual 1601 * encoder rather than the individual physical ones in order to handle 1602 * use cases that require visibility into multiple physical encoders at 1603 * a time. 1604 * @dpu_enc: Pointer to virtual encoder structure 1605 */ 1606 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1607 { 1608 struct dpu_hw_ctl *ctl; 1609 uint32_t i, pending_flush; 1610 unsigned long lock_flags; 1611 1612 pending_flush = 0x0; 1613 1614 /* update pending counts and trigger kickoff ctl flush atomically */ 1615 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1616 1617 /* don't perform flush/start operations for slave encoders */ 1618 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1619 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1620 1621 if (phys->enable_state == DPU_ENC_DISABLED) 1622 continue; 1623 1624 ctl = phys->hw_ctl; 1625 1626 /* 1627 * This is cleared in frame_done worker, which isn't invoked 1628 * for async commits. So don't set this for async, since it'll 1629 * roll over to the next commit. 1630 */ 1631 if (phys->split_role != ENC_ROLE_SLAVE) 1632 set_bit(i, dpu_enc->frame_busy_mask); 1633 1634 if (!phys->ops.needs_single_flush || 1635 !phys->ops.needs_single_flush(phys)) 1636 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1637 else if (ctl->ops.get_pending_flush) 1638 pending_flush |= ctl->ops.get_pending_flush(ctl); 1639 } 1640 1641 /* for split flush, combine pending flush masks and send to master */ 1642 if (pending_flush && dpu_enc->cur_master) { 1643 _dpu_encoder_trigger_flush( 1644 &dpu_enc->base, 1645 dpu_enc->cur_master, 1646 pending_flush); 1647 } 1648 1649 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1650 1651 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1652 } 1653 1654 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1655 { 1656 struct dpu_encoder_virt *dpu_enc; 1657 struct dpu_encoder_phys *phys; 1658 unsigned int i; 1659 struct dpu_hw_ctl *ctl; 1660 struct msm_display_info *disp_info; 1661 1662 if (!drm_enc) { 1663 DPU_ERROR("invalid encoder\n"); 1664 return; 1665 } 1666 dpu_enc = to_dpu_encoder_virt(drm_enc); 1667 disp_info = &dpu_enc->disp_info; 1668 1669 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1670 phys = dpu_enc->phys_encs[i]; 1671 1672 ctl = phys->hw_ctl; 1673 if (ctl->ops.clear_pending_flush) 1674 ctl->ops.clear_pending_flush(ctl); 1675 1676 /* update only for command mode primary ctl */ 1677 if ((phys == dpu_enc->cur_master) && 1678 disp_info->is_cmd_mode 1679 && ctl->ops.trigger_pending) 1680 ctl->ops.trigger_pending(ctl); 1681 } 1682 } 1683 1684 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1685 struct drm_display_mode *mode) 1686 { 1687 u64 pclk_rate; 1688 u32 pclk_period; 1689 u32 line_time; 1690 1691 /* 1692 * For linetime calculation, only operate on master encoder. 1693 */ 1694 if (!dpu_enc->cur_master) 1695 return 0; 1696 1697 if (!dpu_enc->cur_master->ops.get_line_count) { 1698 DPU_ERROR("get_line_count function not defined\n"); 1699 return 0; 1700 } 1701 1702 pclk_rate = mode->clock; /* pixel clock in kHz */ 1703 if (pclk_rate == 0) { 1704 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1705 return 0; 1706 } 1707 1708 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1709 if (pclk_period == 0) { 1710 DPU_ERROR("pclk period is 0\n"); 1711 return 0; 1712 } 1713 1714 /* 1715 * Line time calculation based on Pixel clock and HTOTAL. 1716 * Final unit is in ns. 1717 */ 1718 line_time = (pclk_period * mode->htotal) / 1000; 1719 if (line_time == 0) { 1720 DPU_ERROR("line time calculation is 0\n"); 1721 return 0; 1722 } 1723 1724 DPU_DEBUG_ENC(dpu_enc, 1725 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1726 pclk_rate, pclk_period, line_time); 1727 1728 return line_time; 1729 } 1730 1731 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1732 { 1733 struct drm_display_mode *mode; 1734 struct dpu_encoder_virt *dpu_enc; 1735 u32 cur_line; 1736 u32 line_time; 1737 u32 vtotal, time_to_vsync; 1738 ktime_t cur_time; 1739 1740 dpu_enc = to_dpu_encoder_virt(drm_enc); 1741 1742 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1743 DPU_ERROR("crtc/crtc state object is NULL\n"); 1744 return -EINVAL; 1745 } 1746 mode = &drm_enc->crtc->state->adjusted_mode; 1747 1748 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1749 if (!line_time) 1750 return -EINVAL; 1751 1752 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1753 1754 vtotal = mode->vtotal; 1755 if (cur_line >= vtotal) 1756 time_to_vsync = line_time * vtotal; 1757 else 1758 time_to_vsync = line_time * (vtotal - cur_line); 1759 1760 if (time_to_vsync == 0) { 1761 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1762 vtotal); 1763 return -EINVAL; 1764 } 1765 1766 cur_time = ktime_get(); 1767 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1768 1769 DPU_DEBUG_ENC(dpu_enc, 1770 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1771 cur_line, vtotal, time_to_vsync, 1772 ktime_to_ms(cur_time), 1773 ktime_to_ms(*wakeup_time)); 1774 return 0; 1775 } 1776 1777 static u32 1778 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1779 u32 enc_ip_width) 1780 { 1781 int ssm_delay, total_pixels, soft_slice_per_enc; 1782 1783 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1784 1785 /* 1786 * minimum number of initial line pixels is a sum of: 1787 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1788 * 91 for 10 bpc) * 3 1789 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1790 * 3. the initial xmit delay 1791 * 4. total pipeline delay through the "lock step" of encoder (47) 1792 * 5. 6 additional pixels as the output of the rate buffer is 1793 * 48 bits wide 1794 */ 1795 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1796 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1797 if (soft_slice_per_enc > 1) 1798 total_pixels += (ssm_delay * 3); 1799 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1800 } 1801 1802 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1803 struct dpu_hw_dsc *hw_dsc, 1804 struct dpu_hw_pingpong *hw_pp, 1805 struct drm_dsc_config *dsc, 1806 u32 common_mode, 1807 u32 initial_lines) 1808 { 1809 if (hw_dsc->ops.dsc_config) 1810 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1811 1812 if (hw_dsc->ops.dsc_config_thresh) 1813 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 1814 1815 if (hw_pp->ops.setup_dsc) 1816 hw_pp->ops.setup_dsc(hw_pp); 1817 1818 if (hw_dsc->ops.dsc_bind_pingpong_blk) 1819 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 1820 1821 if (hw_pp->ops.enable_dsc) 1822 hw_pp->ops.enable_dsc(hw_pp); 1823 1824 if (ctl->ops.update_pending_flush_dsc) 1825 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 1826 } 1827 1828 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 1829 struct drm_dsc_config *dsc) 1830 { 1831 /* coding only for 2LM, 2enc, 1 dsc config */ 1832 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 1833 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 1834 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 1835 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 1836 int this_frame_slices; 1837 int intf_ip_w, enc_ip_w; 1838 int dsc_common_mode; 1839 int pic_width; 1840 u32 initial_lines; 1841 int i; 1842 1843 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1844 hw_pp[i] = dpu_enc->hw_pp[i]; 1845 hw_dsc[i] = dpu_enc->hw_dsc[i]; 1846 1847 if (!hw_pp[i] || !hw_dsc[i]) { 1848 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); 1849 return; 1850 } 1851 } 1852 1853 dsc_common_mode = 0; 1854 pic_width = dsc->pic_width; 1855 1856 dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; 1857 if (enc_master->intf_mode == INTF_MODE_VIDEO) 1858 dsc_common_mode |= DSC_MODE_VIDEO; 1859 1860 this_frame_slices = pic_width / dsc->slice_width; 1861 intf_ip_w = this_frame_slices * dsc->slice_width; 1862 1863 /* 1864 * dsc merge case: when using 2 encoders for the same stream, 1865 * no. of slices need to be same on both the encoders. 1866 */ 1867 enc_ip_w = intf_ip_w / 2; 1868 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 1869 1870 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1871 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 1872 dsc, dsc_common_mode, initial_lines); 1873 } 1874 1875 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1876 { 1877 struct dpu_encoder_virt *dpu_enc; 1878 struct dpu_encoder_phys *phys; 1879 bool needs_hw_reset = false; 1880 unsigned int i; 1881 1882 dpu_enc = to_dpu_encoder_virt(drm_enc); 1883 1884 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1885 1886 /* prepare for next kickoff, may include waiting on previous kickoff */ 1887 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1888 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1889 phys = dpu_enc->phys_encs[i]; 1890 if (phys->ops.prepare_for_kickoff) 1891 phys->ops.prepare_for_kickoff(phys); 1892 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1893 needs_hw_reset = true; 1894 } 1895 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1896 1897 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1898 1899 /* if any phys needs reset, reset all phys, in-order */ 1900 if (needs_hw_reset) { 1901 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1902 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1903 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1904 } 1905 } 1906 1907 if (dpu_enc->dsc) 1908 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 1909 } 1910 1911 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 1912 { 1913 struct dpu_encoder_virt *dpu_enc; 1914 unsigned int i; 1915 struct dpu_encoder_phys *phys; 1916 1917 dpu_enc = to_dpu_encoder_virt(drm_enc); 1918 1919 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 1920 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1921 phys = dpu_enc->phys_encs[i]; 1922 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 1923 DPU_DEBUG("invalid FB not kicking off\n"); 1924 return false; 1925 } 1926 } 1927 } 1928 1929 return true; 1930 } 1931 1932 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1933 { 1934 struct dpu_encoder_virt *dpu_enc; 1935 struct dpu_encoder_phys *phys; 1936 unsigned long timeout_ms; 1937 unsigned int i; 1938 1939 DPU_ATRACE_BEGIN("encoder_kickoff"); 1940 dpu_enc = to_dpu_encoder_virt(drm_enc); 1941 1942 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1943 1944 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1945 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1946 1947 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1948 mod_timer(&dpu_enc->frame_done_timer, 1949 jiffies + msecs_to_jiffies(timeout_ms)); 1950 1951 /* All phys encs are ready to go, trigger the kickoff */ 1952 _dpu_encoder_kickoff_phys(dpu_enc); 1953 1954 /* allow phys encs to handle any post-kickoff business */ 1955 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1956 phys = dpu_enc->phys_encs[i]; 1957 if (phys->ops.handle_post_kickoff) 1958 phys->ops.handle_post_kickoff(phys); 1959 } 1960 1961 DPU_ATRACE_END("encoder_kickoff"); 1962 } 1963 1964 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 1965 { 1966 struct dpu_hw_mixer_cfg mixer; 1967 int i, num_lm; 1968 struct dpu_global_state *global_state; 1969 struct dpu_hw_blk *hw_lm[2]; 1970 struct dpu_hw_mixer *hw_mixer[2]; 1971 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 1972 1973 memset(&mixer, 0, sizeof(mixer)); 1974 1975 /* reset all mixers for this encoder */ 1976 if (phys_enc->hw_ctl->ops.clear_all_blendstages) 1977 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); 1978 1979 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 1980 1981 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 1982 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1983 1984 for (i = 0; i < num_lm; i++) { 1985 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 1986 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer) 1987 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 1988 1989 /* clear all blendstages */ 1990 if (phys_enc->hw_ctl->ops.setup_blendstage) 1991 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 1992 } 1993 } 1994 1995 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 1996 struct dpu_hw_dsc *hw_dsc, 1997 struct dpu_hw_pingpong *hw_pp) 1998 { 1999 if (hw_dsc->ops.dsc_disable) 2000 hw_dsc->ops.dsc_disable(hw_dsc); 2001 2002 if (hw_pp->ops.disable_dsc) 2003 hw_pp->ops.disable_dsc(hw_pp); 2004 2005 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2006 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2007 2008 if (ctl->ops.update_pending_flush_dsc) 2009 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2010 } 2011 2012 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2013 { 2014 /* coding only for 2LM, 2enc, 1 dsc config */ 2015 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2016 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2017 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2018 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2019 int i; 2020 2021 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2022 hw_pp[i] = dpu_enc->hw_pp[i]; 2023 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2024 2025 if (hw_pp[i] && hw_dsc[i]) 2026 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2027 } 2028 } 2029 2030 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2031 { 2032 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2033 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2034 int i; 2035 struct dpu_encoder_virt *dpu_enc; 2036 2037 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2038 2039 phys_enc->hw_ctl->ops.reset(ctl); 2040 2041 dpu_encoder_helper_reset_mixers(phys_enc); 2042 2043 /* 2044 * TODO: move the once-only operation like CTL flush/trigger 2045 * into dpu_encoder_virt_disable() and all operations which need 2046 * to be done per phys encoder into the phys_disable() op. 2047 */ 2048 if (phys_enc->hw_wb) { 2049 /* disable the PP block */ 2050 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2051 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2052 2053 /* mark WB flush as pending */ 2054 if (phys_enc->hw_ctl->ops.update_pending_flush_wb) 2055 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2056 } else { 2057 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2058 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2059 phys_enc->hw_intf->ops.bind_pingpong_blk( 2060 dpu_enc->phys_encs[i]->hw_intf, 2061 PINGPONG_NONE); 2062 2063 /* mark INTF flush as pending */ 2064 if (phys_enc->hw_ctl->ops.update_pending_flush_intf) 2065 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl, 2066 dpu_enc->phys_encs[i]->hw_intf->idx); 2067 } 2068 } 2069 2070 /* reset the merge 3D HW block */ 2071 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { 2072 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2073 BLEND_3D_NONE); 2074 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d) 2075 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl, 2076 phys_enc->hw_pp->merge_3d->idx); 2077 } 2078 2079 if (phys_enc->hw_cdm) { 2080 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) 2081 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, 2082 PINGPONG_NONE); 2083 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) 2084 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, 2085 phys_enc->hw_cdm->idx); 2086 } 2087 2088 if (dpu_enc->dsc) { 2089 dpu_encoder_unprep_dsc(dpu_enc); 2090 dpu_enc->dsc = NULL; 2091 } 2092 2093 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2094 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2095 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2096 2097 if (phys_enc->hw_intf) 2098 intf_cfg.intf = phys_enc->hw_intf->idx; 2099 if (phys_enc->hw_wb) 2100 intf_cfg.wb = phys_enc->hw_wb->idx; 2101 2102 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) 2103 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2104 2105 if (ctl->ops.reset_intf_cfg) 2106 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2107 2108 ctl->ops.trigger_flush(ctl); 2109 ctl->ops.trigger_start(ctl); 2110 ctl->ops.clear_pending_flush(ctl); 2111 } 2112 2113 #ifdef CONFIG_DEBUG_FS 2114 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2115 { 2116 struct drm_encoder *drm_enc = s->private; 2117 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2118 int i; 2119 2120 mutex_lock(&dpu_enc->enc_lock); 2121 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2122 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2123 2124 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d", 2125 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2126 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2127 atomic_read(&phys->vsync_cnt), 2128 atomic_read(&phys->underrun_cnt), 2129 atomic_read(&dpu_enc->frame_done_timeout_cnt)); 2130 2131 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2132 } 2133 mutex_unlock(&dpu_enc->enc_lock); 2134 2135 return 0; 2136 } 2137 2138 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2139 2140 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root) 2141 { 2142 /* don't error check these */ 2143 debugfs_create_file("status", 0600, 2144 root, drm_enc, &_dpu_encoder_status_fops); 2145 } 2146 #else 2147 #define dpu_encoder_debugfs_init NULL 2148 #endif 2149 2150 static int dpu_encoder_virt_add_phys_encs( 2151 struct drm_device *dev, 2152 struct msm_display_info *disp_info, 2153 struct dpu_encoder_virt *dpu_enc, 2154 struct dpu_enc_phys_init_params *params) 2155 { 2156 struct dpu_encoder_phys *enc = NULL; 2157 2158 DPU_DEBUG_ENC(dpu_enc, "\n"); 2159 2160 /* 2161 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2162 * in this function, check up-front. 2163 */ 2164 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2165 ARRAY_SIZE(dpu_enc->phys_encs)) { 2166 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2167 dpu_enc->num_phys_encs); 2168 return -EINVAL; 2169 } 2170 2171 2172 if (disp_info->intf_type == INTF_WB) { 2173 enc = dpu_encoder_phys_wb_init(dev, params); 2174 2175 if (IS_ERR(enc)) { 2176 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2177 PTR_ERR(enc)); 2178 return PTR_ERR(enc); 2179 } 2180 2181 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2182 ++dpu_enc->num_phys_encs; 2183 } else if (disp_info->is_cmd_mode) { 2184 enc = dpu_encoder_phys_cmd_init(dev, params); 2185 2186 if (IS_ERR(enc)) { 2187 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2188 PTR_ERR(enc)); 2189 return PTR_ERR(enc); 2190 } 2191 2192 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2193 ++dpu_enc->num_phys_encs; 2194 } else { 2195 enc = dpu_encoder_phys_vid_init(dev, params); 2196 2197 if (IS_ERR(enc)) { 2198 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2199 PTR_ERR(enc)); 2200 return PTR_ERR(enc); 2201 } 2202 2203 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2204 ++dpu_enc->num_phys_encs; 2205 } 2206 2207 if (params->split_role == ENC_ROLE_SLAVE) 2208 dpu_enc->cur_slave = enc; 2209 else 2210 dpu_enc->cur_master = enc; 2211 2212 return 0; 2213 } 2214 2215 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2216 struct dpu_kms *dpu_kms, 2217 struct msm_display_info *disp_info) 2218 { 2219 int ret = 0; 2220 int i = 0; 2221 struct dpu_enc_phys_init_params phys_params; 2222 2223 if (!dpu_enc) { 2224 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2225 return -EINVAL; 2226 } 2227 2228 dpu_enc->cur_master = NULL; 2229 2230 memset(&phys_params, 0, sizeof(phys_params)); 2231 phys_params.dpu_kms = dpu_kms; 2232 phys_params.parent = &dpu_enc->base; 2233 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2234 2235 WARN_ON(disp_info->num_of_h_tiles < 1); 2236 2237 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2238 2239 if (disp_info->intf_type != INTF_WB) 2240 dpu_enc->idle_pc_supported = 2241 dpu_kms->catalog->caps->has_idle_pc; 2242 2243 mutex_lock(&dpu_enc->enc_lock); 2244 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2245 /* 2246 * Left-most tile is at index 0, content is controller id 2247 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2248 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2249 */ 2250 u32 controller_id = disp_info->h_tile_instance[i]; 2251 2252 if (disp_info->num_of_h_tiles > 1) { 2253 if (i == 0) 2254 phys_params.split_role = ENC_ROLE_MASTER; 2255 else 2256 phys_params.split_role = ENC_ROLE_SLAVE; 2257 } else { 2258 phys_params.split_role = ENC_ROLE_SOLO; 2259 } 2260 2261 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2262 i, controller_id, phys_params.split_role); 2263 2264 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2265 disp_info->intf_type, 2266 controller_id); 2267 2268 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2269 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2270 2271 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2272 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2273 ret = -EINVAL; 2274 break; 2275 } 2276 2277 if (phys_params.hw_intf && phys_params.hw_wb) { 2278 DPU_ERROR_ENC(dpu_enc, 2279 "invalid phys both intf and wb block at idx: %d\n", i); 2280 ret = -EINVAL; 2281 break; 2282 } 2283 2284 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, 2285 dpu_enc, &phys_params); 2286 if (ret) { 2287 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2288 break; 2289 } 2290 } 2291 2292 mutex_unlock(&dpu_enc->enc_lock); 2293 2294 return ret; 2295 } 2296 2297 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2298 { 2299 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2300 frame_done_timer); 2301 struct drm_encoder *drm_enc = &dpu_enc->base; 2302 u32 event; 2303 2304 if (!drm_enc->dev) { 2305 DPU_ERROR("invalid parameters\n"); 2306 return; 2307 } 2308 2309 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2310 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2311 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2312 return; 2313 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2314 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2315 return; 2316 } 2317 2318 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n"); 2319 2320 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1) 2321 msm_disp_snapshot_state(drm_enc->dev); 2322 2323 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2324 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2325 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2326 } 2327 2328 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2329 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2330 .atomic_disable = dpu_encoder_virt_atomic_disable, 2331 .atomic_enable = dpu_encoder_virt_atomic_enable, 2332 .atomic_check = dpu_encoder_virt_atomic_check, 2333 }; 2334 2335 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2336 .debugfs_init = dpu_encoder_debugfs_init, 2337 }; 2338 2339 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2340 int drm_enc_mode, 2341 struct msm_display_info *disp_info) 2342 { 2343 struct msm_drm_private *priv = dev->dev_private; 2344 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2345 struct dpu_encoder_virt *dpu_enc; 2346 int ret; 2347 2348 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base, 2349 &dpu_encoder_funcs, drm_enc_mode, NULL); 2350 if (IS_ERR(dpu_enc)) 2351 return ERR_CAST(dpu_enc); 2352 2353 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2354 2355 spin_lock_init(&dpu_enc->enc_spinlock); 2356 dpu_enc->enabled = false; 2357 mutex_init(&dpu_enc->enc_lock); 2358 mutex_init(&dpu_enc->rc_lock); 2359 2360 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2361 if (ret) { 2362 DPU_ERROR("failed to setup encoder\n"); 2363 return ERR_PTR(-ENOMEM); 2364 } 2365 2366 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2367 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 2368 timer_setup(&dpu_enc->frame_done_timer, 2369 dpu_encoder_frame_done_timeout, 0); 2370 2371 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2372 dpu_encoder_off_work); 2373 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2374 2375 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2376 2377 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2378 2379 return &dpu_enc->base; 2380 } 2381 2382 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2383 enum msm_event_wait event) 2384 { 2385 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2386 struct dpu_encoder_virt *dpu_enc = NULL; 2387 int i, ret = 0; 2388 2389 if (!drm_enc) { 2390 DPU_ERROR("invalid encoder\n"); 2391 return -EINVAL; 2392 } 2393 dpu_enc = to_dpu_encoder_virt(drm_enc); 2394 DPU_DEBUG_ENC(dpu_enc, "\n"); 2395 2396 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2397 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2398 2399 switch (event) { 2400 case MSM_ENC_COMMIT_DONE: 2401 fn_wait = phys->ops.wait_for_commit_done; 2402 break; 2403 case MSM_ENC_TX_COMPLETE: 2404 fn_wait = phys->ops.wait_for_tx_complete; 2405 break; 2406 default: 2407 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2408 event); 2409 return -EINVAL; 2410 } 2411 2412 if (fn_wait) { 2413 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2414 ret = fn_wait(phys); 2415 DPU_ATRACE_END("wait_for_completion_event"); 2416 if (ret) 2417 return ret; 2418 } 2419 } 2420 2421 return ret; 2422 } 2423 2424 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2425 { 2426 struct dpu_encoder_virt *dpu_enc = NULL; 2427 2428 if (!encoder) { 2429 DPU_ERROR("invalid encoder\n"); 2430 return INTF_MODE_NONE; 2431 } 2432 dpu_enc = to_dpu_encoder_virt(encoder); 2433 2434 if (dpu_enc->cur_master) 2435 return dpu_enc->cur_master->intf_mode; 2436 2437 if (dpu_enc->num_phys_encs) 2438 return dpu_enc->phys_encs[0]->intf_mode; 2439 2440 return INTF_MODE_NONE; 2441 } 2442 2443 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2444 { 2445 struct drm_encoder *encoder = phys_enc->parent; 2446 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2447 2448 return dpu_enc->dsc_mask; 2449 } 2450 2451 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2452 struct dpu_enc_phys_init_params *p) 2453 { 2454 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2455 phys_enc->hw_intf = p->hw_intf; 2456 phys_enc->hw_wb = p->hw_wb; 2457 phys_enc->parent = p->parent; 2458 phys_enc->dpu_kms = p->dpu_kms; 2459 phys_enc->split_role = p->split_role; 2460 phys_enc->enc_spinlock = p->enc_spinlock; 2461 phys_enc->enable_state = DPU_ENC_DISABLED; 2462 2463 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2464 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2465 2466 atomic_set(&phys_enc->vsync_cnt, 0); 2467 atomic_set(&phys_enc->underrun_cnt, 0); 2468 2469 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2470 } 2471