1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_framebuffer.h> 20 21 #include "msm_drv.h" 22 #include "dpu_kms.h" 23 #include "dpu_hwio.h" 24 #include "dpu_hw_catalog.h" 25 #include "dpu_hw_intf.h" 26 #include "dpu_hw_ctl.h" 27 #include "dpu_hw_dspp.h" 28 #include "dpu_hw_dsc.h" 29 #include "dpu_hw_merge3d.h" 30 #include "dpu_hw_cdm.h" 31 #include "dpu_formats.h" 32 #include "dpu_encoder_phys.h" 33 #include "dpu_crtc.h" 34 #include "dpu_trace.h" 35 #include "dpu_core_irq.h" 36 #include "disp/msm_disp_snapshot.h" 37 38 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 40 41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 43 44 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\ 45 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 46 47 /* 48 * Two to anticipate panels that can do cmd/vid dynamic switching 49 * plan is to create all possible physical encoder types, and switch between 50 * them at runtime 51 */ 52 #define NUM_PHYS_ENCODER_TYPES 2 53 54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 56 57 #define MAX_CHANNELS_PER_ENC 2 58 59 #define IDLE_SHORT_TIMEOUT 1 60 61 #define MAX_HDISPLAY_SPLIT 1080 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @enabled: True if the encoder is active, protected by enc_lock 129 * @commit_done_timedout: True if there has been a timeout on commit after 130 * enabling the encoder. 131 * @num_phys_encs: Actual number of physical encoders contained. 132 * @phys_encs: Container of physical encoders managed. 133 * @cur_master: Pointer to the current master in this mode. Optimization 134 * Only valid after enable. Cleared as disable. 135 * @cur_slave: As above but for the slave encoder. 136 * @hw_pp: Handle to the pingpong blocks used for the display. No. 137 * pingpong blocks can be different than num_phys_encs. 138 * @hw_dsc: Handle to the DSC blocks used for the display. 139 * @dsc_mask: Bitmask of used DSC blocks. 140 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 141 * for partial update right-only cases, such as pingpong 142 * split where virtual pingpong does not generate IRQs 143 * @crtc: Pointer to the currently assigned crtc. Normally you 144 * would use crtc->state->encoder_mask to determine the 145 * link between encoder/crtc. However in this case we need 146 * to track crtc in the disable() hook which is called 147 * _after_ encoder_mask is cleared. 148 * @connector: If a mode is set, cached pointer to the active connector 149 * @enc_lock: Lock around physical encoder 150 * create/destroy/enable/disable 151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 152 * busy processing current command. 153 * Bit0 = phys_encs[0] etc. 154 * @frame_done_timeout_ms: frame done timeout in ms 155 * @frame_done_timeout_cnt: atomic counter tracking the number of frame 156 * done timeouts 157 * @frame_done_timer: watchdog timer for frame done event 158 * @disp_info: local copy of msm_display_info struct 159 * @idle_pc_supported: indicate if idle power collaps is supported 160 * @rc_lock: resource control mutex lock to protect 161 * virt encoder over various state changes 162 * @rc_state: resource controller state 163 * @delayed_off_work: delayed worker to schedule disabling of 164 * clks and resources after IDLE_TIMEOUT time. 165 * @topology: topology of the display 166 * @idle_timeout: idle timeout duration in milliseconds 167 * @wide_bus_en: wide bus is enabled on this interface 168 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 169 */ 170 struct dpu_encoder_virt { 171 struct drm_encoder base; 172 spinlock_t enc_spinlock; 173 174 bool enabled; 175 bool commit_done_timedout; 176 177 unsigned int num_phys_encs; 178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 179 struct dpu_encoder_phys *cur_master; 180 struct dpu_encoder_phys *cur_slave; 181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 182 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 183 184 unsigned int dsc_mask; 185 186 bool intfs_swapped; 187 188 struct drm_crtc *crtc; 189 struct drm_connector *connector; 190 191 struct mutex enc_lock; 192 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 193 194 atomic_t frame_done_timeout_ms; 195 atomic_t frame_done_timeout_cnt; 196 struct timer_list frame_done_timer; 197 198 struct msm_display_info disp_info; 199 200 bool idle_pc_supported; 201 struct mutex rc_lock; 202 enum dpu_enc_rc_states rc_state; 203 struct delayed_work delayed_off_work; 204 struct msm_display_topology topology; 205 206 u32 idle_timeout; 207 208 bool wide_bus_en; 209 210 /* DSC configuration */ 211 struct drm_dsc_config *dsc; 212 }; 213 214 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 215 216 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 217 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 218 }; 219 220 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) 221 { 222 struct drm_encoder *drm_enc; 223 struct dpu_encoder_virt *dpu_enc; 224 struct drm_display_info *info; 225 struct drm_display_mode *mode; 226 227 drm_enc = phys_enc->parent; 228 dpu_enc = to_dpu_encoder_virt(drm_enc); 229 info = &dpu_enc->connector->display_info; 230 mode = &phys_enc->cached_mode; 231 232 if (drm_mode_is_420_only(info, mode)) 233 return DRM_FORMAT_YUV420; 234 235 return DRM_FORMAT_RGB888; 236 } 237 238 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) 239 { 240 struct drm_encoder *drm_enc; 241 struct dpu_encoder_virt *dpu_enc; 242 struct msm_display_info *disp_info; 243 struct msm_drm_private *priv; 244 struct drm_display_mode *mode; 245 246 drm_enc = phys_enc->parent; 247 dpu_enc = to_dpu_encoder_virt(drm_enc); 248 disp_info = &dpu_enc->disp_info; 249 priv = drm_enc->dev->dev_private; 250 mode = &phys_enc->cached_mode; 251 252 return phys_enc->hw_intf->cap->type == INTF_DP && 253 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode); 254 } 255 256 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 257 { 258 const struct dpu_encoder_virt *dpu_enc; 259 struct msm_drm_private *priv = drm_enc->dev->dev_private; 260 const struct msm_display_info *disp_info; 261 int index; 262 263 dpu_enc = to_dpu_encoder_virt(drm_enc); 264 disp_info = &dpu_enc->disp_info; 265 index = disp_info->h_tile_instance[0]; 266 267 if (disp_info->intf_type == INTF_DP) 268 return msm_dp_wide_bus_available(priv->dp[index]); 269 else if (disp_info->intf_type == INTF_DSI) 270 return msm_dsi_wide_bus_enabled(priv->dsi[index]); 271 272 return false; 273 } 274 275 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) 276 { 277 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 278 279 return dpu_enc->dsc ? true : false; 280 } 281 282 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 283 { 284 struct dpu_encoder_virt *dpu_enc; 285 int i, num_intf = 0; 286 287 dpu_enc = to_dpu_encoder_virt(drm_enc); 288 289 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 290 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 291 292 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 293 && phys->hw_intf->ops.collect_misr) 294 num_intf++; 295 } 296 297 return num_intf; 298 } 299 300 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 301 { 302 struct dpu_encoder_virt *dpu_enc; 303 304 int i; 305 306 dpu_enc = to_dpu_encoder_virt(drm_enc); 307 308 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 309 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 310 311 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 312 continue; 313 314 phys->hw_intf->ops.setup_misr(phys->hw_intf); 315 } 316 } 317 318 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 319 { 320 struct dpu_encoder_virt *dpu_enc; 321 322 int i, rc = 0, entries_added = 0; 323 324 if (!drm_enc->crtc) { 325 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 326 return -EINVAL; 327 } 328 329 dpu_enc = to_dpu_encoder_virt(drm_enc); 330 331 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 332 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 333 334 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 335 continue; 336 337 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 338 if (rc) 339 return rc; 340 entries_added++; 341 } 342 343 return entries_added; 344 } 345 346 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 347 { 348 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 349 350 if (!hw_pp->ops.setup_dither) 351 return; 352 353 switch (bpc) { 354 case 6: 355 dither_cfg.c0_bitdepth = 6; 356 dither_cfg.c1_bitdepth = 6; 357 dither_cfg.c2_bitdepth = 6; 358 dither_cfg.c3_bitdepth = 6; 359 dither_cfg.temporal_en = 0; 360 break; 361 default: 362 hw_pp->ops.setup_dither(hw_pp, NULL); 363 return; 364 } 365 366 memcpy(&dither_cfg.matrix, dither_matrix, 367 sizeof(u32) * DITHER_MATRIX_SZ); 368 369 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 370 } 371 372 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 373 { 374 switch (intf_mode) { 375 case INTF_MODE_VIDEO: 376 return "INTF_MODE_VIDEO"; 377 case INTF_MODE_CMD: 378 return "INTF_MODE_CMD"; 379 case INTF_MODE_WB_BLOCK: 380 return "INTF_MODE_WB_BLOCK"; 381 case INTF_MODE_WB_LINE: 382 return "INTF_MODE_WB_LINE"; 383 default: 384 return "INTF_MODE_UNKNOWN"; 385 } 386 } 387 388 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 389 enum dpu_intr_idx intr_idx) 390 { 391 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 392 DRMID(phys_enc->parent), 393 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 394 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 395 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 396 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 397 398 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 399 DPU_ENCODER_FRAME_EVENT_ERROR); 400 } 401 402 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 403 u32 irq_idx, struct dpu_encoder_wait_info *info); 404 405 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 406 unsigned int irq_idx, 407 void (*func)(void *arg), 408 struct dpu_encoder_wait_info *wait_info) 409 { 410 u32 irq_status; 411 int ret; 412 413 if (!wait_info) { 414 DPU_ERROR("invalid params\n"); 415 return -EINVAL; 416 } 417 /* note: do master / slave checking outside */ 418 419 /* return EWOULDBLOCK since we know the wait isn't necessary */ 420 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 421 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 422 DRMID(phys_enc->parent), func, 423 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 424 return -EWOULDBLOCK; 425 } 426 427 if (irq_idx == 0) { 428 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 429 DRMID(phys_enc->parent), func); 430 return 0; 431 } 432 433 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 434 DRMID(phys_enc->parent), func, 435 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 436 atomic_read(wait_info->atomic_cnt)); 437 438 ret = dpu_encoder_helper_wait_event_timeout( 439 DRMID(phys_enc->parent), 440 irq_idx, 441 wait_info); 442 443 if (ret <= 0) { 444 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 445 if (irq_status) { 446 unsigned long flags; 447 448 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 449 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 450 DRMID(phys_enc->parent), func, 451 phys_enc->hw_pp->idx - PINGPONG_0, 452 atomic_read(wait_info->atomic_cnt)); 453 local_irq_save(flags); 454 func(phys_enc); 455 local_irq_restore(flags); 456 ret = 0; 457 } else { 458 ret = -ETIMEDOUT; 459 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 460 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 461 DRMID(phys_enc->parent), func, 462 phys_enc->hw_pp->idx - PINGPONG_0, 463 atomic_read(wait_info->atomic_cnt)); 464 } 465 } else { 466 ret = 0; 467 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 468 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 469 phys_enc->hw_pp->idx - PINGPONG_0, 470 atomic_read(wait_info->atomic_cnt)); 471 } 472 473 return ret; 474 } 475 476 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 477 { 478 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 479 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 480 return phys ? atomic_read(&phys->vsync_cnt) : 0; 481 } 482 483 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 484 { 485 struct dpu_encoder_virt *dpu_enc; 486 struct dpu_encoder_phys *phys; 487 int linecount = 0; 488 489 dpu_enc = to_dpu_encoder_virt(drm_enc); 490 phys = dpu_enc ? dpu_enc->cur_master : NULL; 491 492 if (phys && phys->ops.get_line_count) 493 linecount = phys->ops.get_line_count(phys); 494 495 return linecount; 496 } 497 498 void dpu_encoder_helper_split_config( 499 struct dpu_encoder_phys *phys_enc, 500 enum dpu_intf interface) 501 { 502 struct dpu_encoder_virt *dpu_enc; 503 struct split_pipe_cfg cfg = { 0 }; 504 struct dpu_hw_mdp *hw_mdptop; 505 struct msm_display_info *disp_info; 506 507 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 508 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 509 return; 510 } 511 512 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 513 hw_mdptop = phys_enc->hw_mdptop; 514 disp_info = &dpu_enc->disp_info; 515 516 if (disp_info->intf_type != INTF_DSI) 517 return; 518 519 /** 520 * disable split modes since encoder will be operating in as the only 521 * encoder, either for the entire use case in the case of, for example, 522 * single DSI, or for this frame in the case of left/right only partial 523 * update. 524 */ 525 if (phys_enc->split_role == ENC_ROLE_SOLO) { 526 if (hw_mdptop->ops.setup_split_pipe) 527 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 528 return; 529 } 530 531 cfg.en = true; 532 cfg.mode = phys_enc->intf_mode; 533 cfg.intf = interface; 534 535 if (cfg.en && phys_enc->ops.needs_single_flush && 536 phys_enc->ops.needs_single_flush(phys_enc)) 537 cfg.split_flush_en = true; 538 539 if (phys_enc->split_role == ENC_ROLE_MASTER) { 540 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 541 542 if (hw_mdptop->ops.setup_split_pipe) 543 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 544 } 545 } 546 547 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 548 { 549 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 550 int i, intf_count = 0, num_dsc = 0; 551 552 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 553 if (dpu_enc->phys_encs[i]) 554 intf_count++; 555 556 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ 557 if (dpu_enc->dsc) 558 num_dsc = 2; 559 560 return (num_dsc > 0) && (num_dsc > intf_count); 561 } 562 563 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 564 { 565 struct msm_drm_private *priv = drm_enc->dev->dev_private; 566 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 567 int index = dpu_enc->disp_info.h_tile_instance[0]; 568 569 if (dpu_enc->disp_info.intf_type == INTF_DSI) 570 return msm_dsi_get_dsc_config(priv->dsi[index]); 571 572 return NULL; 573 } 574 575 static struct msm_display_topology dpu_encoder_get_topology( 576 struct dpu_encoder_virt *dpu_enc, 577 struct dpu_kms *dpu_kms, 578 struct drm_display_mode *mode, 579 struct drm_crtc_state *crtc_state, 580 struct drm_dsc_config *dsc) 581 { 582 struct msm_display_topology topology = {0}; 583 int i, intf_count = 0; 584 585 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 586 if (dpu_enc->phys_encs[i]) 587 intf_count++; 588 589 /* Datapath topology selection 590 * 591 * Dual display 592 * 2 LM, 2 INTF ( Split display using 2 interfaces) 593 * 594 * Single display 595 * 1 LM, 1 INTF 596 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 597 * 598 * Add dspps to the reservation requirements if ctm is requested 599 */ 600 if (intf_count == 2) 601 topology.num_lm = 2; 602 else if (!dpu_kms->catalog->caps->has_3d_merge) 603 topology.num_lm = 1; 604 else 605 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 606 607 if (crtc_state->ctm) 608 topology.num_dspp = topology.num_lm; 609 610 topology.num_intf = intf_count; 611 612 if (dsc) { 613 /* 614 * In case of Display Stream Compression (DSC), we would use 615 * 2 DSC encoders, 2 layer mixers and 1 interface 616 * this is power optimal and can drive up to (including) 4k 617 * screens 618 */ 619 topology.num_dsc = 2; 620 topology.num_lm = 2; 621 topology.num_intf = 1; 622 } 623 624 return topology; 625 } 626 627 static void dpu_encoder_assign_crtc_resources(struct dpu_kms *dpu_kms, 628 struct drm_encoder *drm_enc, 629 struct dpu_global_state *global_state, 630 struct drm_crtc_state *crtc_state) 631 { 632 struct dpu_crtc_state *cstate; 633 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 634 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 635 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC]; 636 int num_lm, num_ctl, num_dspp, i; 637 638 cstate = to_dpu_crtc_state(crtc_state); 639 640 memset(cstate->mixers, 0, sizeof(cstate->mixers)); 641 642 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 643 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 644 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 645 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 646 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 647 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 648 ARRAY_SIZE(hw_dspp)); 649 650 for (i = 0; i < num_lm; i++) { 651 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 652 653 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 654 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 655 cstate->mixers[i].hw_dspp = i < num_dspp ? to_dpu_hw_dspp(hw_dspp[i]) : NULL; 656 } 657 658 cstate->num_mixers = num_lm; 659 } 660 661 static int dpu_encoder_virt_atomic_check( 662 struct drm_encoder *drm_enc, 663 struct drm_crtc_state *crtc_state, 664 struct drm_connector_state *conn_state) 665 { 666 struct dpu_encoder_virt *dpu_enc; 667 struct msm_drm_private *priv; 668 struct dpu_kms *dpu_kms; 669 struct drm_display_mode *adj_mode; 670 struct msm_display_topology topology; 671 struct msm_display_info *disp_info; 672 struct dpu_global_state *global_state; 673 struct drm_framebuffer *fb; 674 struct drm_dsc_config *dsc; 675 int ret = 0; 676 677 if (!drm_enc || !crtc_state || !conn_state) { 678 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 679 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 680 return -EINVAL; 681 } 682 683 dpu_enc = to_dpu_encoder_virt(drm_enc); 684 DPU_DEBUG_ENC(dpu_enc, "\n"); 685 686 priv = drm_enc->dev->dev_private; 687 disp_info = &dpu_enc->disp_info; 688 dpu_kms = to_dpu_kms(priv->kms); 689 adj_mode = &crtc_state->adjusted_mode; 690 global_state = dpu_kms_get_global_state(crtc_state->state); 691 if (IS_ERR(global_state)) 692 return PTR_ERR(global_state); 693 694 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 695 696 dsc = dpu_encoder_get_dsc_config(drm_enc); 697 698 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); 699 700 /* 701 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. 702 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() 703 * earlier. 704 */ 705 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { 706 fb = conn_state->writeback_job->fb; 707 708 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) 709 topology.needs_cdm = true; 710 } else if (disp_info->intf_type == INTF_DP) { 711 if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) 712 topology.needs_cdm = true; 713 } 714 715 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) 716 crtc_state->mode_changed = true; 717 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) 718 crtc_state->mode_changed = true; 719 /* 720 * Release and Allocate resources on every modeset 721 * Dont allocate when active is false. 722 */ 723 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 724 dpu_rm_release(global_state, drm_enc); 725 726 if (!crtc_state->active_changed || crtc_state->enable) 727 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 728 drm_enc, crtc_state, topology); 729 if (!ret) 730 dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc, 731 global_state, crtc_state); 732 } 733 734 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 735 736 return ret; 737 } 738 739 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 740 struct msm_display_info *disp_info) 741 { 742 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 743 struct msm_drm_private *priv; 744 struct dpu_kms *dpu_kms; 745 struct dpu_hw_mdp *hw_mdptop; 746 struct drm_encoder *drm_enc; 747 struct dpu_encoder_phys *phys_enc; 748 int i; 749 750 if (!dpu_enc || !disp_info) { 751 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 752 dpu_enc != NULL, disp_info != NULL); 753 return; 754 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 755 DPU_ERROR("invalid num phys enc %d/%d\n", 756 dpu_enc->num_phys_encs, 757 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 758 return; 759 } 760 761 drm_enc = &dpu_enc->base; 762 /* this pointers are checked in virt_enable_helper */ 763 priv = drm_enc->dev->dev_private; 764 765 dpu_kms = to_dpu_kms(priv->kms); 766 hw_mdptop = dpu_kms->hw_mdp; 767 if (!hw_mdptop) { 768 DPU_ERROR("invalid mdptop\n"); 769 return; 770 } 771 772 if (hw_mdptop->ops.setup_vsync_source) { 773 for (i = 0; i < dpu_enc->num_phys_encs; i++) 774 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 775 776 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 777 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 778 779 vsync_cfg.vsync_source = disp_info->vsync_source; 780 781 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 782 783 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 784 phys_enc = dpu_enc->phys_encs[i]; 785 786 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 787 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 788 vsync_cfg.vsync_source); 789 } 790 } 791 } 792 793 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) 794 { 795 struct dpu_encoder_virt *dpu_enc; 796 int i; 797 798 if (!drm_enc) { 799 DPU_ERROR("invalid encoder\n"); 800 return; 801 } 802 803 dpu_enc = to_dpu_encoder_virt(drm_enc); 804 805 DPU_DEBUG_ENC(dpu_enc, "\n"); 806 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 807 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 808 809 phys->ops.irq_enable(phys); 810 } 811 } 812 813 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) 814 { 815 struct dpu_encoder_virt *dpu_enc; 816 int i; 817 818 if (!drm_enc) { 819 DPU_ERROR("invalid encoder\n"); 820 return; 821 } 822 823 dpu_enc = to_dpu_encoder_virt(drm_enc); 824 825 DPU_DEBUG_ENC(dpu_enc, "\n"); 826 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 827 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 828 829 phys->ops.irq_disable(phys); 830 } 831 } 832 833 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc) 834 { 835 struct msm_drm_private *priv; 836 struct dpu_kms *dpu_kms; 837 struct dpu_encoder_virt *dpu_enc; 838 839 dpu_enc = to_dpu_encoder_virt(drm_enc); 840 priv = drm_enc->dev->dev_private; 841 dpu_kms = to_dpu_kms(priv->kms); 842 843 trace_dpu_enc_rc_enable(DRMID(drm_enc)); 844 845 if (!dpu_enc->cur_master) { 846 DPU_ERROR("encoder master not set\n"); 847 return; 848 } 849 850 /* enable DPU core clks */ 851 pm_runtime_get_sync(&dpu_kms->pdev->dev); 852 853 /* enable all the irq */ 854 _dpu_encoder_irq_enable(drm_enc); 855 } 856 857 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc) 858 { 859 struct msm_drm_private *priv; 860 struct dpu_kms *dpu_kms; 861 struct dpu_encoder_virt *dpu_enc; 862 863 dpu_enc = to_dpu_encoder_virt(drm_enc); 864 priv = drm_enc->dev->dev_private; 865 dpu_kms = to_dpu_kms(priv->kms); 866 867 trace_dpu_enc_rc_disable(DRMID(drm_enc)); 868 869 if (!dpu_enc->cur_master) { 870 DPU_ERROR("encoder master not set\n"); 871 return; 872 } 873 874 /* disable all the irq */ 875 _dpu_encoder_irq_disable(drm_enc); 876 877 /* disable DPU core clks */ 878 pm_runtime_put_sync(&dpu_kms->pdev->dev); 879 } 880 881 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 882 u32 sw_event) 883 { 884 struct dpu_encoder_virt *dpu_enc; 885 struct msm_drm_private *priv; 886 bool is_vid_mode = false; 887 888 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 889 DPU_ERROR("invalid parameters\n"); 890 return -EINVAL; 891 } 892 dpu_enc = to_dpu_encoder_virt(drm_enc); 893 priv = drm_enc->dev->dev_private; 894 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 895 896 /* 897 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 898 * events and return early for other events (ie wb display). 899 */ 900 if (!dpu_enc->idle_pc_supported && 901 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 902 sw_event != DPU_ENC_RC_EVENT_STOP && 903 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 904 return 0; 905 906 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 907 dpu_enc->rc_state, "begin"); 908 909 switch (sw_event) { 910 case DPU_ENC_RC_EVENT_KICKOFF: 911 /* cancel delayed off work, if any */ 912 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 913 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 914 sw_event); 915 916 mutex_lock(&dpu_enc->rc_lock); 917 918 /* return if the resource control is already in ON state */ 919 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 920 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 921 DRMID(drm_enc), sw_event); 922 mutex_unlock(&dpu_enc->rc_lock); 923 return 0; 924 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 925 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 926 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 927 DRMID(drm_enc), sw_event, 928 dpu_enc->rc_state); 929 mutex_unlock(&dpu_enc->rc_lock); 930 return -EINVAL; 931 } 932 933 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 934 _dpu_encoder_irq_enable(drm_enc); 935 else 936 _dpu_encoder_resource_enable(drm_enc); 937 938 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 939 940 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 941 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 942 "kickoff"); 943 944 mutex_unlock(&dpu_enc->rc_lock); 945 break; 946 947 case DPU_ENC_RC_EVENT_FRAME_DONE: 948 /* 949 * mutex lock is not used as this event happens at interrupt 950 * context. And locking is not required as, the other events 951 * like KICKOFF and STOP does a wait-for-idle before executing 952 * the resource_control 953 */ 954 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 955 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 956 DRMID(drm_enc), sw_event, 957 dpu_enc->rc_state); 958 return -EINVAL; 959 } 960 961 /* 962 * schedule off work item only when there are no 963 * frames pending 964 */ 965 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 966 DRM_DEBUG_KMS("id:%d skip schedule work\n", 967 DRMID(drm_enc)); 968 return 0; 969 } 970 971 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 972 msecs_to_jiffies(dpu_enc->idle_timeout)); 973 974 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 975 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 976 "frame done"); 977 break; 978 979 case DPU_ENC_RC_EVENT_PRE_STOP: 980 /* cancel delayed off work, if any */ 981 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 982 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 983 sw_event); 984 985 mutex_lock(&dpu_enc->rc_lock); 986 987 if (is_vid_mode && 988 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 989 _dpu_encoder_irq_enable(drm_enc); 990 } 991 /* skip if is already OFF or IDLE, resources are off already */ 992 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 993 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 994 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 995 DRMID(drm_enc), sw_event, 996 dpu_enc->rc_state); 997 mutex_unlock(&dpu_enc->rc_lock); 998 return 0; 999 } 1000 1001 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 1002 1003 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1004 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1005 "pre stop"); 1006 1007 mutex_unlock(&dpu_enc->rc_lock); 1008 break; 1009 1010 case DPU_ENC_RC_EVENT_STOP: 1011 mutex_lock(&dpu_enc->rc_lock); 1012 1013 /* return if the resource control is already in OFF state */ 1014 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 1015 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 1016 DRMID(drm_enc), sw_event); 1017 mutex_unlock(&dpu_enc->rc_lock); 1018 return 0; 1019 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 1020 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 1021 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1022 mutex_unlock(&dpu_enc->rc_lock); 1023 return -EINVAL; 1024 } 1025 1026 /** 1027 * expect to arrive here only if in either idle state or pre-off 1028 * and in IDLE state the resources are already disabled 1029 */ 1030 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 1031 _dpu_encoder_resource_disable(drm_enc); 1032 1033 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 1034 1035 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1036 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1037 "stop"); 1038 1039 mutex_unlock(&dpu_enc->rc_lock); 1040 break; 1041 1042 case DPU_ENC_RC_EVENT_ENTER_IDLE: 1043 mutex_lock(&dpu_enc->rc_lock); 1044 1045 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 1046 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 1047 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1048 mutex_unlock(&dpu_enc->rc_lock); 1049 return 0; 1050 } 1051 1052 /* 1053 * if we are in ON but a frame was just kicked off, 1054 * ignore the IDLE event, it's probably a stale timer event 1055 */ 1056 if (dpu_enc->frame_busy_mask[0]) { 1057 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 1058 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1059 mutex_unlock(&dpu_enc->rc_lock); 1060 return 0; 1061 } 1062 1063 if (is_vid_mode) 1064 _dpu_encoder_irq_disable(drm_enc); 1065 else 1066 _dpu_encoder_resource_disable(drm_enc); 1067 1068 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 1069 1070 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1071 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1072 "idle"); 1073 1074 mutex_unlock(&dpu_enc->rc_lock); 1075 break; 1076 1077 default: 1078 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 1079 sw_event); 1080 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1081 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1082 "error"); 1083 break; 1084 } 1085 1086 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1087 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1088 "end"); 1089 return 0; 1090 } 1091 1092 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1093 struct drm_writeback_job *job) 1094 { 1095 struct dpu_encoder_virt *dpu_enc; 1096 int i; 1097 1098 dpu_enc = to_dpu_encoder_virt(drm_enc); 1099 1100 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1101 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1102 1103 if (phys->ops.prepare_wb_job) 1104 phys->ops.prepare_wb_job(phys, job); 1105 1106 } 1107 } 1108 1109 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1110 struct drm_writeback_job *job) 1111 { 1112 struct dpu_encoder_virt *dpu_enc; 1113 int i; 1114 1115 dpu_enc = to_dpu_encoder_virt(drm_enc); 1116 1117 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1118 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1119 1120 if (phys->ops.cleanup_wb_job) 1121 phys->ops.cleanup_wb_job(phys, job); 1122 1123 } 1124 } 1125 1126 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1127 struct drm_crtc_state *crtc_state, 1128 struct drm_connector_state *conn_state) 1129 { 1130 struct dpu_encoder_virt *dpu_enc; 1131 struct msm_drm_private *priv; 1132 struct dpu_kms *dpu_kms; 1133 struct dpu_global_state *global_state; 1134 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1135 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1136 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1137 int num_ctl, num_pp, num_dsc; 1138 unsigned int dsc_mask = 0; 1139 int i; 1140 1141 if (!drm_enc) { 1142 DPU_ERROR("invalid encoder\n"); 1143 return; 1144 } 1145 1146 dpu_enc = to_dpu_encoder_virt(drm_enc); 1147 DPU_DEBUG_ENC(dpu_enc, "\n"); 1148 1149 priv = drm_enc->dev->dev_private; 1150 dpu_kms = to_dpu_kms(priv->kms); 1151 1152 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1153 if (IS_ERR_OR_NULL(global_state)) { 1154 DPU_ERROR("Failed to get global state"); 1155 return; 1156 } 1157 1158 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1159 1160 /* Query resource that have been reserved in atomic check step. */ 1161 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1162 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1163 ARRAY_SIZE(hw_pp)); 1164 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1165 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1166 1167 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1168 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1169 : NULL; 1170 1171 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1172 drm_enc->base.id, DPU_HW_BLK_DSC, 1173 hw_dsc, ARRAY_SIZE(hw_dsc)); 1174 for (i = 0; i < num_dsc; i++) { 1175 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1176 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1177 } 1178 1179 dpu_enc->dsc_mask = dsc_mask; 1180 1181 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || 1182 dpu_enc->disp_info.intf_type == INTF_DP) { 1183 struct dpu_hw_blk *hw_cdm = NULL; 1184 1185 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1186 drm_enc->base.id, DPU_HW_BLK_CDM, 1187 &hw_cdm, 1); 1188 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1189 } 1190 1191 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1192 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1193 1194 phys->hw_pp = dpu_enc->hw_pp[i]; 1195 if (!phys->hw_pp) { 1196 DPU_ERROR_ENC(dpu_enc, 1197 "no pp block assigned at idx: %d\n", i); 1198 return; 1199 } 1200 1201 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; 1202 if (!phys->hw_ctl) { 1203 DPU_ERROR_ENC(dpu_enc, 1204 "no ctl block assigned at idx: %d\n", i); 1205 return; 1206 } 1207 1208 phys->cached_mode = crtc_state->adjusted_mode; 1209 if (phys->ops.atomic_mode_set) 1210 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1211 } 1212 } 1213 1214 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1215 { 1216 struct dpu_encoder_virt *dpu_enc = NULL; 1217 int i; 1218 1219 if (!drm_enc || !drm_enc->dev) { 1220 DPU_ERROR("invalid parameters\n"); 1221 return; 1222 } 1223 1224 dpu_enc = to_dpu_encoder_virt(drm_enc); 1225 if (!dpu_enc || !dpu_enc->cur_master) { 1226 DPU_ERROR("invalid dpu encoder/master\n"); 1227 return; 1228 } 1229 1230 1231 if (dpu_enc->disp_info.intf_type == INTF_DP && 1232 dpu_enc->cur_master->hw_mdptop && 1233 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1234 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1235 dpu_enc->cur_master->hw_mdptop); 1236 1237 if (dpu_enc->disp_info.is_cmd_mode) 1238 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1239 1240 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1241 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1242 unsigned bpc = dpu_enc->connector->display_info.bpc; 1243 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1244 if (!dpu_enc->hw_pp[i]) 1245 continue; 1246 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1247 } 1248 } 1249 } 1250 1251 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1252 { 1253 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1254 1255 mutex_lock(&dpu_enc->enc_lock); 1256 1257 if (!dpu_enc->enabled) 1258 goto out; 1259 1260 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1261 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1262 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1263 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1264 1265 _dpu_encoder_virt_enable_helper(drm_enc); 1266 1267 out: 1268 mutex_unlock(&dpu_enc->enc_lock); 1269 } 1270 1271 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1272 struct drm_atomic_state *state) 1273 { 1274 struct dpu_encoder_virt *dpu_enc = NULL; 1275 int ret = 0; 1276 struct drm_display_mode *cur_mode = NULL; 1277 1278 dpu_enc = to_dpu_encoder_virt(drm_enc); 1279 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1280 1281 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 1282 1283 mutex_lock(&dpu_enc->enc_lock); 1284 1285 dpu_enc->commit_done_timedout = false; 1286 1287 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 1288 1289 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1290 1291 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc); 1292 1293 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1294 cur_mode->vdisplay); 1295 1296 /* always enable slave encoder before master */ 1297 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1298 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1299 1300 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1301 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1302 1303 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1304 if (ret) { 1305 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1306 ret); 1307 goto out; 1308 } 1309 1310 _dpu_encoder_virt_enable_helper(drm_enc); 1311 1312 dpu_enc->enabled = true; 1313 1314 out: 1315 mutex_unlock(&dpu_enc->enc_lock); 1316 } 1317 1318 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1319 struct drm_atomic_state *state) 1320 { 1321 struct dpu_encoder_virt *dpu_enc = NULL; 1322 struct drm_crtc *crtc; 1323 struct drm_crtc_state *old_state = NULL; 1324 int i = 0; 1325 1326 dpu_enc = to_dpu_encoder_virt(drm_enc); 1327 DPU_DEBUG_ENC(dpu_enc, "\n"); 1328 1329 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1330 if (crtc) 1331 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1332 1333 /* 1334 * The encoder is already disabled if self refresh mode was set earlier, 1335 * in the old_state for the corresponding crtc. 1336 */ 1337 if (old_state && old_state->self_refresh_active) 1338 return; 1339 1340 mutex_lock(&dpu_enc->enc_lock); 1341 dpu_enc->enabled = false; 1342 1343 trace_dpu_enc_disable(DRMID(drm_enc)); 1344 1345 /* wait for idle */ 1346 dpu_encoder_wait_for_tx_complete(drm_enc); 1347 1348 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1349 1350 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1351 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1352 1353 if (phys->ops.disable) 1354 phys->ops.disable(phys); 1355 } 1356 1357 1358 /* after phys waits for frame-done, should be no more frames pending */ 1359 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1360 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1361 del_timer_sync(&dpu_enc->frame_done_timer); 1362 } 1363 1364 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1365 1366 dpu_enc->connector = NULL; 1367 1368 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1369 1370 mutex_unlock(&dpu_enc->enc_lock); 1371 } 1372 1373 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1374 struct dpu_rm *dpu_rm, 1375 enum dpu_intf_type type, u32 controller_id) 1376 { 1377 int i = 0; 1378 1379 if (type == INTF_WB) 1380 return NULL; 1381 1382 for (i = 0; i < catalog->intf_count; i++) { 1383 if (catalog->intf[i].type == type 1384 && catalog->intf[i].controller_id == controller_id) { 1385 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1386 } 1387 } 1388 1389 return NULL; 1390 } 1391 1392 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1393 struct dpu_encoder_phys *phy_enc) 1394 { 1395 struct dpu_encoder_virt *dpu_enc = NULL; 1396 unsigned long lock_flags; 1397 1398 if (!drm_enc || !phy_enc) 1399 return; 1400 1401 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1402 dpu_enc = to_dpu_encoder_virt(drm_enc); 1403 1404 atomic_inc(&phy_enc->vsync_cnt); 1405 1406 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1407 if (dpu_enc->crtc) 1408 dpu_crtc_vblank_callback(dpu_enc->crtc); 1409 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1410 1411 DPU_ATRACE_END("encoder_vblank_callback"); 1412 } 1413 1414 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1415 struct dpu_encoder_phys *phy_enc) 1416 { 1417 if (!phy_enc) 1418 return; 1419 1420 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1421 atomic_inc(&phy_enc->underrun_cnt); 1422 1423 /* trigger dump only on the first underrun */ 1424 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1425 msm_disp_snapshot_state(drm_enc->dev); 1426 1427 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1428 atomic_read(&phy_enc->underrun_cnt)); 1429 DPU_ATRACE_END("encoder_underrun_callback"); 1430 } 1431 1432 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1433 { 1434 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1435 unsigned long lock_flags; 1436 1437 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1438 /* crtc should always be cleared before re-assigning */ 1439 WARN_ON(crtc && dpu_enc->crtc); 1440 dpu_enc->crtc = crtc; 1441 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1442 } 1443 1444 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1445 struct drm_crtc *crtc, bool enable) 1446 { 1447 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1448 unsigned long lock_flags; 1449 int i; 1450 1451 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1452 1453 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1454 if (dpu_enc->crtc != crtc) { 1455 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1456 return; 1457 } 1458 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1459 1460 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1461 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1462 1463 if (phys->ops.control_vblank_irq) 1464 phys->ops.control_vblank_irq(phys, enable); 1465 } 1466 } 1467 1468 void dpu_encoder_frame_done_callback( 1469 struct drm_encoder *drm_enc, 1470 struct dpu_encoder_phys *ready_phys, u32 event) 1471 { 1472 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1473 unsigned int i; 1474 1475 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1476 | DPU_ENCODER_FRAME_EVENT_ERROR 1477 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1478 1479 if (!dpu_enc->frame_busy_mask[0]) { 1480 /** 1481 * suppress frame_done without waiter, 1482 * likely autorefresh 1483 */ 1484 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1485 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1486 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1487 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1488 return; 1489 } 1490 1491 /* One of the physical encoders has become idle */ 1492 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1493 if (dpu_enc->phys_encs[i] == ready_phys) { 1494 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1495 dpu_enc->frame_busy_mask[0]); 1496 clear_bit(i, dpu_enc->frame_busy_mask); 1497 } 1498 } 1499 1500 if (!dpu_enc->frame_busy_mask[0]) { 1501 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1502 del_timer(&dpu_enc->frame_done_timer); 1503 1504 dpu_encoder_resource_control(drm_enc, 1505 DPU_ENC_RC_EVENT_FRAME_DONE); 1506 1507 if (dpu_enc->crtc) 1508 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1509 } 1510 } else { 1511 if (dpu_enc->crtc) 1512 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1513 } 1514 } 1515 1516 static void dpu_encoder_off_work(struct work_struct *work) 1517 { 1518 struct dpu_encoder_virt *dpu_enc = container_of(work, 1519 struct dpu_encoder_virt, delayed_off_work.work); 1520 1521 dpu_encoder_resource_control(&dpu_enc->base, 1522 DPU_ENC_RC_EVENT_ENTER_IDLE); 1523 1524 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1525 DPU_ENCODER_FRAME_EVENT_IDLE); 1526 } 1527 1528 /** 1529 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1530 * @drm_enc: Pointer to drm encoder structure 1531 * @phys: Pointer to physical encoder structure 1532 * @extra_flush_bits: Additional bit mask to include in flush trigger 1533 */ 1534 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1535 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1536 { 1537 struct dpu_hw_ctl *ctl; 1538 int pending_kickoff_cnt; 1539 u32 ret = UINT_MAX; 1540 1541 if (!phys->hw_pp) { 1542 DPU_ERROR("invalid pingpong hw\n"); 1543 return; 1544 } 1545 1546 ctl = phys->hw_ctl; 1547 if (!ctl->ops.trigger_flush) { 1548 DPU_ERROR("missing trigger cb\n"); 1549 return; 1550 } 1551 1552 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1553 1554 if (extra_flush_bits && ctl->ops.update_pending_flush) 1555 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1556 1557 ctl->ops.trigger_flush(ctl); 1558 1559 if (ctl->ops.get_pending_flush) 1560 ret = ctl->ops.get_pending_flush(ctl); 1561 1562 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1563 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1564 phys->hw_intf ? phys->hw_intf->idx : -1, 1565 phys->hw_wb ? phys->hw_wb->idx : -1, 1566 pending_kickoff_cnt, ctl->idx, 1567 extra_flush_bits, ret); 1568 } 1569 1570 /** 1571 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1572 * @phys: Pointer to physical encoder structure 1573 */ 1574 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1575 { 1576 if (!phys) { 1577 DPU_ERROR("invalid argument(s)\n"); 1578 return; 1579 } 1580 1581 if (!phys->hw_pp) { 1582 DPU_ERROR("invalid pingpong hw\n"); 1583 return; 1584 } 1585 1586 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1587 phys->ops.trigger_start(phys); 1588 } 1589 1590 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1591 { 1592 struct dpu_hw_ctl *ctl; 1593 1594 ctl = phys_enc->hw_ctl; 1595 if (ctl->ops.trigger_start) { 1596 ctl->ops.trigger_start(ctl); 1597 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1598 } 1599 } 1600 1601 static int dpu_encoder_helper_wait_event_timeout( 1602 int32_t drm_id, 1603 unsigned int irq_idx, 1604 struct dpu_encoder_wait_info *info) 1605 { 1606 int rc = 0; 1607 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1608 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1609 s64 time; 1610 1611 do { 1612 rc = wait_event_timeout(*(info->wq), 1613 atomic_read(info->atomic_cnt) == 0, jiffies); 1614 time = ktime_to_ms(ktime_get()); 1615 1616 trace_dpu_enc_wait_event_timeout(drm_id, 1617 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1618 rc, time, 1619 expected_time, 1620 atomic_read(info->atomic_cnt)); 1621 /* If we timed out, counter is valid and time is less, wait again */ 1622 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1623 (time < expected_time)); 1624 1625 return rc; 1626 } 1627 1628 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1629 { 1630 struct dpu_encoder_virt *dpu_enc; 1631 struct dpu_hw_ctl *ctl; 1632 int rc; 1633 struct drm_encoder *drm_enc; 1634 1635 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1636 ctl = phys_enc->hw_ctl; 1637 drm_enc = phys_enc->parent; 1638 1639 if (!ctl->ops.reset) 1640 return; 1641 1642 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1643 ctl->idx); 1644 1645 rc = ctl->ops.reset(ctl); 1646 if (rc) { 1647 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1648 msm_disp_snapshot_state(drm_enc->dev); 1649 } 1650 1651 phys_enc->enable_state = DPU_ENC_ENABLED; 1652 } 1653 1654 /** 1655 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1656 * Iterate through the physical encoders and perform consolidated flush 1657 * and/or control start triggering as needed. This is done in the virtual 1658 * encoder rather than the individual physical ones in order to handle 1659 * use cases that require visibility into multiple physical encoders at 1660 * a time. 1661 * @dpu_enc: Pointer to virtual encoder structure 1662 */ 1663 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1664 { 1665 struct dpu_hw_ctl *ctl; 1666 uint32_t i, pending_flush; 1667 unsigned long lock_flags; 1668 1669 pending_flush = 0x0; 1670 1671 /* update pending counts and trigger kickoff ctl flush atomically */ 1672 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1673 1674 /* don't perform flush/start operations for slave encoders */ 1675 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1676 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1677 1678 if (phys->enable_state == DPU_ENC_DISABLED) 1679 continue; 1680 1681 ctl = phys->hw_ctl; 1682 1683 /* 1684 * This is cleared in frame_done worker, which isn't invoked 1685 * for async commits. So don't set this for async, since it'll 1686 * roll over to the next commit. 1687 */ 1688 if (phys->split_role != ENC_ROLE_SLAVE) 1689 set_bit(i, dpu_enc->frame_busy_mask); 1690 1691 if (!phys->ops.needs_single_flush || 1692 !phys->ops.needs_single_flush(phys)) 1693 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1694 else if (ctl->ops.get_pending_flush) 1695 pending_flush |= ctl->ops.get_pending_flush(ctl); 1696 } 1697 1698 /* for split flush, combine pending flush masks and send to master */ 1699 if (pending_flush && dpu_enc->cur_master) { 1700 _dpu_encoder_trigger_flush( 1701 &dpu_enc->base, 1702 dpu_enc->cur_master, 1703 pending_flush); 1704 } 1705 1706 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1707 1708 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1709 } 1710 1711 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1712 { 1713 struct dpu_encoder_virt *dpu_enc; 1714 struct dpu_encoder_phys *phys; 1715 unsigned int i; 1716 struct dpu_hw_ctl *ctl; 1717 struct msm_display_info *disp_info; 1718 1719 if (!drm_enc) { 1720 DPU_ERROR("invalid encoder\n"); 1721 return; 1722 } 1723 dpu_enc = to_dpu_encoder_virt(drm_enc); 1724 disp_info = &dpu_enc->disp_info; 1725 1726 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1727 phys = dpu_enc->phys_encs[i]; 1728 1729 ctl = phys->hw_ctl; 1730 ctl->ops.clear_pending_flush(ctl); 1731 1732 /* update only for command mode primary ctl */ 1733 if ((phys == dpu_enc->cur_master) && 1734 disp_info->is_cmd_mode 1735 && ctl->ops.trigger_pending) 1736 ctl->ops.trigger_pending(ctl); 1737 } 1738 } 1739 1740 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1741 struct drm_display_mode *mode) 1742 { 1743 u64 pclk_rate; 1744 u32 pclk_period; 1745 u32 line_time; 1746 1747 /* 1748 * For linetime calculation, only operate on master encoder. 1749 */ 1750 if (!dpu_enc->cur_master) 1751 return 0; 1752 1753 if (!dpu_enc->cur_master->ops.get_line_count) { 1754 DPU_ERROR("get_line_count function not defined\n"); 1755 return 0; 1756 } 1757 1758 pclk_rate = mode->clock; /* pixel clock in kHz */ 1759 if (pclk_rate == 0) { 1760 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1761 return 0; 1762 } 1763 1764 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1765 if (pclk_period == 0) { 1766 DPU_ERROR("pclk period is 0\n"); 1767 return 0; 1768 } 1769 1770 /* 1771 * Line time calculation based on Pixel clock and HTOTAL. 1772 * Final unit is in ns. 1773 */ 1774 line_time = (pclk_period * mode->htotal) / 1000; 1775 if (line_time == 0) { 1776 DPU_ERROR("line time calculation is 0\n"); 1777 return 0; 1778 } 1779 1780 DPU_DEBUG_ENC(dpu_enc, 1781 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1782 pclk_rate, pclk_period, line_time); 1783 1784 return line_time; 1785 } 1786 1787 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1788 { 1789 struct drm_display_mode *mode; 1790 struct dpu_encoder_virt *dpu_enc; 1791 u32 cur_line; 1792 u32 line_time; 1793 u32 vtotal, time_to_vsync; 1794 ktime_t cur_time; 1795 1796 dpu_enc = to_dpu_encoder_virt(drm_enc); 1797 1798 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1799 DPU_ERROR("crtc/crtc state object is NULL\n"); 1800 return -EINVAL; 1801 } 1802 mode = &drm_enc->crtc->state->adjusted_mode; 1803 1804 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1805 if (!line_time) 1806 return -EINVAL; 1807 1808 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1809 1810 vtotal = mode->vtotal; 1811 if (cur_line >= vtotal) 1812 time_to_vsync = line_time * vtotal; 1813 else 1814 time_to_vsync = line_time * (vtotal - cur_line); 1815 1816 if (time_to_vsync == 0) { 1817 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1818 vtotal); 1819 return -EINVAL; 1820 } 1821 1822 cur_time = ktime_get(); 1823 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1824 1825 DPU_DEBUG_ENC(dpu_enc, 1826 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1827 cur_line, vtotal, time_to_vsync, 1828 ktime_to_ms(cur_time), 1829 ktime_to_ms(*wakeup_time)); 1830 return 0; 1831 } 1832 1833 static u32 1834 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1835 u32 enc_ip_width) 1836 { 1837 int ssm_delay, total_pixels, soft_slice_per_enc; 1838 1839 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1840 1841 /* 1842 * minimum number of initial line pixels is a sum of: 1843 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1844 * 91 for 10 bpc) * 3 1845 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1846 * 3. the initial xmit delay 1847 * 4. total pipeline delay through the "lock step" of encoder (47) 1848 * 5. 6 additional pixels as the output of the rate buffer is 1849 * 48 bits wide 1850 */ 1851 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1852 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1853 if (soft_slice_per_enc > 1) 1854 total_pixels += (ssm_delay * 3); 1855 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1856 } 1857 1858 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1859 struct dpu_hw_dsc *hw_dsc, 1860 struct dpu_hw_pingpong *hw_pp, 1861 struct drm_dsc_config *dsc, 1862 u32 common_mode, 1863 u32 initial_lines) 1864 { 1865 if (hw_dsc->ops.dsc_config) 1866 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1867 1868 if (hw_dsc->ops.dsc_config_thresh) 1869 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 1870 1871 if (hw_pp->ops.setup_dsc) 1872 hw_pp->ops.setup_dsc(hw_pp); 1873 1874 if (hw_dsc->ops.dsc_bind_pingpong_blk) 1875 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 1876 1877 if (hw_pp->ops.enable_dsc) 1878 hw_pp->ops.enable_dsc(hw_pp); 1879 1880 if (ctl->ops.update_pending_flush_dsc) 1881 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 1882 } 1883 1884 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 1885 struct drm_dsc_config *dsc) 1886 { 1887 /* coding only for 2LM, 2enc, 1 dsc config */ 1888 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 1889 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 1890 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 1891 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 1892 int this_frame_slices; 1893 int intf_ip_w, enc_ip_w; 1894 int dsc_common_mode; 1895 int pic_width; 1896 u32 initial_lines; 1897 int i; 1898 1899 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1900 hw_pp[i] = dpu_enc->hw_pp[i]; 1901 hw_dsc[i] = dpu_enc->hw_dsc[i]; 1902 1903 if (!hw_pp[i] || !hw_dsc[i]) { 1904 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); 1905 return; 1906 } 1907 } 1908 1909 dsc_common_mode = 0; 1910 pic_width = dsc->pic_width; 1911 1912 dsc_common_mode = DSC_MODE_SPLIT_PANEL; 1913 if (dpu_encoder_use_dsc_merge(enc_master->parent)) 1914 dsc_common_mode |= DSC_MODE_MULTIPLEX; 1915 if (enc_master->intf_mode == INTF_MODE_VIDEO) 1916 dsc_common_mode |= DSC_MODE_VIDEO; 1917 1918 this_frame_slices = pic_width / dsc->slice_width; 1919 intf_ip_w = this_frame_slices * dsc->slice_width; 1920 1921 /* 1922 * dsc merge case: when using 2 encoders for the same stream, 1923 * no. of slices need to be same on both the encoders. 1924 */ 1925 enc_ip_w = intf_ip_w / 2; 1926 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 1927 1928 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1929 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 1930 dsc, dsc_common_mode, initial_lines); 1931 } 1932 1933 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1934 { 1935 struct dpu_encoder_virt *dpu_enc; 1936 struct dpu_encoder_phys *phys; 1937 bool needs_hw_reset = false; 1938 unsigned int i; 1939 1940 dpu_enc = to_dpu_encoder_virt(drm_enc); 1941 1942 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1943 1944 /* prepare for next kickoff, may include waiting on previous kickoff */ 1945 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1946 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1947 phys = dpu_enc->phys_encs[i]; 1948 if (phys->ops.prepare_for_kickoff) 1949 phys->ops.prepare_for_kickoff(phys); 1950 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1951 needs_hw_reset = true; 1952 } 1953 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1954 1955 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1956 1957 /* if any phys needs reset, reset all phys, in-order */ 1958 if (needs_hw_reset) { 1959 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1960 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1961 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1962 } 1963 } 1964 1965 if (dpu_enc->dsc) 1966 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 1967 } 1968 1969 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 1970 { 1971 struct dpu_encoder_virt *dpu_enc; 1972 unsigned int i; 1973 struct dpu_encoder_phys *phys; 1974 1975 dpu_enc = to_dpu_encoder_virt(drm_enc); 1976 1977 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 1978 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1979 phys = dpu_enc->phys_encs[i]; 1980 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 1981 DPU_DEBUG("invalid FB not kicking off\n"); 1982 return false; 1983 } 1984 } 1985 } 1986 1987 return true; 1988 } 1989 1990 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1991 { 1992 struct dpu_encoder_virt *dpu_enc; 1993 struct dpu_encoder_phys *phys; 1994 unsigned long timeout_ms; 1995 unsigned int i; 1996 1997 DPU_ATRACE_BEGIN("encoder_kickoff"); 1998 dpu_enc = to_dpu_encoder_virt(drm_enc); 1999 2000 trace_dpu_enc_kickoff(DRMID(drm_enc)); 2001 2002 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 2003 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 2004 2005 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 2006 mod_timer(&dpu_enc->frame_done_timer, 2007 jiffies + msecs_to_jiffies(timeout_ms)); 2008 2009 /* All phys encs are ready to go, trigger the kickoff */ 2010 _dpu_encoder_kickoff_phys(dpu_enc); 2011 2012 /* allow phys encs to handle any post-kickoff business */ 2013 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2014 phys = dpu_enc->phys_encs[i]; 2015 if (phys->ops.handle_post_kickoff) 2016 phys->ops.handle_post_kickoff(phys); 2017 } 2018 2019 DPU_ATRACE_END("encoder_kickoff"); 2020 } 2021 2022 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 2023 { 2024 struct dpu_hw_mixer_cfg mixer; 2025 int i, num_lm; 2026 struct dpu_global_state *global_state; 2027 struct dpu_hw_blk *hw_lm[2]; 2028 struct dpu_hw_mixer *hw_mixer[2]; 2029 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2030 2031 memset(&mixer, 0, sizeof(mixer)); 2032 2033 /* reset all mixers for this encoder */ 2034 if (phys_enc->hw_ctl->ops.clear_all_blendstages) 2035 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); 2036 2037 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 2038 2039 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 2040 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 2041 2042 for (i = 0; i < num_lm; i++) { 2043 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 2044 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer) 2045 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 2046 2047 /* clear all blendstages */ 2048 if (phys_enc->hw_ctl->ops.setup_blendstage) 2049 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 2050 } 2051 } 2052 2053 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 2054 struct dpu_hw_dsc *hw_dsc, 2055 struct dpu_hw_pingpong *hw_pp) 2056 { 2057 if (hw_dsc->ops.dsc_disable) 2058 hw_dsc->ops.dsc_disable(hw_dsc); 2059 2060 if (hw_pp->ops.disable_dsc) 2061 hw_pp->ops.disable_dsc(hw_pp); 2062 2063 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2064 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2065 2066 if (ctl->ops.update_pending_flush_dsc) 2067 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2068 } 2069 2070 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2071 { 2072 /* coding only for 2LM, 2enc, 1 dsc config */ 2073 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2074 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2075 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2076 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2077 int i; 2078 2079 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2080 hw_pp[i] = dpu_enc->hw_pp[i]; 2081 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2082 2083 if (hw_pp[i] && hw_dsc[i]) 2084 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2085 } 2086 } 2087 2088 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2089 { 2090 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2091 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2092 int i; 2093 struct dpu_encoder_virt *dpu_enc; 2094 2095 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2096 2097 phys_enc->hw_ctl->ops.reset(ctl); 2098 2099 dpu_encoder_helper_reset_mixers(phys_enc); 2100 2101 /* 2102 * TODO: move the once-only operation like CTL flush/trigger 2103 * into dpu_encoder_virt_disable() and all operations which need 2104 * to be done per phys encoder into the phys_disable() op. 2105 */ 2106 if (phys_enc->hw_wb) { 2107 /* disable the PP block */ 2108 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2109 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2110 2111 /* mark WB flush as pending */ 2112 if (phys_enc->hw_ctl->ops.update_pending_flush_wb) 2113 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2114 } else { 2115 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2116 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2117 phys_enc->hw_intf->ops.bind_pingpong_blk( 2118 dpu_enc->phys_encs[i]->hw_intf, 2119 PINGPONG_NONE); 2120 2121 /* mark INTF flush as pending */ 2122 if (phys_enc->hw_ctl->ops.update_pending_flush_intf) 2123 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl, 2124 dpu_enc->phys_encs[i]->hw_intf->idx); 2125 } 2126 } 2127 2128 /* reset the merge 3D HW block */ 2129 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { 2130 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2131 BLEND_3D_NONE); 2132 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d) 2133 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl, 2134 phys_enc->hw_pp->merge_3d->idx); 2135 } 2136 2137 if (phys_enc->hw_cdm) { 2138 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) 2139 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, 2140 PINGPONG_NONE); 2141 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) 2142 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, 2143 phys_enc->hw_cdm->idx); 2144 } 2145 2146 if (dpu_enc->dsc) { 2147 dpu_encoder_unprep_dsc(dpu_enc); 2148 dpu_enc->dsc = NULL; 2149 } 2150 2151 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2152 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2153 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2154 2155 if (phys_enc->hw_intf) 2156 intf_cfg.intf = phys_enc->hw_intf->idx; 2157 if (phys_enc->hw_wb) 2158 intf_cfg.wb = phys_enc->hw_wb->idx; 2159 2160 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) 2161 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2162 2163 if (ctl->ops.reset_intf_cfg) 2164 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2165 2166 ctl->ops.trigger_flush(ctl); 2167 ctl->ops.trigger_start(ctl); 2168 ctl->ops.clear_pending_flush(ctl); 2169 } 2170 2171 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 2172 const struct msm_format *dpu_fmt, 2173 u32 output_type) 2174 { 2175 struct dpu_hw_cdm *hw_cdm; 2176 struct dpu_hw_cdm_cfg *cdm_cfg; 2177 struct dpu_hw_pingpong *hw_pp; 2178 int ret; 2179 2180 if (!phys_enc) 2181 return; 2182 2183 cdm_cfg = &phys_enc->cdm_cfg; 2184 hw_pp = phys_enc->hw_pp; 2185 hw_cdm = phys_enc->hw_cdm; 2186 2187 if (!hw_cdm) 2188 return; 2189 2190 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) { 2191 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), 2192 &dpu_fmt->pixel_format); 2193 if (hw_cdm->ops.bind_pingpong_blk) 2194 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); 2195 2196 return; 2197 } 2198 2199 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); 2200 2201 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; 2202 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; 2203 cdm_cfg->output_fmt = dpu_fmt; 2204 cdm_cfg->output_type = output_type; 2205 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ? 2206 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; 2207 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; 2208 2209 /* enable 10 bit logic */ 2210 switch (cdm_cfg->output_fmt->chroma_sample) { 2211 case CHROMA_FULL: 2212 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2213 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2214 break; 2215 case CHROMA_H2V1: 2216 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2217 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2218 break; 2219 case CHROMA_420: 2220 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2221 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; 2222 break; 2223 case CHROMA_H1V2: 2224 default: 2225 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", 2226 DRMID(phys_enc->parent)); 2227 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2228 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2229 break; 2230 } 2231 2232 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n", 2233 DRMID(phys_enc->parent), cdm_cfg->output_width, 2234 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format, 2235 cdm_cfg->output_type, cdm_cfg->output_bit_depth, 2236 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); 2237 2238 if (hw_cdm->ops.enable) { 2239 cdm_cfg->pp_id = hw_pp->idx; 2240 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg); 2241 if (ret < 0) { 2242 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n", 2243 DRMID(phys_enc->parent), ret); 2244 return; 2245 } 2246 } 2247 } 2248 2249 #ifdef CONFIG_DEBUG_FS 2250 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2251 { 2252 struct drm_encoder *drm_enc = s->private; 2253 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2254 int i; 2255 2256 mutex_lock(&dpu_enc->enc_lock); 2257 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2258 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2259 2260 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d", 2261 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2262 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2263 atomic_read(&phys->vsync_cnt), 2264 atomic_read(&phys->underrun_cnt), 2265 atomic_read(&dpu_enc->frame_done_timeout_cnt)); 2266 2267 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2268 } 2269 mutex_unlock(&dpu_enc->enc_lock); 2270 2271 return 0; 2272 } 2273 2274 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2275 2276 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root) 2277 { 2278 /* don't error check these */ 2279 debugfs_create_file("status", 0600, 2280 root, drm_enc, &_dpu_encoder_status_fops); 2281 } 2282 #else 2283 #define dpu_encoder_debugfs_init NULL 2284 #endif 2285 2286 static int dpu_encoder_virt_add_phys_encs( 2287 struct drm_device *dev, 2288 struct msm_display_info *disp_info, 2289 struct dpu_encoder_virt *dpu_enc, 2290 struct dpu_enc_phys_init_params *params) 2291 { 2292 struct dpu_encoder_phys *enc = NULL; 2293 2294 DPU_DEBUG_ENC(dpu_enc, "\n"); 2295 2296 /* 2297 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2298 * in this function, check up-front. 2299 */ 2300 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2301 ARRAY_SIZE(dpu_enc->phys_encs)) { 2302 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2303 dpu_enc->num_phys_encs); 2304 return -EINVAL; 2305 } 2306 2307 2308 if (disp_info->intf_type == INTF_WB) { 2309 enc = dpu_encoder_phys_wb_init(dev, params); 2310 2311 if (IS_ERR(enc)) { 2312 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2313 PTR_ERR(enc)); 2314 return PTR_ERR(enc); 2315 } 2316 2317 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2318 ++dpu_enc->num_phys_encs; 2319 } else if (disp_info->is_cmd_mode) { 2320 enc = dpu_encoder_phys_cmd_init(dev, params); 2321 2322 if (IS_ERR(enc)) { 2323 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2324 PTR_ERR(enc)); 2325 return PTR_ERR(enc); 2326 } 2327 2328 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2329 ++dpu_enc->num_phys_encs; 2330 } else { 2331 enc = dpu_encoder_phys_vid_init(dev, params); 2332 2333 if (IS_ERR(enc)) { 2334 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2335 PTR_ERR(enc)); 2336 return PTR_ERR(enc); 2337 } 2338 2339 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2340 ++dpu_enc->num_phys_encs; 2341 } 2342 2343 if (params->split_role == ENC_ROLE_SLAVE) 2344 dpu_enc->cur_slave = enc; 2345 else 2346 dpu_enc->cur_master = enc; 2347 2348 return 0; 2349 } 2350 2351 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2352 struct dpu_kms *dpu_kms, 2353 struct msm_display_info *disp_info) 2354 { 2355 int ret = 0; 2356 int i = 0; 2357 struct dpu_enc_phys_init_params phys_params; 2358 2359 if (!dpu_enc) { 2360 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2361 return -EINVAL; 2362 } 2363 2364 dpu_enc->cur_master = NULL; 2365 2366 memset(&phys_params, 0, sizeof(phys_params)); 2367 phys_params.dpu_kms = dpu_kms; 2368 phys_params.parent = &dpu_enc->base; 2369 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2370 2371 WARN_ON(disp_info->num_of_h_tiles < 1); 2372 2373 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2374 2375 if (disp_info->intf_type != INTF_WB) 2376 dpu_enc->idle_pc_supported = 2377 dpu_kms->catalog->caps->has_idle_pc; 2378 2379 mutex_lock(&dpu_enc->enc_lock); 2380 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2381 /* 2382 * Left-most tile is at index 0, content is controller id 2383 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2384 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2385 */ 2386 u32 controller_id = disp_info->h_tile_instance[i]; 2387 2388 if (disp_info->num_of_h_tiles > 1) { 2389 if (i == 0) 2390 phys_params.split_role = ENC_ROLE_MASTER; 2391 else 2392 phys_params.split_role = ENC_ROLE_SLAVE; 2393 } else { 2394 phys_params.split_role = ENC_ROLE_SOLO; 2395 } 2396 2397 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2398 i, controller_id, phys_params.split_role); 2399 2400 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2401 disp_info->intf_type, 2402 controller_id); 2403 2404 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2405 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2406 2407 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2408 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2409 ret = -EINVAL; 2410 break; 2411 } 2412 2413 if (phys_params.hw_intf && phys_params.hw_wb) { 2414 DPU_ERROR_ENC(dpu_enc, 2415 "invalid phys both intf and wb block at idx: %d\n", i); 2416 ret = -EINVAL; 2417 break; 2418 } 2419 2420 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, 2421 dpu_enc, &phys_params); 2422 if (ret) { 2423 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2424 break; 2425 } 2426 } 2427 2428 mutex_unlock(&dpu_enc->enc_lock); 2429 2430 return ret; 2431 } 2432 2433 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2434 { 2435 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2436 frame_done_timer); 2437 struct drm_encoder *drm_enc = &dpu_enc->base; 2438 u32 event; 2439 2440 if (!drm_enc->dev) { 2441 DPU_ERROR("invalid parameters\n"); 2442 return; 2443 } 2444 2445 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) { 2446 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2447 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2448 return; 2449 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2450 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2451 return; 2452 } 2453 2454 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n"); 2455 2456 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1) 2457 msm_disp_snapshot_state(drm_enc->dev); 2458 2459 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2460 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2461 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 2462 } 2463 2464 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2465 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2466 .atomic_disable = dpu_encoder_virt_atomic_disable, 2467 .atomic_enable = dpu_encoder_virt_atomic_enable, 2468 .atomic_check = dpu_encoder_virt_atomic_check, 2469 }; 2470 2471 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2472 .debugfs_init = dpu_encoder_debugfs_init, 2473 }; 2474 2475 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2476 int drm_enc_mode, 2477 struct msm_display_info *disp_info) 2478 { 2479 struct msm_drm_private *priv = dev->dev_private; 2480 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2481 struct dpu_encoder_virt *dpu_enc; 2482 int ret; 2483 2484 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base, 2485 &dpu_encoder_funcs, drm_enc_mode, NULL); 2486 if (IS_ERR(dpu_enc)) 2487 return ERR_CAST(dpu_enc); 2488 2489 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2490 2491 spin_lock_init(&dpu_enc->enc_spinlock); 2492 dpu_enc->enabled = false; 2493 mutex_init(&dpu_enc->enc_lock); 2494 mutex_init(&dpu_enc->rc_lock); 2495 2496 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2497 if (ret) { 2498 DPU_ERROR("failed to setup encoder\n"); 2499 return ERR_PTR(-ENOMEM); 2500 } 2501 2502 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2503 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 2504 timer_setup(&dpu_enc->frame_done_timer, 2505 dpu_encoder_frame_done_timeout, 0); 2506 2507 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2508 dpu_encoder_off_work); 2509 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2510 2511 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2512 2513 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2514 2515 return &dpu_enc->base; 2516 } 2517 2518 /** 2519 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state 2520 * @drm_enc: encoder pointer 2521 * 2522 * Wait for hardware to have flushed the current pending changes to hardware at 2523 * a vblank or CTL_START. Physical encoders will map this differently depending 2524 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. 2525 * 2526 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2527 */ 2528 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) 2529 { 2530 struct dpu_encoder_virt *dpu_enc = NULL; 2531 int i, ret = 0; 2532 2533 if (!drm_enc) { 2534 DPU_ERROR("invalid encoder\n"); 2535 return -EINVAL; 2536 } 2537 dpu_enc = to_dpu_encoder_virt(drm_enc); 2538 DPU_DEBUG_ENC(dpu_enc, "\n"); 2539 2540 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2541 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2542 2543 if (phys->ops.wait_for_commit_done) { 2544 DPU_ATRACE_BEGIN("wait_for_commit_done"); 2545 ret = phys->ops.wait_for_commit_done(phys); 2546 DPU_ATRACE_END("wait_for_commit_done"); 2547 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { 2548 dpu_enc->commit_done_timedout = true; 2549 msm_disp_snapshot_state(drm_enc->dev); 2550 } 2551 if (ret) 2552 return ret; 2553 } 2554 } 2555 2556 return ret; 2557 } 2558 2559 /** 2560 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel 2561 * @drm_enc: encoder pointer 2562 * 2563 * Wait for the hardware to transfer all the pixels to the panel. Physical 2564 * encoders will map this differently depending on the type: vid mode -> vsync_irq, 2565 * cmd mode -> pp_done. 2566 * 2567 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2568 */ 2569 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) 2570 { 2571 struct dpu_encoder_virt *dpu_enc = NULL; 2572 int i, ret = 0; 2573 2574 if (!drm_enc) { 2575 DPU_ERROR("invalid encoder\n"); 2576 return -EINVAL; 2577 } 2578 dpu_enc = to_dpu_encoder_virt(drm_enc); 2579 DPU_DEBUG_ENC(dpu_enc, "\n"); 2580 2581 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2582 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2583 2584 if (phys->ops.wait_for_tx_complete) { 2585 DPU_ATRACE_BEGIN("wait_for_tx_complete"); 2586 ret = phys->ops.wait_for_tx_complete(phys); 2587 DPU_ATRACE_END("wait_for_tx_complete"); 2588 if (ret) 2589 return ret; 2590 } 2591 } 2592 2593 return ret; 2594 } 2595 2596 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2597 { 2598 struct dpu_encoder_virt *dpu_enc = NULL; 2599 2600 if (!encoder) { 2601 DPU_ERROR("invalid encoder\n"); 2602 return INTF_MODE_NONE; 2603 } 2604 dpu_enc = to_dpu_encoder_virt(encoder); 2605 2606 if (dpu_enc->cur_master) 2607 return dpu_enc->cur_master->intf_mode; 2608 2609 if (dpu_enc->num_phys_encs) 2610 return dpu_enc->phys_encs[0]->intf_mode; 2611 2612 return INTF_MODE_NONE; 2613 } 2614 2615 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2616 { 2617 struct drm_encoder *encoder = phys_enc->parent; 2618 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2619 2620 return dpu_enc->dsc_mask; 2621 } 2622 2623 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2624 struct dpu_enc_phys_init_params *p) 2625 { 2626 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2627 phys_enc->hw_intf = p->hw_intf; 2628 phys_enc->hw_wb = p->hw_wb; 2629 phys_enc->parent = p->parent; 2630 phys_enc->dpu_kms = p->dpu_kms; 2631 phys_enc->split_role = p->split_role; 2632 phys_enc->enc_spinlock = p->enc_spinlock; 2633 phys_enc->enable_state = DPU_ENC_DISABLED; 2634 2635 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2636 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2637 2638 atomic_set(&phys_enc->vsync_cnt, 0); 2639 atomic_set(&phys_enc->underrun_cnt, 0); 2640 2641 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2642 } 2643