1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_hwio.h" 23 #include "dpu_hw_catalog.h" 24 #include "dpu_hw_intf.h" 25 #include "dpu_hw_ctl.h" 26 #include "dpu_hw_dspp.h" 27 #include "dpu_hw_dsc.h" 28 #include "dpu_hw_merge3d.h" 29 #include "dpu_formats.h" 30 #include "dpu_encoder_phys.h" 31 #include "dpu_crtc.h" 32 #include "dpu_trace.h" 33 #include "dpu_core_irq.h" 34 #include "disp/msm_disp_snapshot.h" 35 36 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 37 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 38 39 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 41 42 /* 43 * Two to anticipate panels that can do cmd/vid dynamic switching 44 * plan is to create all possible physical encoder types, and switch between 45 * them at runtime 46 */ 47 #define NUM_PHYS_ENCODER_TYPES 2 48 49 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 50 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 51 52 #define MAX_CHANNELS_PER_ENC 2 53 54 #define IDLE_SHORT_TIMEOUT 1 55 56 #define MAX_HDISPLAY_SPLIT 1080 57 58 /* timeout in frames waiting for frame done */ 59 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 60 61 /** 62 * enum dpu_enc_rc_events - events for resource control state machine 63 * @DPU_ENC_RC_EVENT_KICKOFF: 64 * This event happens at NORMAL priority. 65 * Event that signals the start of the transfer. When this event is 66 * received, enable MDP/DSI core clocks. Regardless of the previous 67 * state, the resource should be in ON state at the end of this event. 68 * @DPU_ENC_RC_EVENT_FRAME_DONE: 69 * This event happens at INTERRUPT level. 70 * Event signals the end of the data transfer after the PP FRAME_DONE 71 * event. At the end of this event, a delayed work is scheduled to go to 72 * IDLE_PC state after IDLE_TIMEOUT time. 73 * @DPU_ENC_RC_EVENT_PRE_STOP: 74 * This event happens at NORMAL priority. 75 * This event, when received during the ON state, leave the RC STATE 76 * in the PRE_OFF state. It should be followed by the STOP event as 77 * part of encoder disable. 78 * If received during IDLE or OFF states, it will do nothing. 79 * @DPU_ENC_RC_EVENT_STOP: 80 * This event happens at NORMAL priority. 81 * When this event is received, disable all the MDP/DSI core clocks, and 82 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 83 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 84 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 85 * Resource state should be in OFF at the end of the event. 86 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 87 * This event happens at NORMAL priority from a work item. 88 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 89 * This would disable MDP/DSI core clocks and change the resource state 90 * to IDLE. 91 */ 92 enum dpu_enc_rc_events { 93 DPU_ENC_RC_EVENT_KICKOFF = 1, 94 DPU_ENC_RC_EVENT_FRAME_DONE, 95 DPU_ENC_RC_EVENT_PRE_STOP, 96 DPU_ENC_RC_EVENT_STOP, 97 DPU_ENC_RC_EVENT_ENTER_IDLE 98 }; 99 100 /* 101 * enum dpu_enc_rc_states - states that the resource control maintains 102 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 103 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 104 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 105 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 106 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 107 */ 108 enum dpu_enc_rc_states { 109 DPU_ENC_RC_STATE_OFF, 110 DPU_ENC_RC_STATE_PRE_OFF, 111 DPU_ENC_RC_STATE_ON, 112 DPU_ENC_RC_STATE_IDLE 113 }; 114 115 /** 116 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 117 * encoders. Virtual encoder manages one "logical" display. Physical 118 * encoders manage one intf block, tied to a specific panel/sub-panel. 119 * Virtual encoder defers as much as possible to the physical encoders. 120 * Virtual encoder registers itself with the DRM Framework as the encoder. 121 * @base: drm_encoder base class for registration with DRM 122 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 123 * @enabled: True if the encoder is active, protected by enc_lock 124 * @num_phys_encs: Actual number of physical encoders contained. 125 * @phys_encs: Container of physical encoders managed. 126 * @cur_master: Pointer to the current master in this mode. Optimization 127 * Only valid after enable. Cleared as disable. 128 * @cur_slave: As above but for the slave encoder. 129 * @hw_pp: Handle to the pingpong blocks used for the display. No. 130 * pingpong blocks can be different than num_phys_encs. 131 * @hw_dsc: Handle to the DSC blocks used for the display. 132 * @dsc_mask: Bitmask of used DSC blocks. 133 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 134 * for partial update right-only cases, such as pingpong 135 * split where virtual pingpong does not generate IRQs 136 * @crtc: Pointer to the currently assigned crtc. Normally you 137 * would use crtc->state->encoder_mask to determine the 138 * link between encoder/crtc. However in this case we need 139 * to track crtc in the disable() hook which is called 140 * _after_ encoder_mask is cleared. 141 * @connector: If a mode is set, cached pointer to the active connector 142 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 143 * all CTL paths 144 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 145 * @debugfs_root: Debug file system root file node 146 * @enc_lock: Lock around physical encoder 147 * create/destroy/enable/disable 148 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 149 * busy processing current command. 150 * Bit0 = phys_encs[0] etc. 151 * @crtc_frame_event_cb: callback handler for frame event 152 * @crtc_frame_event_cb_data: callback handler private data 153 * @frame_done_timeout_ms: frame done timeout in ms 154 * @frame_done_timer: watchdog timer for frame done event 155 * @disp_info: local copy of msm_display_info struct 156 * @idle_pc_supported: indicate if idle power collaps is supported 157 * @rc_lock: resource control mutex lock to protect 158 * virt encoder over various state changes 159 * @rc_state: resource controller state 160 * @delayed_off_work: delayed worker to schedule disabling of 161 * clks and resources after IDLE_TIMEOUT time. 162 * @topology: topology of the display 163 * @idle_timeout: idle timeout duration in milliseconds 164 * @wide_bus_en: wide bus is enabled on this interface 165 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 166 */ 167 struct dpu_encoder_virt { 168 struct drm_encoder base; 169 spinlock_t enc_spinlock; 170 171 bool enabled; 172 173 unsigned int num_phys_encs; 174 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 175 struct dpu_encoder_phys *cur_master; 176 struct dpu_encoder_phys *cur_slave; 177 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 178 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 179 180 unsigned int dsc_mask; 181 182 bool intfs_swapped; 183 184 struct drm_crtc *crtc; 185 struct drm_connector *connector; 186 187 struct dentry *debugfs_root; 188 struct mutex enc_lock; 189 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 190 void (*crtc_frame_event_cb)(void *, u32 event); 191 void *crtc_frame_event_cb_data; 192 193 atomic_t frame_done_timeout_ms; 194 struct timer_list frame_done_timer; 195 196 struct msm_display_info disp_info; 197 198 bool idle_pc_supported; 199 struct mutex rc_lock; 200 enum dpu_enc_rc_states rc_state; 201 struct delayed_work delayed_off_work; 202 struct msm_display_topology topology; 203 204 u32 idle_timeout; 205 206 bool wide_bus_en; 207 208 /* DSC configuration */ 209 struct drm_dsc_config *dsc; 210 }; 211 212 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 213 214 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 215 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 216 }; 217 218 219 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 220 { 221 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 222 223 return dpu_enc->wide_bus_en; 224 } 225 226 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 227 { 228 struct dpu_encoder_virt *dpu_enc; 229 int i, num_intf = 0; 230 231 dpu_enc = to_dpu_encoder_virt(drm_enc); 232 233 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 234 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 235 236 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 237 && phys->hw_intf->ops.collect_misr) 238 num_intf++; 239 } 240 241 return num_intf; 242 } 243 244 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 245 { 246 struct dpu_encoder_virt *dpu_enc; 247 248 int i; 249 250 dpu_enc = to_dpu_encoder_virt(drm_enc); 251 252 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 253 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 254 255 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 256 continue; 257 258 phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); 259 } 260 } 261 262 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 263 { 264 struct dpu_encoder_virt *dpu_enc; 265 266 int i, rc = 0, entries_added = 0; 267 268 if (!drm_enc->crtc) { 269 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 270 return -EINVAL; 271 } 272 273 dpu_enc = to_dpu_encoder_virt(drm_enc); 274 275 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 276 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 277 278 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 279 continue; 280 281 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 282 if (rc) 283 return rc; 284 entries_added++; 285 } 286 287 return entries_added; 288 } 289 290 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 291 { 292 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 293 294 if (!hw_pp->ops.setup_dither) 295 return; 296 297 switch (bpc) { 298 case 6: 299 dither_cfg.c0_bitdepth = 6; 300 dither_cfg.c1_bitdepth = 6; 301 dither_cfg.c2_bitdepth = 6; 302 dither_cfg.c3_bitdepth = 6; 303 dither_cfg.temporal_en = 0; 304 break; 305 default: 306 hw_pp->ops.setup_dither(hw_pp, NULL); 307 return; 308 } 309 310 memcpy(&dither_cfg.matrix, dither_matrix, 311 sizeof(u32) * DITHER_MATRIX_SZ); 312 313 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 314 } 315 316 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 317 { 318 switch (intf_mode) { 319 case INTF_MODE_VIDEO: 320 return "INTF_MODE_VIDEO"; 321 case INTF_MODE_CMD: 322 return "INTF_MODE_CMD"; 323 case INTF_MODE_WB_BLOCK: 324 return "INTF_MODE_WB_BLOCK"; 325 case INTF_MODE_WB_LINE: 326 return "INTF_MODE_WB_LINE"; 327 default: 328 return "INTF_MODE_UNKNOWN"; 329 } 330 } 331 332 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 333 enum dpu_intr_idx intr_idx) 334 { 335 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 336 DRMID(phys_enc->parent), 337 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 338 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 339 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 340 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 341 342 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 343 DPU_ENCODER_FRAME_EVENT_ERROR); 344 } 345 346 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 347 u32 irq_idx, struct dpu_encoder_wait_info *info); 348 349 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 350 unsigned int irq_idx, 351 void (*func)(void *arg), 352 struct dpu_encoder_wait_info *wait_info) 353 { 354 u32 irq_status; 355 int ret; 356 357 if (!wait_info) { 358 DPU_ERROR("invalid params\n"); 359 return -EINVAL; 360 } 361 /* note: do master / slave checking outside */ 362 363 /* return EWOULDBLOCK since we know the wait isn't necessary */ 364 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 365 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 366 DRMID(phys_enc->parent), func, 367 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 368 return -EWOULDBLOCK; 369 } 370 371 if (irq_idx < 0) { 372 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 373 DRMID(phys_enc->parent), func); 374 return 0; 375 } 376 377 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 378 DRMID(phys_enc->parent), func, 379 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 380 atomic_read(wait_info->atomic_cnt)); 381 382 ret = dpu_encoder_helper_wait_event_timeout( 383 DRMID(phys_enc->parent), 384 irq_idx, 385 wait_info); 386 387 if (ret <= 0) { 388 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 389 if (irq_status) { 390 unsigned long flags; 391 392 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 393 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 394 DRMID(phys_enc->parent), func, 395 phys_enc->hw_pp->idx - PINGPONG_0, 396 atomic_read(wait_info->atomic_cnt)); 397 local_irq_save(flags); 398 func(phys_enc); 399 local_irq_restore(flags); 400 ret = 0; 401 } else { 402 ret = -ETIMEDOUT; 403 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 404 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 405 DRMID(phys_enc->parent), func, 406 phys_enc->hw_pp->idx - PINGPONG_0, 407 atomic_read(wait_info->atomic_cnt)); 408 } 409 } else { 410 ret = 0; 411 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 412 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 413 phys_enc->hw_pp->idx - PINGPONG_0, 414 atomic_read(wait_info->atomic_cnt)); 415 } 416 417 return ret; 418 } 419 420 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 421 { 422 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 423 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 424 return phys ? atomic_read(&phys->vsync_cnt) : 0; 425 } 426 427 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 428 { 429 struct dpu_encoder_virt *dpu_enc; 430 struct dpu_encoder_phys *phys; 431 int linecount = 0; 432 433 dpu_enc = to_dpu_encoder_virt(drm_enc); 434 phys = dpu_enc ? dpu_enc->cur_master : NULL; 435 436 if (phys && phys->ops.get_line_count) 437 linecount = phys->ops.get_line_count(phys); 438 439 return linecount; 440 } 441 442 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 443 { 444 struct dpu_encoder_virt *dpu_enc = NULL; 445 int i = 0; 446 447 if (!drm_enc) { 448 DPU_ERROR("invalid encoder\n"); 449 return; 450 } 451 452 dpu_enc = to_dpu_encoder_virt(drm_enc); 453 DPU_DEBUG_ENC(dpu_enc, "\n"); 454 455 mutex_lock(&dpu_enc->enc_lock); 456 457 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 458 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 459 460 if (phys->ops.destroy) { 461 phys->ops.destroy(phys); 462 --dpu_enc->num_phys_encs; 463 dpu_enc->phys_encs[i] = NULL; 464 } 465 } 466 467 if (dpu_enc->num_phys_encs) 468 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 469 dpu_enc->num_phys_encs); 470 dpu_enc->num_phys_encs = 0; 471 mutex_unlock(&dpu_enc->enc_lock); 472 473 drm_encoder_cleanup(drm_enc); 474 mutex_destroy(&dpu_enc->enc_lock); 475 } 476 477 void dpu_encoder_helper_split_config( 478 struct dpu_encoder_phys *phys_enc, 479 enum dpu_intf interface) 480 { 481 struct dpu_encoder_virt *dpu_enc; 482 struct split_pipe_cfg cfg = { 0 }; 483 struct dpu_hw_mdp *hw_mdptop; 484 struct msm_display_info *disp_info; 485 486 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 487 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 488 return; 489 } 490 491 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 492 hw_mdptop = phys_enc->hw_mdptop; 493 disp_info = &dpu_enc->disp_info; 494 495 if (disp_info->intf_type != INTF_DSI) 496 return; 497 498 /** 499 * disable split modes since encoder will be operating in as the only 500 * encoder, either for the entire use case in the case of, for example, 501 * single DSI, or for this frame in the case of left/right only partial 502 * update. 503 */ 504 if (phys_enc->split_role == ENC_ROLE_SOLO) { 505 if (hw_mdptop->ops.setup_split_pipe) 506 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 507 return; 508 } 509 510 cfg.en = true; 511 cfg.mode = phys_enc->intf_mode; 512 cfg.intf = interface; 513 514 if (cfg.en && phys_enc->ops.needs_single_flush && 515 phys_enc->ops.needs_single_flush(phys_enc)) 516 cfg.split_flush_en = true; 517 518 if (phys_enc->split_role == ENC_ROLE_MASTER) { 519 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 520 521 if (hw_mdptop->ops.setup_split_pipe) 522 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 523 } 524 } 525 526 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 527 { 528 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 529 int i, intf_count = 0, num_dsc = 0; 530 531 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 532 if (dpu_enc->phys_encs[i]) 533 intf_count++; 534 535 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ 536 if (dpu_enc->dsc) 537 num_dsc = 2; 538 539 return (num_dsc > 0) && (num_dsc > intf_count); 540 } 541 542 static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 543 { 544 struct msm_drm_private *priv = drm_enc->dev->dev_private; 545 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 546 int index = dpu_enc->disp_info.h_tile_instance[0]; 547 548 if (dpu_enc->disp_info.intf_type == INTF_DSI) 549 return msm_dsi_get_dsc_config(priv->dsi[index]); 550 551 return NULL; 552 } 553 554 static struct msm_display_topology dpu_encoder_get_topology( 555 struct dpu_encoder_virt *dpu_enc, 556 struct dpu_kms *dpu_kms, 557 struct drm_display_mode *mode, 558 struct drm_crtc_state *crtc_state, 559 struct drm_dsc_config *dsc) 560 { 561 struct msm_display_topology topology = {0}; 562 int i, intf_count = 0; 563 564 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 565 if (dpu_enc->phys_encs[i]) 566 intf_count++; 567 568 /* Datapath topology selection 569 * 570 * Dual display 571 * 2 LM, 2 INTF ( Split display using 2 interfaces) 572 * 573 * Single display 574 * 1 LM, 1 INTF 575 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 576 * 577 * Add dspps to the reservation requirements if ctm is requested 578 */ 579 if (intf_count == 2) 580 topology.num_lm = 2; 581 else if (!dpu_kms->catalog->caps->has_3d_merge) 582 topology.num_lm = 1; 583 else 584 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 585 586 if (crtc_state->ctm) 587 topology.num_dspp = topology.num_lm; 588 589 topology.num_intf = intf_count; 590 591 if (dsc) { 592 /* 593 * In case of Display Stream Compression (DSC), we would use 594 * 2 DSC encoders, 2 layer mixers and 1 interface 595 * this is power optimal and can drive up to (including) 4k 596 * screens 597 */ 598 topology.num_dsc = 2; 599 topology.num_lm = 2; 600 topology.num_intf = 1; 601 } 602 603 return topology; 604 } 605 606 static int dpu_encoder_virt_atomic_check( 607 struct drm_encoder *drm_enc, 608 struct drm_crtc_state *crtc_state, 609 struct drm_connector_state *conn_state) 610 { 611 struct dpu_encoder_virt *dpu_enc; 612 struct msm_drm_private *priv; 613 struct dpu_kms *dpu_kms; 614 struct drm_display_mode *adj_mode; 615 struct msm_display_topology topology; 616 struct dpu_global_state *global_state; 617 struct drm_dsc_config *dsc; 618 int i = 0; 619 int ret = 0; 620 621 if (!drm_enc || !crtc_state || !conn_state) { 622 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 623 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 624 return -EINVAL; 625 } 626 627 dpu_enc = to_dpu_encoder_virt(drm_enc); 628 DPU_DEBUG_ENC(dpu_enc, "\n"); 629 630 priv = drm_enc->dev->dev_private; 631 dpu_kms = to_dpu_kms(priv->kms); 632 adj_mode = &crtc_state->adjusted_mode; 633 global_state = dpu_kms_get_global_state(crtc_state->state); 634 if (IS_ERR(global_state)) 635 return PTR_ERR(global_state); 636 637 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 638 639 /* perform atomic check on the first physical encoder (master) */ 640 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 641 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 642 643 if (phys->ops.atomic_check) 644 ret = phys->ops.atomic_check(phys, crtc_state, 645 conn_state); 646 if (ret) { 647 DPU_ERROR_ENC(dpu_enc, 648 "mode unsupported, phys idx %d\n", i); 649 return ret; 650 } 651 } 652 653 dsc = dpu_encoder_get_dsc_config(drm_enc); 654 655 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); 656 657 /* 658 * Release and Allocate resources on every modeset 659 * Dont allocate when active is false. 660 */ 661 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 662 dpu_rm_release(global_state, drm_enc); 663 664 if (!crtc_state->active_changed || crtc_state->enable) 665 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 666 drm_enc, crtc_state, topology); 667 } 668 669 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 670 671 return ret; 672 } 673 674 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 675 struct msm_display_info *disp_info) 676 { 677 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 678 struct msm_drm_private *priv; 679 struct dpu_kms *dpu_kms; 680 struct dpu_hw_mdp *hw_mdptop; 681 struct drm_encoder *drm_enc; 682 struct dpu_encoder_phys *phys_enc; 683 int i; 684 685 if (!dpu_enc || !disp_info) { 686 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 687 dpu_enc != NULL, disp_info != NULL); 688 return; 689 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 690 DPU_ERROR("invalid num phys enc %d/%d\n", 691 dpu_enc->num_phys_encs, 692 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 693 return; 694 } 695 696 drm_enc = &dpu_enc->base; 697 /* this pointers are checked in virt_enable_helper */ 698 priv = drm_enc->dev->dev_private; 699 700 dpu_kms = to_dpu_kms(priv->kms); 701 hw_mdptop = dpu_kms->hw_mdp; 702 if (!hw_mdptop) { 703 DPU_ERROR("invalid mdptop\n"); 704 return; 705 } 706 707 if (hw_mdptop->ops.setup_vsync_source && 708 disp_info->is_cmd_mode) { 709 for (i = 0; i < dpu_enc->num_phys_encs; i++) 710 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 711 712 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 713 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 714 715 if (disp_info->is_te_using_watchdog_timer) 716 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 717 else 718 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 719 720 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 721 722 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 723 phys_enc = dpu_enc->phys_encs[i]; 724 725 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 726 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 727 vsync_cfg.vsync_source); 728 } 729 } 730 } 731 732 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 733 { 734 struct dpu_encoder_virt *dpu_enc; 735 int i; 736 737 if (!drm_enc) { 738 DPU_ERROR("invalid encoder\n"); 739 return; 740 } 741 742 dpu_enc = to_dpu_encoder_virt(drm_enc); 743 744 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 745 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 746 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 747 748 if (phys->ops.irq_control) 749 phys->ops.irq_control(phys, enable); 750 } 751 752 } 753 754 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 755 bool enable) 756 { 757 struct msm_drm_private *priv; 758 struct dpu_kms *dpu_kms; 759 struct dpu_encoder_virt *dpu_enc; 760 761 dpu_enc = to_dpu_encoder_virt(drm_enc); 762 priv = drm_enc->dev->dev_private; 763 dpu_kms = to_dpu_kms(priv->kms); 764 765 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 766 767 if (!dpu_enc->cur_master) { 768 DPU_ERROR("encoder master not set\n"); 769 return; 770 } 771 772 if (enable) { 773 /* enable DPU core clks */ 774 pm_runtime_get_sync(&dpu_kms->pdev->dev); 775 776 /* enable all the irq */ 777 _dpu_encoder_irq_control(drm_enc, true); 778 779 } else { 780 /* disable all the irq */ 781 _dpu_encoder_irq_control(drm_enc, false); 782 783 /* disable DPU core clks */ 784 pm_runtime_put_sync(&dpu_kms->pdev->dev); 785 } 786 787 } 788 789 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 790 u32 sw_event) 791 { 792 struct dpu_encoder_virt *dpu_enc; 793 struct msm_drm_private *priv; 794 bool is_vid_mode = false; 795 796 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 797 DPU_ERROR("invalid parameters\n"); 798 return -EINVAL; 799 } 800 dpu_enc = to_dpu_encoder_virt(drm_enc); 801 priv = drm_enc->dev->dev_private; 802 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 803 804 /* 805 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 806 * events and return early for other events (ie wb display). 807 */ 808 if (!dpu_enc->idle_pc_supported && 809 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 810 sw_event != DPU_ENC_RC_EVENT_STOP && 811 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 812 return 0; 813 814 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 815 dpu_enc->rc_state, "begin"); 816 817 switch (sw_event) { 818 case DPU_ENC_RC_EVENT_KICKOFF: 819 /* cancel delayed off work, if any */ 820 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 821 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 822 sw_event); 823 824 mutex_lock(&dpu_enc->rc_lock); 825 826 /* return if the resource control is already in ON state */ 827 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 828 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 829 DRMID(drm_enc), sw_event); 830 mutex_unlock(&dpu_enc->rc_lock); 831 return 0; 832 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 833 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 834 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 835 DRMID(drm_enc), sw_event, 836 dpu_enc->rc_state); 837 mutex_unlock(&dpu_enc->rc_lock); 838 return -EINVAL; 839 } 840 841 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 842 _dpu_encoder_irq_control(drm_enc, true); 843 else 844 _dpu_encoder_resource_control_helper(drm_enc, true); 845 846 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 847 848 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 849 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 850 "kickoff"); 851 852 mutex_unlock(&dpu_enc->rc_lock); 853 break; 854 855 case DPU_ENC_RC_EVENT_FRAME_DONE: 856 /* 857 * mutex lock is not used as this event happens at interrupt 858 * context. And locking is not required as, the other events 859 * like KICKOFF and STOP does a wait-for-idle before executing 860 * the resource_control 861 */ 862 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 863 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 864 DRMID(drm_enc), sw_event, 865 dpu_enc->rc_state); 866 return -EINVAL; 867 } 868 869 /* 870 * schedule off work item only when there are no 871 * frames pending 872 */ 873 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 874 DRM_DEBUG_KMS("id:%d skip schedule work\n", 875 DRMID(drm_enc)); 876 return 0; 877 } 878 879 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 880 msecs_to_jiffies(dpu_enc->idle_timeout)); 881 882 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 883 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 884 "frame done"); 885 break; 886 887 case DPU_ENC_RC_EVENT_PRE_STOP: 888 /* cancel delayed off work, if any */ 889 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 890 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 891 sw_event); 892 893 mutex_lock(&dpu_enc->rc_lock); 894 895 if (is_vid_mode && 896 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 897 _dpu_encoder_irq_control(drm_enc, true); 898 } 899 /* skip if is already OFF or IDLE, resources are off already */ 900 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 901 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 902 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 903 DRMID(drm_enc), sw_event, 904 dpu_enc->rc_state); 905 mutex_unlock(&dpu_enc->rc_lock); 906 return 0; 907 } 908 909 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 910 911 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 912 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 913 "pre stop"); 914 915 mutex_unlock(&dpu_enc->rc_lock); 916 break; 917 918 case DPU_ENC_RC_EVENT_STOP: 919 mutex_lock(&dpu_enc->rc_lock); 920 921 /* return if the resource control is already in OFF state */ 922 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 923 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 924 DRMID(drm_enc), sw_event); 925 mutex_unlock(&dpu_enc->rc_lock); 926 return 0; 927 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 928 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 929 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 930 mutex_unlock(&dpu_enc->rc_lock); 931 return -EINVAL; 932 } 933 934 /** 935 * expect to arrive here only if in either idle state or pre-off 936 * and in IDLE state the resources are already disabled 937 */ 938 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 939 _dpu_encoder_resource_control_helper(drm_enc, false); 940 941 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 942 943 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 944 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 945 "stop"); 946 947 mutex_unlock(&dpu_enc->rc_lock); 948 break; 949 950 case DPU_ENC_RC_EVENT_ENTER_IDLE: 951 mutex_lock(&dpu_enc->rc_lock); 952 953 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 954 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 955 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 956 mutex_unlock(&dpu_enc->rc_lock); 957 return 0; 958 } 959 960 /* 961 * if we are in ON but a frame was just kicked off, 962 * ignore the IDLE event, it's probably a stale timer event 963 */ 964 if (dpu_enc->frame_busy_mask[0]) { 965 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 966 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 967 mutex_unlock(&dpu_enc->rc_lock); 968 return 0; 969 } 970 971 if (is_vid_mode) 972 _dpu_encoder_irq_control(drm_enc, false); 973 else 974 _dpu_encoder_resource_control_helper(drm_enc, false); 975 976 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 977 978 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 979 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 980 "idle"); 981 982 mutex_unlock(&dpu_enc->rc_lock); 983 break; 984 985 default: 986 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 987 sw_event); 988 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 989 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 990 "error"); 991 break; 992 } 993 994 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 995 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 996 "end"); 997 return 0; 998 } 999 1000 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1001 struct drm_writeback_job *job) 1002 { 1003 struct dpu_encoder_virt *dpu_enc; 1004 int i; 1005 1006 dpu_enc = to_dpu_encoder_virt(drm_enc); 1007 1008 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1009 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1010 1011 if (phys->ops.prepare_wb_job) 1012 phys->ops.prepare_wb_job(phys, job); 1013 1014 } 1015 } 1016 1017 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1018 struct drm_writeback_job *job) 1019 { 1020 struct dpu_encoder_virt *dpu_enc; 1021 int i; 1022 1023 dpu_enc = to_dpu_encoder_virt(drm_enc); 1024 1025 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1026 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1027 1028 if (phys->ops.cleanup_wb_job) 1029 phys->ops.cleanup_wb_job(phys, job); 1030 1031 } 1032 } 1033 1034 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1035 struct drm_crtc_state *crtc_state, 1036 struct drm_connector_state *conn_state) 1037 { 1038 struct dpu_encoder_virt *dpu_enc; 1039 struct msm_drm_private *priv; 1040 struct dpu_kms *dpu_kms; 1041 struct dpu_crtc_state *cstate; 1042 struct dpu_global_state *global_state; 1043 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1044 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1045 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 1046 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 1047 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1048 int num_lm, num_ctl, num_pp, num_dsc; 1049 unsigned int dsc_mask = 0; 1050 int i; 1051 1052 if (!drm_enc) { 1053 DPU_ERROR("invalid encoder\n"); 1054 return; 1055 } 1056 1057 dpu_enc = to_dpu_encoder_virt(drm_enc); 1058 DPU_DEBUG_ENC(dpu_enc, "\n"); 1059 1060 priv = drm_enc->dev->dev_private; 1061 dpu_kms = to_dpu_kms(priv->kms); 1062 1063 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1064 if (IS_ERR_OR_NULL(global_state)) { 1065 DPU_ERROR("Failed to get global state"); 1066 return; 1067 } 1068 1069 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1070 1071 /* Query resource that have been reserved in atomic check step. */ 1072 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1073 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1074 ARRAY_SIZE(hw_pp)); 1075 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1076 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1077 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1078 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1079 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1080 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 1081 ARRAY_SIZE(hw_dspp)); 1082 1083 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1084 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1085 : NULL; 1086 1087 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1088 drm_enc->base.id, DPU_HW_BLK_DSC, 1089 hw_dsc, ARRAY_SIZE(hw_dsc)); 1090 for (i = 0; i < num_dsc; i++) { 1091 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1092 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1093 } 1094 1095 dpu_enc->dsc_mask = dsc_mask; 1096 1097 cstate = to_dpu_crtc_state(crtc_state); 1098 1099 for (i = 0; i < num_lm; i++) { 1100 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1101 1102 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1103 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1104 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1105 } 1106 1107 cstate->num_mixers = num_lm; 1108 1109 dpu_enc->connector = conn_state->connector; 1110 1111 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1112 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1113 1114 if (!dpu_enc->hw_pp[i]) { 1115 DPU_ERROR_ENC(dpu_enc, 1116 "no pp block assigned at idx: %d\n", i); 1117 return; 1118 } 1119 1120 if (!hw_ctl[i]) { 1121 DPU_ERROR_ENC(dpu_enc, 1122 "no ctl block assigned at idx: %d\n", i); 1123 return; 1124 } 1125 1126 phys->hw_pp = dpu_enc->hw_pp[i]; 1127 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1128 1129 phys->cached_mode = crtc_state->adjusted_mode; 1130 if (phys->ops.atomic_mode_set) 1131 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1132 } 1133 } 1134 1135 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1136 { 1137 struct dpu_encoder_virt *dpu_enc = NULL; 1138 int i; 1139 1140 if (!drm_enc || !drm_enc->dev) { 1141 DPU_ERROR("invalid parameters\n"); 1142 return; 1143 } 1144 1145 dpu_enc = to_dpu_encoder_virt(drm_enc); 1146 if (!dpu_enc || !dpu_enc->cur_master) { 1147 DPU_ERROR("invalid dpu encoder/master\n"); 1148 return; 1149 } 1150 1151 1152 if (dpu_enc->disp_info.intf_type == INTF_DP && 1153 dpu_enc->cur_master->hw_mdptop && 1154 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1155 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1156 dpu_enc->cur_master->hw_mdptop); 1157 1158 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1159 1160 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1161 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1162 unsigned bpc = dpu_enc->connector->display_info.bpc; 1163 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1164 if (!dpu_enc->hw_pp[i]) 1165 continue; 1166 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1167 } 1168 } 1169 } 1170 1171 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1172 { 1173 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1174 1175 mutex_lock(&dpu_enc->enc_lock); 1176 1177 if (!dpu_enc->enabled) 1178 goto out; 1179 1180 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1181 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1182 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1183 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1184 1185 _dpu_encoder_virt_enable_helper(drm_enc); 1186 1187 out: 1188 mutex_unlock(&dpu_enc->enc_lock); 1189 } 1190 1191 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1192 struct drm_atomic_state *state) 1193 { 1194 struct dpu_encoder_virt *dpu_enc = NULL; 1195 int ret = 0; 1196 struct drm_display_mode *cur_mode = NULL; 1197 struct msm_drm_private *priv = drm_enc->dev->dev_private; 1198 struct msm_display_info *disp_info; 1199 int index; 1200 1201 dpu_enc = to_dpu_encoder_virt(drm_enc); 1202 disp_info = &dpu_enc->disp_info; 1203 index = disp_info->h_tile_instance[0]; 1204 1205 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1206 1207 if (disp_info->intf_type == INTF_DP) 1208 dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]); 1209 else if (disp_info->intf_type == INTF_DSI) 1210 dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]); 1211 1212 mutex_lock(&dpu_enc->enc_lock); 1213 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1214 1215 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1216 cur_mode->vdisplay); 1217 1218 /* always enable slave encoder before master */ 1219 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1220 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1221 1222 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1223 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1224 1225 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1226 if (ret) { 1227 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1228 ret); 1229 goto out; 1230 } 1231 1232 _dpu_encoder_virt_enable_helper(drm_enc); 1233 1234 dpu_enc->enabled = true; 1235 1236 out: 1237 mutex_unlock(&dpu_enc->enc_lock); 1238 } 1239 1240 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1241 struct drm_atomic_state *state) 1242 { 1243 struct dpu_encoder_virt *dpu_enc = NULL; 1244 struct drm_crtc *crtc; 1245 struct drm_crtc_state *old_state = NULL; 1246 int i = 0; 1247 1248 dpu_enc = to_dpu_encoder_virt(drm_enc); 1249 DPU_DEBUG_ENC(dpu_enc, "\n"); 1250 1251 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1252 if (crtc) 1253 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1254 1255 /* 1256 * The encoder is already disabled if self refresh mode was set earlier, 1257 * in the old_state for the corresponding crtc. 1258 */ 1259 if (old_state && old_state->self_refresh_active) 1260 return; 1261 1262 mutex_lock(&dpu_enc->enc_lock); 1263 dpu_enc->enabled = false; 1264 1265 trace_dpu_enc_disable(DRMID(drm_enc)); 1266 1267 /* wait for idle */ 1268 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1269 1270 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1271 1272 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1273 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1274 1275 if (phys->ops.disable) 1276 phys->ops.disable(phys); 1277 } 1278 1279 1280 /* after phys waits for frame-done, should be no more frames pending */ 1281 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1282 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1283 del_timer_sync(&dpu_enc->frame_done_timer); 1284 } 1285 1286 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1287 1288 dpu_enc->connector = NULL; 1289 1290 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1291 1292 mutex_unlock(&dpu_enc->enc_lock); 1293 } 1294 1295 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1296 struct dpu_rm *dpu_rm, 1297 enum dpu_intf_type type, u32 controller_id) 1298 { 1299 int i = 0; 1300 1301 if (type == INTF_WB) 1302 return NULL; 1303 1304 for (i = 0; i < catalog->intf_count; i++) { 1305 if (catalog->intf[i].type == type 1306 && catalog->intf[i].controller_id == controller_id) { 1307 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1308 } 1309 } 1310 1311 return NULL; 1312 } 1313 1314 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1315 struct dpu_encoder_phys *phy_enc) 1316 { 1317 struct dpu_encoder_virt *dpu_enc = NULL; 1318 unsigned long lock_flags; 1319 1320 if (!drm_enc || !phy_enc) 1321 return; 1322 1323 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1324 dpu_enc = to_dpu_encoder_virt(drm_enc); 1325 1326 atomic_inc(&phy_enc->vsync_cnt); 1327 1328 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1329 if (dpu_enc->crtc) 1330 dpu_crtc_vblank_callback(dpu_enc->crtc); 1331 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1332 1333 DPU_ATRACE_END("encoder_vblank_callback"); 1334 } 1335 1336 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1337 struct dpu_encoder_phys *phy_enc) 1338 { 1339 if (!phy_enc) 1340 return; 1341 1342 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1343 atomic_inc(&phy_enc->underrun_cnt); 1344 1345 /* trigger dump only on the first underrun */ 1346 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1347 msm_disp_snapshot_state(drm_enc->dev); 1348 1349 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1350 atomic_read(&phy_enc->underrun_cnt)); 1351 DPU_ATRACE_END("encoder_underrun_callback"); 1352 } 1353 1354 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1355 { 1356 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1357 unsigned long lock_flags; 1358 1359 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1360 /* crtc should always be cleared before re-assigning */ 1361 WARN_ON(crtc && dpu_enc->crtc); 1362 dpu_enc->crtc = crtc; 1363 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1364 } 1365 1366 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1367 struct drm_crtc *crtc, bool enable) 1368 { 1369 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1370 unsigned long lock_flags; 1371 int i; 1372 1373 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1374 1375 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1376 if (dpu_enc->crtc != crtc) { 1377 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1378 return; 1379 } 1380 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1381 1382 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1383 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1384 1385 if (phys->ops.control_vblank_irq) 1386 phys->ops.control_vblank_irq(phys, enable); 1387 } 1388 } 1389 1390 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1391 void (*frame_event_cb)(void *, u32 event), 1392 void *frame_event_cb_data) 1393 { 1394 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1395 unsigned long lock_flags; 1396 bool enable; 1397 1398 enable = frame_event_cb ? true : false; 1399 1400 if (!drm_enc) { 1401 DPU_ERROR("invalid encoder\n"); 1402 return; 1403 } 1404 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1405 1406 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1407 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1408 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1409 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1410 } 1411 1412 void dpu_encoder_frame_done_callback( 1413 struct drm_encoder *drm_enc, 1414 struct dpu_encoder_phys *ready_phys, u32 event) 1415 { 1416 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1417 unsigned int i; 1418 1419 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1420 | DPU_ENCODER_FRAME_EVENT_ERROR 1421 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1422 1423 if (!dpu_enc->frame_busy_mask[0]) { 1424 /** 1425 * suppress frame_done without waiter, 1426 * likely autorefresh 1427 */ 1428 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1429 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1430 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1431 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1432 return; 1433 } 1434 1435 /* One of the physical encoders has become idle */ 1436 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1437 if (dpu_enc->phys_encs[i] == ready_phys) { 1438 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1439 dpu_enc->frame_busy_mask[0]); 1440 clear_bit(i, dpu_enc->frame_busy_mask); 1441 } 1442 } 1443 1444 if (!dpu_enc->frame_busy_mask[0]) { 1445 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1446 del_timer(&dpu_enc->frame_done_timer); 1447 1448 dpu_encoder_resource_control(drm_enc, 1449 DPU_ENC_RC_EVENT_FRAME_DONE); 1450 1451 if (dpu_enc->crtc_frame_event_cb) 1452 dpu_enc->crtc_frame_event_cb( 1453 dpu_enc->crtc_frame_event_cb_data, 1454 event); 1455 } 1456 } else { 1457 if (dpu_enc->crtc_frame_event_cb) 1458 dpu_enc->crtc_frame_event_cb( 1459 dpu_enc->crtc_frame_event_cb_data, event); 1460 } 1461 } 1462 1463 static void dpu_encoder_off_work(struct work_struct *work) 1464 { 1465 struct dpu_encoder_virt *dpu_enc = container_of(work, 1466 struct dpu_encoder_virt, delayed_off_work.work); 1467 1468 dpu_encoder_resource_control(&dpu_enc->base, 1469 DPU_ENC_RC_EVENT_ENTER_IDLE); 1470 1471 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1472 DPU_ENCODER_FRAME_EVENT_IDLE); 1473 } 1474 1475 /** 1476 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1477 * @drm_enc: Pointer to drm encoder structure 1478 * @phys: Pointer to physical encoder structure 1479 * @extra_flush_bits: Additional bit mask to include in flush trigger 1480 */ 1481 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1482 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1483 { 1484 struct dpu_hw_ctl *ctl; 1485 int pending_kickoff_cnt; 1486 u32 ret = UINT_MAX; 1487 1488 if (!phys->hw_pp) { 1489 DPU_ERROR("invalid pingpong hw\n"); 1490 return; 1491 } 1492 1493 ctl = phys->hw_ctl; 1494 if (!ctl->ops.trigger_flush) { 1495 DPU_ERROR("missing trigger cb\n"); 1496 return; 1497 } 1498 1499 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1500 1501 if (extra_flush_bits && ctl->ops.update_pending_flush) 1502 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1503 1504 ctl->ops.trigger_flush(ctl); 1505 1506 if (ctl->ops.get_pending_flush) 1507 ret = ctl->ops.get_pending_flush(ctl); 1508 1509 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1510 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1511 phys->hw_intf ? phys->hw_intf->idx : -1, 1512 phys->hw_wb ? phys->hw_wb->idx : -1, 1513 pending_kickoff_cnt, ctl->idx, 1514 extra_flush_bits, ret); 1515 } 1516 1517 /** 1518 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1519 * @phys: Pointer to physical encoder structure 1520 */ 1521 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1522 { 1523 if (!phys) { 1524 DPU_ERROR("invalid argument(s)\n"); 1525 return; 1526 } 1527 1528 if (!phys->hw_pp) { 1529 DPU_ERROR("invalid pingpong hw\n"); 1530 return; 1531 } 1532 1533 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1534 phys->ops.trigger_start(phys); 1535 } 1536 1537 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1538 { 1539 struct dpu_hw_ctl *ctl; 1540 1541 ctl = phys_enc->hw_ctl; 1542 if (ctl->ops.trigger_start) { 1543 ctl->ops.trigger_start(ctl); 1544 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1545 } 1546 } 1547 1548 static int dpu_encoder_helper_wait_event_timeout( 1549 int32_t drm_id, 1550 unsigned int irq_idx, 1551 struct dpu_encoder_wait_info *info) 1552 { 1553 int rc = 0; 1554 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1555 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1556 s64 time; 1557 1558 do { 1559 rc = wait_event_timeout(*(info->wq), 1560 atomic_read(info->atomic_cnt) == 0, jiffies); 1561 time = ktime_to_ms(ktime_get()); 1562 1563 trace_dpu_enc_wait_event_timeout(drm_id, 1564 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1565 rc, time, 1566 expected_time, 1567 atomic_read(info->atomic_cnt)); 1568 /* If we timed out, counter is valid and time is less, wait again */ 1569 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1570 (time < expected_time)); 1571 1572 return rc; 1573 } 1574 1575 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1576 { 1577 struct dpu_encoder_virt *dpu_enc; 1578 struct dpu_hw_ctl *ctl; 1579 int rc; 1580 struct drm_encoder *drm_enc; 1581 1582 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1583 ctl = phys_enc->hw_ctl; 1584 drm_enc = phys_enc->parent; 1585 1586 if (!ctl->ops.reset) 1587 return; 1588 1589 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1590 ctl->idx); 1591 1592 rc = ctl->ops.reset(ctl); 1593 if (rc) { 1594 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1595 msm_disp_snapshot_state(drm_enc->dev); 1596 } 1597 1598 phys_enc->enable_state = DPU_ENC_ENABLED; 1599 } 1600 1601 /** 1602 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1603 * Iterate through the physical encoders and perform consolidated flush 1604 * and/or control start triggering as needed. This is done in the virtual 1605 * encoder rather than the individual physical ones in order to handle 1606 * use cases that require visibility into multiple physical encoders at 1607 * a time. 1608 * @dpu_enc: Pointer to virtual encoder structure 1609 */ 1610 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1611 { 1612 struct dpu_hw_ctl *ctl; 1613 uint32_t i, pending_flush; 1614 unsigned long lock_flags; 1615 1616 pending_flush = 0x0; 1617 1618 /* update pending counts and trigger kickoff ctl flush atomically */ 1619 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1620 1621 /* don't perform flush/start operations for slave encoders */ 1622 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1623 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1624 1625 if (phys->enable_state == DPU_ENC_DISABLED) 1626 continue; 1627 1628 ctl = phys->hw_ctl; 1629 1630 /* 1631 * This is cleared in frame_done worker, which isn't invoked 1632 * for async commits. So don't set this for async, since it'll 1633 * roll over to the next commit. 1634 */ 1635 if (phys->split_role != ENC_ROLE_SLAVE) 1636 set_bit(i, dpu_enc->frame_busy_mask); 1637 1638 if (!phys->ops.needs_single_flush || 1639 !phys->ops.needs_single_flush(phys)) 1640 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1641 else if (ctl->ops.get_pending_flush) 1642 pending_flush |= ctl->ops.get_pending_flush(ctl); 1643 } 1644 1645 /* for split flush, combine pending flush masks and send to master */ 1646 if (pending_flush && dpu_enc->cur_master) { 1647 _dpu_encoder_trigger_flush( 1648 &dpu_enc->base, 1649 dpu_enc->cur_master, 1650 pending_flush); 1651 } 1652 1653 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1654 1655 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1656 } 1657 1658 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1659 { 1660 struct dpu_encoder_virt *dpu_enc; 1661 struct dpu_encoder_phys *phys; 1662 unsigned int i; 1663 struct dpu_hw_ctl *ctl; 1664 struct msm_display_info *disp_info; 1665 1666 if (!drm_enc) { 1667 DPU_ERROR("invalid encoder\n"); 1668 return; 1669 } 1670 dpu_enc = to_dpu_encoder_virt(drm_enc); 1671 disp_info = &dpu_enc->disp_info; 1672 1673 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1674 phys = dpu_enc->phys_encs[i]; 1675 1676 ctl = phys->hw_ctl; 1677 if (ctl->ops.clear_pending_flush) 1678 ctl->ops.clear_pending_flush(ctl); 1679 1680 /* update only for command mode primary ctl */ 1681 if ((phys == dpu_enc->cur_master) && 1682 disp_info->is_cmd_mode 1683 && ctl->ops.trigger_pending) 1684 ctl->ops.trigger_pending(ctl); 1685 } 1686 } 1687 1688 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1689 struct drm_display_mode *mode) 1690 { 1691 u64 pclk_rate; 1692 u32 pclk_period; 1693 u32 line_time; 1694 1695 /* 1696 * For linetime calculation, only operate on master encoder. 1697 */ 1698 if (!dpu_enc->cur_master) 1699 return 0; 1700 1701 if (!dpu_enc->cur_master->ops.get_line_count) { 1702 DPU_ERROR("get_line_count function not defined\n"); 1703 return 0; 1704 } 1705 1706 pclk_rate = mode->clock; /* pixel clock in kHz */ 1707 if (pclk_rate == 0) { 1708 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1709 return 0; 1710 } 1711 1712 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1713 if (pclk_period == 0) { 1714 DPU_ERROR("pclk period is 0\n"); 1715 return 0; 1716 } 1717 1718 /* 1719 * Line time calculation based on Pixel clock and HTOTAL. 1720 * Final unit is in ns. 1721 */ 1722 line_time = (pclk_period * mode->htotal) / 1000; 1723 if (line_time == 0) { 1724 DPU_ERROR("line time calculation is 0\n"); 1725 return 0; 1726 } 1727 1728 DPU_DEBUG_ENC(dpu_enc, 1729 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1730 pclk_rate, pclk_period, line_time); 1731 1732 return line_time; 1733 } 1734 1735 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1736 { 1737 struct drm_display_mode *mode; 1738 struct dpu_encoder_virt *dpu_enc; 1739 u32 cur_line; 1740 u32 line_time; 1741 u32 vtotal, time_to_vsync; 1742 ktime_t cur_time; 1743 1744 dpu_enc = to_dpu_encoder_virt(drm_enc); 1745 1746 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1747 DPU_ERROR("crtc/crtc state object is NULL\n"); 1748 return -EINVAL; 1749 } 1750 mode = &drm_enc->crtc->state->adjusted_mode; 1751 1752 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1753 if (!line_time) 1754 return -EINVAL; 1755 1756 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1757 1758 vtotal = mode->vtotal; 1759 if (cur_line >= vtotal) 1760 time_to_vsync = line_time * vtotal; 1761 else 1762 time_to_vsync = line_time * (vtotal - cur_line); 1763 1764 if (time_to_vsync == 0) { 1765 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1766 vtotal); 1767 return -EINVAL; 1768 } 1769 1770 cur_time = ktime_get(); 1771 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1772 1773 DPU_DEBUG_ENC(dpu_enc, 1774 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1775 cur_line, vtotal, time_to_vsync, 1776 ktime_to_ms(cur_time), 1777 ktime_to_ms(*wakeup_time)); 1778 return 0; 1779 } 1780 1781 static u32 1782 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1783 u32 enc_ip_width) 1784 { 1785 int ssm_delay, total_pixels, soft_slice_per_enc; 1786 1787 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1788 1789 /* 1790 * minimum number of initial line pixels is a sum of: 1791 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1792 * 91 for 10 bpc) * 3 1793 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1794 * 3. the initial xmit delay 1795 * 4. total pipeline delay through the "lock step" of encoder (47) 1796 * 5. 6 additional pixels as the output of the rate buffer is 1797 * 48 bits wide 1798 */ 1799 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1800 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1801 if (soft_slice_per_enc > 1) 1802 total_pixels += (ssm_delay * 3); 1803 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1804 } 1805 1806 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1807 struct dpu_hw_dsc *hw_dsc, 1808 struct dpu_hw_pingpong *hw_pp, 1809 struct drm_dsc_config *dsc, 1810 u32 common_mode, 1811 u32 initial_lines) 1812 { 1813 if (hw_dsc->ops.dsc_config) 1814 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1815 1816 if (hw_dsc->ops.dsc_config_thresh) 1817 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 1818 1819 if (hw_pp->ops.setup_dsc) 1820 hw_pp->ops.setup_dsc(hw_pp); 1821 1822 if (hw_dsc->ops.dsc_bind_pingpong_blk) 1823 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 1824 1825 if (hw_pp->ops.enable_dsc) 1826 hw_pp->ops.enable_dsc(hw_pp); 1827 1828 if (ctl->ops.update_pending_flush_dsc) 1829 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 1830 } 1831 1832 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 1833 struct drm_dsc_config *dsc) 1834 { 1835 /* coding only for 2LM, 2enc, 1 dsc config */ 1836 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 1837 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 1838 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 1839 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 1840 int this_frame_slices; 1841 int intf_ip_w, enc_ip_w; 1842 int dsc_common_mode; 1843 int pic_width; 1844 u32 initial_lines; 1845 int i; 1846 1847 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1848 hw_pp[i] = dpu_enc->hw_pp[i]; 1849 hw_dsc[i] = dpu_enc->hw_dsc[i]; 1850 1851 if (!hw_pp[i] || !hw_dsc[i]) { 1852 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); 1853 return; 1854 } 1855 } 1856 1857 dsc_common_mode = 0; 1858 pic_width = dsc->pic_width; 1859 1860 dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; 1861 if (enc_master->intf_mode == INTF_MODE_VIDEO) 1862 dsc_common_mode |= DSC_MODE_VIDEO; 1863 1864 this_frame_slices = pic_width / dsc->slice_width; 1865 intf_ip_w = this_frame_slices * dsc->slice_width; 1866 1867 /* 1868 * dsc merge case: when using 2 encoders for the same stream, 1869 * no. of slices need to be same on both the encoders. 1870 */ 1871 enc_ip_w = intf_ip_w / 2; 1872 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 1873 1874 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1875 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 1876 dsc, dsc_common_mode, initial_lines); 1877 } 1878 1879 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1880 { 1881 struct dpu_encoder_virt *dpu_enc; 1882 struct dpu_encoder_phys *phys; 1883 bool needs_hw_reset = false; 1884 unsigned int i; 1885 1886 dpu_enc = to_dpu_encoder_virt(drm_enc); 1887 1888 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1889 1890 /* prepare for next kickoff, may include waiting on previous kickoff */ 1891 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1892 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1893 phys = dpu_enc->phys_encs[i]; 1894 if (phys->ops.prepare_for_kickoff) 1895 phys->ops.prepare_for_kickoff(phys); 1896 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1897 needs_hw_reset = true; 1898 } 1899 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1900 1901 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1902 1903 /* if any phys needs reset, reset all phys, in-order */ 1904 if (needs_hw_reset) { 1905 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1906 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1907 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1908 } 1909 } 1910 1911 if (dpu_enc->dsc) 1912 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 1913 } 1914 1915 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 1916 { 1917 struct dpu_encoder_virt *dpu_enc; 1918 unsigned int i; 1919 struct dpu_encoder_phys *phys; 1920 1921 dpu_enc = to_dpu_encoder_virt(drm_enc); 1922 1923 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 1924 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1925 phys = dpu_enc->phys_encs[i]; 1926 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 1927 DPU_DEBUG("invalid FB not kicking off\n"); 1928 return false; 1929 } 1930 } 1931 } 1932 1933 return true; 1934 } 1935 1936 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1937 { 1938 struct dpu_encoder_virt *dpu_enc; 1939 struct dpu_encoder_phys *phys; 1940 unsigned long timeout_ms; 1941 unsigned int i; 1942 1943 DPU_ATRACE_BEGIN("encoder_kickoff"); 1944 dpu_enc = to_dpu_encoder_virt(drm_enc); 1945 1946 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1947 1948 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1949 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1950 1951 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1952 mod_timer(&dpu_enc->frame_done_timer, 1953 jiffies + msecs_to_jiffies(timeout_ms)); 1954 1955 /* All phys encs are ready to go, trigger the kickoff */ 1956 _dpu_encoder_kickoff_phys(dpu_enc); 1957 1958 /* allow phys encs to handle any post-kickoff business */ 1959 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1960 phys = dpu_enc->phys_encs[i]; 1961 if (phys->ops.handle_post_kickoff) 1962 phys->ops.handle_post_kickoff(phys); 1963 } 1964 1965 DPU_ATRACE_END("encoder_kickoff"); 1966 } 1967 1968 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 1969 { 1970 struct dpu_hw_mixer_cfg mixer; 1971 int i, num_lm; 1972 struct dpu_global_state *global_state; 1973 struct dpu_hw_blk *hw_lm[2]; 1974 struct dpu_hw_mixer *hw_mixer[2]; 1975 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 1976 1977 memset(&mixer, 0, sizeof(mixer)); 1978 1979 /* reset all mixers for this encoder */ 1980 if (phys_enc->hw_ctl->ops.clear_all_blendstages) 1981 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); 1982 1983 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 1984 1985 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 1986 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1987 1988 for (i = 0; i < num_lm; i++) { 1989 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 1990 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer) 1991 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 1992 1993 /* clear all blendstages */ 1994 if (phys_enc->hw_ctl->ops.setup_blendstage) 1995 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 1996 } 1997 } 1998 1999 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 2000 struct dpu_hw_dsc *hw_dsc, 2001 struct dpu_hw_pingpong *hw_pp) 2002 { 2003 if (hw_dsc->ops.dsc_disable) 2004 hw_dsc->ops.dsc_disable(hw_dsc); 2005 2006 if (hw_pp->ops.disable_dsc) 2007 hw_pp->ops.disable_dsc(hw_pp); 2008 2009 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2010 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2011 2012 if (ctl->ops.update_pending_flush_dsc) 2013 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2014 } 2015 2016 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2017 { 2018 /* coding only for 2LM, 2enc, 1 dsc config */ 2019 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2020 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2021 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2022 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2023 int i; 2024 2025 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2026 hw_pp[i] = dpu_enc->hw_pp[i]; 2027 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2028 2029 if (hw_pp[i] && hw_dsc[i]) 2030 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2031 } 2032 } 2033 2034 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2035 { 2036 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2037 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2038 int i; 2039 struct dpu_encoder_virt *dpu_enc; 2040 2041 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2042 2043 phys_enc->hw_ctl->ops.reset(ctl); 2044 2045 dpu_encoder_helper_reset_mixers(phys_enc); 2046 2047 /* 2048 * TODO: move the once-only operation like CTL flush/trigger 2049 * into dpu_encoder_virt_disable() and all operations which need 2050 * to be done per phys encoder into the phys_disable() op. 2051 */ 2052 if (phys_enc->hw_wb) { 2053 /* disable the PP block */ 2054 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2055 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2056 2057 /* mark WB flush as pending */ 2058 if (phys_enc->hw_ctl->ops.update_pending_flush_wb) 2059 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2060 } else { 2061 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2062 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2063 phys_enc->hw_intf->ops.bind_pingpong_blk( 2064 dpu_enc->phys_encs[i]->hw_intf, 2065 PINGPONG_NONE); 2066 2067 /* mark INTF flush as pending */ 2068 if (phys_enc->hw_ctl->ops.update_pending_flush_intf) 2069 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl, 2070 dpu_enc->phys_encs[i]->hw_intf->idx); 2071 } 2072 } 2073 2074 /* reset the merge 3D HW block */ 2075 if (phys_enc->hw_pp->merge_3d) { 2076 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2077 BLEND_3D_NONE); 2078 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d) 2079 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl, 2080 phys_enc->hw_pp->merge_3d->idx); 2081 } 2082 2083 if (dpu_enc->dsc) { 2084 dpu_encoder_unprep_dsc(dpu_enc); 2085 dpu_enc->dsc = NULL; 2086 } 2087 2088 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2089 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2090 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2091 2092 if (phys_enc->hw_intf) 2093 intf_cfg.intf = phys_enc->hw_intf->idx; 2094 if (phys_enc->hw_wb) 2095 intf_cfg.wb = phys_enc->hw_wb->idx; 2096 2097 if (phys_enc->hw_pp->merge_3d) 2098 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2099 2100 if (ctl->ops.reset_intf_cfg) 2101 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2102 2103 ctl->ops.trigger_flush(ctl); 2104 ctl->ops.trigger_start(ctl); 2105 ctl->ops.clear_pending_flush(ctl); 2106 } 2107 2108 #ifdef CONFIG_DEBUG_FS 2109 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2110 { 2111 struct dpu_encoder_virt *dpu_enc = s->private; 2112 int i; 2113 2114 mutex_lock(&dpu_enc->enc_lock); 2115 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2116 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2117 2118 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d ", 2119 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2120 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2121 atomic_read(&phys->vsync_cnt), 2122 atomic_read(&phys->underrun_cnt)); 2123 2124 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2125 } 2126 mutex_unlock(&dpu_enc->enc_lock); 2127 2128 return 0; 2129 } 2130 2131 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2132 2133 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 2134 { 2135 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2136 2137 char name[12]; 2138 2139 if (!drm_enc->dev) { 2140 DPU_ERROR("invalid encoder or kms\n"); 2141 return -EINVAL; 2142 } 2143 2144 snprintf(name, sizeof(name), "encoder%u", drm_enc->base.id); 2145 2146 /* create overall sub-directory for the encoder */ 2147 dpu_enc->debugfs_root = debugfs_create_dir(name, 2148 drm_enc->dev->primary->debugfs_root); 2149 2150 /* don't error check these */ 2151 debugfs_create_file("status", 0600, 2152 dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops); 2153 2154 return 0; 2155 } 2156 #else 2157 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 2158 { 2159 return 0; 2160 } 2161 #endif 2162 2163 static int dpu_encoder_late_register(struct drm_encoder *encoder) 2164 { 2165 return _dpu_encoder_init_debugfs(encoder); 2166 } 2167 2168 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 2169 { 2170 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2171 2172 debugfs_remove_recursive(dpu_enc->debugfs_root); 2173 } 2174 2175 static int dpu_encoder_virt_add_phys_encs( 2176 struct msm_display_info *disp_info, 2177 struct dpu_encoder_virt *dpu_enc, 2178 struct dpu_enc_phys_init_params *params) 2179 { 2180 struct dpu_encoder_phys *enc = NULL; 2181 2182 DPU_DEBUG_ENC(dpu_enc, "\n"); 2183 2184 /* 2185 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2186 * in this function, check up-front. 2187 */ 2188 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2189 ARRAY_SIZE(dpu_enc->phys_encs)) { 2190 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2191 dpu_enc->num_phys_encs); 2192 return -EINVAL; 2193 } 2194 2195 2196 if (disp_info->intf_type == INTF_WB) { 2197 enc = dpu_encoder_phys_wb_init(params); 2198 2199 if (IS_ERR(enc)) { 2200 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2201 PTR_ERR(enc)); 2202 return PTR_ERR(enc); 2203 } 2204 2205 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2206 ++dpu_enc->num_phys_encs; 2207 } else if (disp_info->is_cmd_mode) { 2208 enc = dpu_encoder_phys_cmd_init(params); 2209 2210 if (IS_ERR(enc)) { 2211 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2212 PTR_ERR(enc)); 2213 return PTR_ERR(enc); 2214 } 2215 2216 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2217 ++dpu_enc->num_phys_encs; 2218 } else { 2219 enc = dpu_encoder_phys_vid_init(params); 2220 2221 if (IS_ERR(enc)) { 2222 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2223 PTR_ERR(enc)); 2224 return PTR_ERR(enc); 2225 } 2226 2227 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2228 ++dpu_enc->num_phys_encs; 2229 } 2230 2231 if (params->split_role == ENC_ROLE_SLAVE) 2232 dpu_enc->cur_slave = enc; 2233 else 2234 dpu_enc->cur_master = enc; 2235 2236 return 0; 2237 } 2238 2239 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2240 struct dpu_kms *dpu_kms, 2241 struct msm_display_info *disp_info) 2242 { 2243 int ret = 0; 2244 int i = 0; 2245 struct dpu_enc_phys_init_params phys_params; 2246 2247 if (!dpu_enc) { 2248 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2249 return -EINVAL; 2250 } 2251 2252 dpu_enc->cur_master = NULL; 2253 2254 memset(&phys_params, 0, sizeof(phys_params)); 2255 phys_params.dpu_kms = dpu_kms; 2256 phys_params.parent = &dpu_enc->base; 2257 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2258 2259 WARN_ON(disp_info->num_of_h_tiles < 1); 2260 2261 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2262 2263 if (disp_info->intf_type != INTF_WB) 2264 dpu_enc->idle_pc_supported = 2265 dpu_kms->catalog->caps->has_idle_pc; 2266 2267 mutex_lock(&dpu_enc->enc_lock); 2268 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2269 /* 2270 * Left-most tile is at index 0, content is controller id 2271 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2272 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2273 */ 2274 u32 controller_id = disp_info->h_tile_instance[i]; 2275 2276 if (disp_info->num_of_h_tiles > 1) { 2277 if (i == 0) 2278 phys_params.split_role = ENC_ROLE_MASTER; 2279 else 2280 phys_params.split_role = ENC_ROLE_SLAVE; 2281 } else { 2282 phys_params.split_role = ENC_ROLE_SOLO; 2283 } 2284 2285 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2286 i, controller_id, phys_params.split_role); 2287 2288 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2289 disp_info->intf_type, 2290 controller_id); 2291 2292 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2293 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2294 2295 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2296 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2297 ret = -EINVAL; 2298 break; 2299 } 2300 2301 if (phys_params.hw_intf && phys_params.hw_wb) { 2302 DPU_ERROR_ENC(dpu_enc, 2303 "invalid phys both intf and wb block at idx: %d\n", i); 2304 ret = -EINVAL; 2305 break; 2306 } 2307 2308 ret = dpu_encoder_virt_add_phys_encs(disp_info, 2309 dpu_enc, &phys_params); 2310 if (ret) { 2311 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2312 break; 2313 } 2314 } 2315 2316 mutex_unlock(&dpu_enc->enc_lock); 2317 2318 return ret; 2319 } 2320 2321 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2322 { 2323 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2324 frame_done_timer); 2325 struct drm_encoder *drm_enc = &dpu_enc->base; 2326 u32 event; 2327 2328 if (!drm_enc->dev) { 2329 DPU_ERROR("invalid parameters\n"); 2330 return; 2331 } 2332 2333 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2334 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2335 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2336 return; 2337 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2338 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2339 return; 2340 } 2341 2342 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2343 2344 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2345 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2346 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2347 } 2348 2349 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2350 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2351 .atomic_disable = dpu_encoder_virt_atomic_disable, 2352 .atomic_enable = dpu_encoder_virt_atomic_enable, 2353 .atomic_check = dpu_encoder_virt_atomic_check, 2354 }; 2355 2356 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2357 .destroy = dpu_encoder_destroy, 2358 .late_register = dpu_encoder_late_register, 2359 .early_unregister = dpu_encoder_early_unregister, 2360 }; 2361 2362 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2363 int drm_enc_mode, 2364 struct msm_display_info *disp_info) 2365 { 2366 struct msm_drm_private *priv = dev->dev_private; 2367 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2368 struct drm_encoder *drm_enc = NULL; 2369 struct dpu_encoder_virt *dpu_enc = NULL; 2370 int ret = 0; 2371 2372 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2373 if (!dpu_enc) 2374 return ERR_PTR(-ENOMEM); 2375 2376 ret = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2377 drm_enc_mode, NULL); 2378 if (ret) { 2379 devm_kfree(dev->dev, dpu_enc); 2380 return ERR_PTR(ret); 2381 } 2382 2383 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2384 2385 spin_lock_init(&dpu_enc->enc_spinlock); 2386 dpu_enc->enabled = false; 2387 mutex_init(&dpu_enc->enc_lock); 2388 mutex_init(&dpu_enc->rc_lock); 2389 2390 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2391 if (ret) 2392 goto fail; 2393 2394 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2395 timer_setup(&dpu_enc->frame_done_timer, 2396 dpu_encoder_frame_done_timeout, 0); 2397 2398 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2399 dpu_encoder_off_work); 2400 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2401 2402 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2403 2404 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2405 2406 return &dpu_enc->base; 2407 2408 fail: 2409 DPU_ERROR("failed to create encoder\n"); 2410 if (drm_enc) 2411 dpu_encoder_destroy(drm_enc); 2412 2413 return ERR_PTR(ret); 2414 } 2415 2416 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2417 enum msm_event_wait event) 2418 { 2419 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2420 struct dpu_encoder_virt *dpu_enc = NULL; 2421 int i, ret = 0; 2422 2423 if (!drm_enc) { 2424 DPU_ERROR("invalid encoder\n"); 2425 return -EINVAL; 2426 } 2427 dpu_enc = to_dpu_encoder_virt(drm_enc); 2428 DPU_DEBUG_ENC(dpu_enc, "\n"); 2429 2430 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2431 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2432 2433 switch (event) { 2434 case MSM_ENC_COMMIT_DONE: 2435 fn_wait = phys->ops.wait_for_commit_done; 2436 break; 2437 case MSM_ENC_TX_COMPLETE: 2438 fn_wait = phys->ops.wait_for_tx_complete; 2439 break; 2440 case MSM_ENC_VBLANK: 2441 fn_wait = phys->ops.wait_for_vblank; 2442 break; 2443 default: 2444 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2445 event); 2446 return -EINVAL; 2447 } 2448 2449 if (fn_wait) { 2450 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2451 ret = fn_wait(phys); 2452 DPU_ATRACE_END("wait_for_completion_event"); 2453 if (ret) 2454 return ret; 2455 } 2456 } 2457 2458 return ret; 2459 } 2460 2461 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2462 { 2463 struct dpu_encoder_virt *dpu_enc = NULL; 2464 2465 if (!encoder) { 2466 DPU_ERROR("invalid encoder\n"); 2467 return INTF_MODE_NONE; 2468 } 2469 dpu_enc = to_dpu_encoder_virt(encoder); 2470 2471 if (dpu_enc->cur_master) 2472 return dpu_enc->cur_master->intf_mode; 2473 2474 if (dpu_enc->num_phys_encs) 2475 return dpu_enc->phys_encs[0]->intf_mode; 2476 2477 return INTF_MODE_NONE; 2478 } 2479 2480 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2481 { 2482 struct drm_encoder *encoder = phys_enc->parent; 2483 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2484 2485 return dpu_enc->dsc_mask; 2486 } 2487 2488 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2489 struct dpu_enc_phys_init_params *p) 2490 { 2491 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2492 phys_enc->hw_intf = p->hw_intf; 2493 phys_enc->hw_wb = p->hw_wb; 2494 phys_enc->parent = p->parent; 2495 phys_enc->dpu_kms = p->dpu_kms; 2496 phys_enc->split_role = p->split_role; 2497 phys_enc->enc_spinlock = p->enc_spinlock; 2498 phys_enc->enable_state = DPU_ENC_DISABLED; 2499 2500 atomic_set(&phys_enc->vblank_refcount, 0); 2501 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2502 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2503 2504 atomic_set(&phys_enc->vsync_cnt, 0); 2505 atomic_set(&phys_enc->underrun_cnt, 0); 2506 2507 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2508 } 2509