xref: /linux/drivers/gpu/drm/msm/adreno/adreno_gpu.h (revision c5dbf04160005e07e8ca7232a7faa77ab1547ae0)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 /**
33  * @enum adreno_family: identify generation and possibly sub-generation
34  *
35  * In some cases there are distinct sub-generations within a major revision
36  * so it helps to be able to group the GPU devices by generation and if
37  * necessary sub-generation.
38  */
39 enum adreno_family {
40 	ADRENO_2XX_GEN1,  /* a20x */
41 	ADRENO_2XX_GEN2,  /* a22x */
42 	ADRENO_3XX,
43 	ADRENO_4XX,
44 	ADRENO_5XX,
45 	ADRENO_6XX_GEN1,  /* a630 family */
46 	ADRENO_6XX_GEN2,  /* a640 family */
47 	ADRENO_6XX_GEN3,  /* a650 family */
48 	ADRENO_6XX_GEN4,  /* a660 family */
49 	ADRENO_7XX_GEN1,  /* a730 family */
50 	ADRENO_7XX_GEN2,  /* a740 family */
51 };
52 
53 #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
54 #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
55 #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
56 #define ADRENO_QUIRK_HAS_HW_APRIV		BIT(3)
57 #define ADRENO_QUIRK_HAS_CACHED_COHERENT	BIT(4)
58 
59 /* Helper for formating the chip_id in the way that userspace tools like
60  * crashdec expect.
61  */
62 #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
63 #define ADRENO_CHIPID_ARGS(_c) \
64 	(((_c) >> 24) & 0xff), \
65 	(((_c) >> 16) & 0xff), \
66 	(((_c) >> 8)  & 0xff), \
67 	((_c) & 0xff)
68 
69 struct adreno_gpu_funcs {
70 	struct msm_gpu_funcs base;
71 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
72 };
73 
74 struct adreno_reglist {
75 	u32 offset;
76 	u32 value;
77 };
78 
79 extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
80 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
81 
82 struct adreno_speedbin {
83 	uint16_t fuse;
84 	uint16_t speedbin;
85 };
86 
87 struct adreno_info {
88 	const char *machine;
89 	/**
90 	 * @chipids: Table of matching chip-ids
91 	 *
92 	 * Terminated with 0 sentinal
93 	 */
94 	uint32_t *chip_ids;
95 	enum adreno_family family;
96 	uint32_t revn;
97 	const char *fw[ADRENO_FW_MAX];
98 	uint32_t gmem;
99 	u64 quirks;
100 	struct msm_gpu *(*init)(struct drm_device *dev);
101 	const char *zapfw;
102 	u32 inactive_period;
103 	const struct adreno_reglist *hwcg;
104 	u64 address_space_size;
105 	/**
106 	 * @speedbins: Optional table of fuse to speedbin mappings
107 	 *
108 	 * Consists of pairs of fuse, index mappings, terminated with
109 	 * {SHRT_MAX, 0} sentinal.
110 	 */
111 	struct adreno_speedbin *speedbins;
112 };
113 
114 #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
115 
116 /*
117  * Helper to build a speedbin table, ie. the table:
118  *      fuse | speedbin
119  *      -----+---------
120  *        0  |   0
121  *       169 |   1
122  *       174 |   2
123  *
124  * would be declared as:
125  *
126  *     .speedbins = ADRENO_SPEEDBINS(
127  *                      { 0,   0 },
128  *                      { 169, 1 },
129  *                      { 174, 2 },
130  *     ),
131  */
132 #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
133 
134 struct adreno_gpu {
135 	struct msm_gpu base;
136 	const struct adreno_info *info;
137 	uint32_t chip_id;
138 	uint16_t speedbin;
139 	const struct adreno_gpu_funcs *funcs;
140 
141 	/* interesting register offsets to dump: */
142 	const unsigned int *registers;
143 
144 	/*
145 	 * Are we loading fw from legacy path?  Prior to addition
146 	 * of gpu firmware to linux-firmware, the fw files were
147 	 * placed in toplevel firmware directory, following qcom's
148 	 * android kernel.  But linux-firmware preferred they be
149 	 * placed in a 'qcom' subdirectory.
150 	 *
151 	 * For backwards compatibility, we try first to load from
152 	 * the new path, using request_firmware_direct() to avoid
153 	 * any potential timeout waiting for usermode helper, then
154 	 * fall back to the old path (with direct load).  And
155 	 * finally fall back to request_firmware() with the new
156 	 * path to allow the usermode helper.
157 	 */
158 	enum {
159 		FW_LOCATION_UNKNOWN = 0,
160 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
161 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
162 		FW_LOCATION_HELPER,
163 	} fwloc;
164 
165 	/* firmware: */
166 	const struct firmware *fw[ADRENO_FW_MAX];
167 
168 	/*
169 	 * Register offsets are different between some GPUs.
170 	 * GPU specific offsets will be exported by GPU specific
171 	 * code (a3xx_gpu.c) and stored in this common location.
172 	 */
173 	const unsigned int *reg_offsets;
174 	bool gmu_is_wrapper;
175 };
176 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
177 
178 struct adreno_ocmem {
179 	struct ocmem *ocmem;
180 	unsigned long base;
181 	void *hdl;
182 };
183 
184 /* platform config data (ie. from DT, or pdata) */
185 struct adreno_platform_config {
186 	uint32_t chip_id;
187 	const struct adreno_info *info;
188 };
189 
190 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
191 
192 #define spin_until(X) ({                                   \
193 	int __ret = -ETIMEDOUT;                            \
194 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
195 	do {                                               \
196 		if (X) {                                   \
197 			__ret = 0;                         \
198 			break;                             \
199 		}                                          \
200 	} while (time_before(jiffies, __t));               \
201 	__ret;                                             \
202 })
203 
204 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
205 {
206 	/* It is probably ok to assume legacy "adreno_rev" format
207 	 * for all a6xx devices, but probably best to limit this
208 	 * to older things.
209 	 */
210 	WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
211 	return gpu->chip_id & 0xff;
212 }
213 
214 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
215 {
216 	if (WARN_ON_ONCE(!gpu->info))
217 		return false;
218 	return gpu->info->revn == revn;
219 }
220 
221 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
222 {
223 	return gpu->gmu_is_wrapper;
224 }
225 
226 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
227 {
228 	if (WARN_ON_ONCE(!gpu->info))
229 		return false;
230 	return gpu->info->family <= ADRENO_2XX_GEN2;
231 }
232 
233 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
234 {
235 	if (WARN_ON_ONCE(!gpu->info))
236 		return false;
237 	return gpu->info->family == ADRENO_2XX_GEN1;
238 }
239 
240 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
241 {
242 	return adreno_is_revn(gpu, 225);
243 }
244 
245 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
246 {
247 	return adreno_is_revn(gpu, 305);
248 }
249 
250 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
251 {
252 	/* yes, 307, because a305c is 306 */
253 	return adreno_is_revn(gpu, 307);
254 }
255 
256 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
257 {
258 	return adreno_is_revn(gpu, 320);
259 }
260 
261 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
262 {
263 	return adreno_is_revn(gpu, 330);
264 }
265 
266 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
267 {
268 	return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
269 }
270 
271 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
272 {
273 	return adreno_is_revn(gpu, 405);
274 }
275 
276 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
277 {
278 	return adreno_is_revn(gpu, 420);
279 }
280 
281 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
282 {
283 	return adreno_is_revn(gpu, 430);
284 }
285 
286 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
287 {
288 	return adreno_is_revn(gpu, 506);
289 }
290 
291 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
292 {
293 	return adreno_is_revn(gpu, 508);
294 }
295 
296 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
297 {
298 	return adreno_is_revn(gpu, 509);
299 }
300 
301 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
302 {
303 	return adreno_is_revn(gpu, 510);
304 }
305 
306 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
307 {
308 	return adreno_is_revn(gpu, 512);
309 }
310 
311 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
312 {
313 	return adreno_is_revn(gpu, 530);
314 }
315 
316 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
317 {
318 	return adreno_is_revn(gpu, 540);
319 }
320 
321 static inline int adreno_is_a610(const struct adreno_gpu *gpu)
322 {
323 	return adreno_is_revn(gpu, 610);
324 }
325 
326 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
327 {
328 	return adreno_is_revn(gpu, 618);
329 }
330 
331 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
332 {
333 	return adreno_is_revn(gpu, 619);
334 }
335 
336 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
337 {
338 	return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
339 }
340 
341 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
342 {
343 	return adreno_is_revn(gpu, 630);
344 }
345 
346 static inline int adreno_is_a640(const struct adreno_gpu *gpu)
347 {
348 	return adreno_is_revn(gpu, 640);
349 }
350 
351 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
352 {
353 	return adreno_is_revn(gpu, 650);
354 }
355 
356 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
357 {
358 	return gpu->info->chip_ids[0] == 0x06030500;
359 }
360 
361 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
362 {
363 	return adreno_is_revn(gpu, 660);
364 }
365 
366 static inline int adreno_is_a680(const struct adreno_gpu *gpu)
367 {
368 	return adreno_is_revn(gpu, 680);
369 }
370 
371 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
372 {
373 	return gpu->info->chip_ids[0] == 0x06090000;
374 }
375 
376 /* check for a615, a616, a618, a619 or any a630 derivatives */
377 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
378 {
379 	if (WARN_ON_ONCE(!gpu->info))
380 		return false;
381 	return gpu->info->family == ADRENO_6XX_GEN1;
382 }
383 
384 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
385 {
386 	if (WARN_ON_ONCE(!gpu->info))
387 		return false;
388 	return gpu->info->family == ADRENO_6XX_GEN4;
389 }
390 
391 /* check for a650, a660, or any derivatives */
392 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
393 {
394 	if (WARN_ON_ONCE(!gpu->info))
395 		return false;
396 	return gpu->info->family == ADRENO_6XX_GEN3 ||
397 	       gpu->info->family == ADRENO_6XX_GEN4;
398 }
399 
400 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
401 {
402 	if (WARN_ON_ONCE(!gpu->info))
403 		return false;
404 	return gpu->info->family == ADRENO_6XX_GEN2;
405 }
406 
407 static inline int adreno_is_a730(struct adreno_gpu *gpu)
408 {
409 	return gpu->info->chip_ids[0] == 0x07030001;
410 }
411 
412 static inline int adreno_is_a740(struct adreno_gpu *gpu)
413 {
414 	return gpu->info->chip_ids[0] == 0x43050a01;
415 }
416 
417 /* Placeholder to make future diffs smaller */
418 static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
419 {
420 	if (WARN_ON_ONCE(!gpu->info))
421 		return false;
422 	return gpu->info->family == ADRENO_7XX_GEN2;
423 }
424 
425 static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
426 {
427 	/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
428 	return gpu->info->family == ADRENO_7XX_GEN1 ||
429 	       adreno_is_a740_family(gpu);
430 }
431 
432 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
433 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
434 		     uint32_t param, uint64_t *value, uint32_t *len);
435 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
436 		     uint32_t param, uint64_t value, uint32_t len);
437 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
438 		const char *fwname);
439 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
440 		const struct firmware *fw, u64 *iova);
441 int adreno_hw_init(struct msm_gpu *gpu);
442 void adreno_recover(struct msm_gpu *gpu);
443 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
444 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
445 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
446 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
447 		struct drm_printer *p);
448 #endif
449 void adreno_dump_info(struct msm_gpu *gpu);
450 void adreno_dump(struct msm_gpu *gpu);
451 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
452 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
453 
454 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
455 			  struct adreno_ocmem *ocmem);
456 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
457 
458 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
459 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
460 		int nr_rings);
461 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
462 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
463 
464 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
465 
466 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
467 int adreno_gpu_state_put(struct msm_gpu_state *state);
468 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
469 		bool *encoded);
470 
471 /*
472  * Common helper function to initialize the default address space for arm-smmu
473  * attached targets
474  */
475 struct msm_gem_address_space *
476 adreno_create_address_space(struct msm_gpu *gpu,
477 			    struct platform_device *pdev);
478 
479 struct msm_gem_address_space *
480 adreno_iommu_create_address_space(struct msm_gpu *gpu,
481 				  struct platform_device *pdev,
482 				  unsigned long quirks);
483 
484 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
485 			 struct adreno_smmu_fault_info *info, const char *block,
486 			 u32 scratch[4]);
487 
488 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
489 
490 /*
491  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
492  * out of secure mode
493  */
494 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
495 
496 /* ringbuffer helpers (the parts that are adreno specific) */
497 
498 static inline void
499 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
500 {
501 	adreno_wait_ring(ring, cnt+1);
502 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
503 }
504 
505 /* no-op packet: */
506 static inline void
507 OUT_PKT2(struct msm_ringbuffer *ring)
508 {
509 	adreno_wait_ring(ring, 1);
510 	OUT_RING(ring, CP_TYPE2_PKT);
511 }
512 
513 static inline void
514 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
515 {
516 	adreno_wait_ring(ring, cnt+1);
517 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
518 }
519 
520 static inline u32 PM4_PARITY(u32 val)
521 {
522 	return (0x9669 >> (0xF & (val ^
523 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
524 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
525 		(val >> 28)))) & 1;
526 }
527 
528 /* Maximum number of values that can be executed for one opcode */
529 #define TYPE4_MAX_PAYLOAD 127
530 
531 #define PKT4(_reg, _cnt) \
532 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
533 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
534 
535 static inline void
536 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
537 {
538 	adreno_wait_ring(ring, cnt + 1);
539 	OUT_RING(ring, PKT4(regindx, cnt));
540 }
541 
542 static inline void
543 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
544 {
545 	adreno_wait_ring(ring, cnt + 1);
546 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
547 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
548 }
549 
550 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
551 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
552 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
553 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
554 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
555 
556 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
557 {
558 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
559 }
560 
561 /*
562  * Given a register and a count, return a value to program into
563  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
564  * registers starting at _reg.
565  *
566  * The register base needs to be a multiple of the length. If it is not, the
567  * hardware will quietly mask off the bits for you and shift the size. For
568  * example, if you intend the protection to start at 0x07 for a length of 4
569  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
570  * expose registers you intended to protect!
571  */
572 #define ADRENO_PROTECT_RW(_reg, _len) \
573 	((1 << 30) | (1 << 29) | \
574 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
575 
576 /*
577  * Same as above, but allow reads over the range. For areas of mixed use (such
578  * as performance counters) this allows us to protect a much larger range with a
579  * single register
580  */
581 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
582 	((1 << 29) \
583 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
584 
585 
586 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
587 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
588 		interval, timeout)
589 
590 #endif /* __ADRENO_GPU_H__ */
591